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      1 /*
      2  * CDDL HEADER START
      3  *
      4  * The contents of this file are subject to the terms of the
      5  * Common Development and Distribution License (the "License").
      6  * You may not use this file except in compliance with the License.
      7  *
      8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
      9  * or http://www.opensolaris.org/os/licensing.
     10  * See the License for the specific language governing permissions
     11  * and limitations under the License.
     12  *
     13  * When distributing Covered Code, include this CDDL HEADER in each
     14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
     15  * If applicable, add the following below this CDDL HEADER, with the
     16  * fields enclosed by brackets "[]" replaced with your own identifying
     17  * information: Portions Copyright [yyyy] [name of copyright owner]
     18  *
     19  * CDDL HEADER END
     20  */
     21 
     22 /*
     23  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
     24  * Use is subject to license terms.
     25  */
     26 
     27 #ifndef _SYS_NIAGARAREGS_H
     28 #define	_SYS_NIAGARAREGS_H
     29 
     30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
     31 
     32 #ifdef __cplusplus
     33 extern "C" {
     34 #endif
     35 
     36 /*
     37  * Niagara SPARC Performance Instrumentation Counter
     38  */
     39 #define	PIC0_MASK (((uint64_t)1 << 32) - 1)	/* pic0 in bits 31:0 */
     40 #define	PIC1_SHIFT 32				/* pic1 in bits 64:32 */
     41 
     42 /*
     43  * Niagara SPARC Performance Control Register
     44  */
     45 
     46 #define	CPC_NIAGARA_PCR_PRIVPIC		0
     47 #define	CPC_NIAGARA_PCR_SYS		1
     48 #define	CPC_NIAGARA_PCR_USR		2
     49 
     50 #define	CPC_NIAGARA_PCR_PIC0_SHIFT	4
     51 #define	CPC_NIAGARA_PCR_PIC1_SHIFT	0
     52 #define	CPC_NIAGARA_PCR_PIC0_MASK	UINT64_C(0x7)
     53 #define	CPC_NIAGARA_PCR_PIC1_MASK	UINT64_C(0)
     54 
     55 #define	CPC_NIAGARA_PCR_OVF_MASK	UINT64_C(0x300)
     56 #define	CPC_NIAGARA_PCR_OVF_SHIFT	8
     57 
     58 /*
     59  * Niagara DRAM performance counters
     60  */
     61 #define	NIAGARA_DRAM_BANKS		0x4
     62 
     63 #define	NIAGARA_DRAM_PIC0_SEL_SHIFT	0x4
     64 #define	NIAGARA_DRAM_PIC1_SEL_SHIFT	0x0
     65 
     66 #define	NIAGARA_DRAM_PIC0_SHIFT		0x20
     67 #define	NIAGARA_DRAM_PIC0_MASK		0x7fffffff
     68 #define	NIAGARA_DRAM_PIC1_SHIFT		0x0
     69 #define	NIAGARA_DRAM_PIC1_MASK		0x7fffffff
     70 
     71 /*
     72  * Niagara JBUS performance counters
     73  */
     74 #define	NIAGARA_JBUS_PIC0_SEL_SHIFT	0x4
     75 #define	NIAGARA_JBUS_PIC1_SEL_SHIFT	0x0
     76 
     77 #define	NIAGARA_JBUS_PIC0_SHIFT		0x20
     78 #define	NIAGARA_JBUS_PIC0_MASK		0x7fffffff
     79 #define	NIAGARA_JBUS_PIC1_SHIFT		0x0
     80 #define	NIAGARA_JBUS_PIC1_MASK		0x7fffffff
     81 
     82 
     83 /*
     84  * Hypervisor FAST_TRAP API function numbers to get/set DRAM and
     85  * JBUS performance counters
     86  */
     87 #define	HV_NIAGARA_GETPERF	0x100
     88 #define	HV_NIAGARA_SETPERF	0x101
     89 
     90 /*
     91  * Hypervisor FAST_TRAP API function numbers for Niagara MMU statistics
     92  */
     93 #define	HV_NIAGARA_MMUSTAT_CONF	0x102
     94 #define	HV_NIAGARA_MMUSTAT_INFO	0x103
     95 
     96 /*
     97  * DRAM/JBUS performance counter register numbers for HV_NIAGARA_GETPERF
     98  * and HV_NIAGARA_SETPERF
     99  */
    100 #define	HV_NIAGARA_JBUS_CTL		0x0
    101 #define	HV_NIAGARA_JBUS_COUNT		0x1
    102 #define	HV_NIAGARA_DRAM_CTL0		0x2
    103 #define	HV_NIAGARA_DRAM_COUNT0		0x3
    104 #define	HV_NIAGARA_DRAM_CTL1		0x4
    105 #define	HV_NIAGARA_DRAM_COUNT1		0x5
    106 #define	HV_NIAGARA_DRAM_CTL2		0x6
    107 #define	HV_NIAGARA_DRAM_COUNT2		0x7
    108 #define	HV_NIAGARA_DRAM_CTL3		0x8
    109 #define	HV_NIAGARA_DRAM_COUNT3		0x9
    110 
    111 #ifndef _ASM
    112 
    113 /*
    114  * Niagara MMU statistics data structure
    115  */
    116 
    117 #define	NIAGARA_MMUSTAT_PGSZS	8
    118 
    119 typedef struct niagara_tsbinfo {
    120 	uint64_t	tsbhit_count;
    121 	uint64_t	tsbhit_time;
    122 } niagara_tsbinfo_t;
    123 
    124 typedef struct niagara_mmustat {
    125 	niagara_tsbinfo_t	kitsb[NIAGARA_MMUSTAT_PGSZS];
    126 	niagara_tsbinfo_t	uitsb[NIAGARA_MMUSTAT_PGSZS];
    127 	niagara_tsbinfo_t	kdtsb[NIAGARA_MMUSTAT_PGSZS];
    128 	niagara_tsbinfo_t	udtsb[NIAGARA_MMUSTAT_PGSZS];
    129 } niagara_mmustat_t;
    130 
    131 
    132 /*
    133  * prototypes for hypervisor interface to get/set DRAM and JBUS
    134  * performance counters
    135  */
    136 extern uint64_t hv_niagara_setperf(uint64_t regnum, uint64_t val);
    137 extern uint64_t hv_niagara_getperf(uint64_t regnum, uint64_t *val);
    138 extern uint64_t hv_niagara_mmustat_conf(uint64_t buf, uint64_t *prev_buf);
    139 extern uint64_t hv_niagara_mmustat_info(uint64_t *buf);
    140 
    141 #endif /* _ASM */
    142 
    143 /*
    144  * Bits defined in L2 Error Status Register
    145  *
    146  *	(Niagara 1)
    147  * +---+---+---+---+----+----+----+----+----+----+----+----+----+----+
    148  * |MEU|MEC|RW |RSV|MODA|VCID|LDAC|LDAU|LDWC|LDWU|LDRC|LDRU|LDSC|LDSU|
    149  * +---+---+---+---+----+----+----+----+----+----+----+----+----+----+
    150  *  63  62  61  60   59 58-54  53   52   51   50   49   48   47   46
    151  *
    152  *	(Niagara 2)
    153  * +---+---+---+----+--------+----+----+----+----+----+----+----+----+
    154  * |MEU|MEC|RW |MODA|  VCID  |LDAC|LDAU|LDWC|LDWU|LDRC|LDRU|LDSC|LDSU|
    155  * +---+---+---+----+--------+----+----+----+----+----+----+----+----+
    156  *  63  62  61  60     59-54   53   52   51   50   49   48   47   46
    157  *
    158  *      (Niagara 1)
    159  * +---+---+---+---+---+---+---+---+---+---+---+-------+------+
    160  * |LTC|LRU|LVU|DAC|DAU|DRC|DRU|DSC|DSU|VEC|VEU| RSVD1 | SYND |
    161  * +---+---+---+---+---+---+---+---+---+---+---+-------+------+
    162  *  45  44  43  42  41  40  39  38  37  36  35   34-32   31-0
    163  *
    164  *      (Niagara 2)
    165  * +---+---+---+---+---+---+---+---+---+---+---+---+----+-----+
    166  * |LTC|LRU|LVU|DAC|DAU|DRC|DRU|DSC|DSU|VEC|VEU|LVC|RSVD| SYND|
    167  * +---+---+---+---+---+---+---+---+---+---+---+---+----+-----+
    168  *  45  44  43  42  41  40  39  38  37  36  35  34  33-28 27-0
    169  *
    170  * Note that relative to error status bits, Niagara-1 is a strict subset of
    171  * Niagara-2.
    172  */
    173 
    174 #define	NI_L2AFSR_MEU 	0x8000000000000000ULL
    175 #define	NI_L2AFSR_MEC	0x4000000000000000ULL
    176 #define	NI_L2AFSR_RW 	0x2000000000000000ULL
    177 #define	NI2_L2AFSR_MODA	0x1000000000000000ULL
    178 #define	NI1_L2AFSR_MODA	0x0800000000000000ULL
    179 #define	NI_L2AFSR_VCID	0x07C0000000000000ULL
    180 #define	NI_L2AFSR_LDAC	0x0020000000000000ULL
    181 #define	NI_L2AFSR_LDAU	0x0010000000000000ULL
    182 #define	NI_L2AFSR_LDWC	0x0008000000000000ULL
    183 #define	NI_L2AFSR_LDWU	0x0004000000000000ULL
    184 #define	NI_L2AFSR_LDRC	0x0002000000000000ULL
    185 #define	NI_L2AFSR_LDRU	0x0001000000000000ULL
    186 #define	NI_L2AFSR_LDSC	0x0000800000000000ULL
    187 #define	NI_L2AFSR_LDSU	0x0000400000000000ULL
    188 #define	NI_L2AFSR_LTC	0x0000200000000000ULL
    189 #define	NI_L2AFSR_LRU	0x0000100000000000ULL
    190 #define	NI_L2AFSR_LVU	0x0000080000000000ULL
    191 #define	NI_L2AFSR_DAC	0x0000040000000000ULL
    192 #define	NI_L2AFSR_DAU	0x0000020000000000ULL
    193 #define	NI_L2AFSR_DRC	0x0000010000000000ULL
    194 #define	NI_L2AFSR_DRU	0x0000008000000000ULL
    195 #define	NI_L2AFSR_DSC	0x0000004000000000ULL
    196 #define	NI_L2AFSR_DSU	0x0000002000000000ULL
    197 #define	NI_L2AFSR_VEC	0x0000001000000000ULL
    198 #define	NI_L2AFSR_VEU	0x0000000800000000ULL
    199 #define	NI_L2AFSR_LVC	0x0000000400000000ULL
    200 #define	NI1_L2AFSR_SYND	0x00000000FFFFFFFFULL
    201 #define	NI2_L2AFSR_SYND	0x000000000FFFFFFFULL
    202 
    203 /*
    204  * These L2 bit masks are used to determine if another bit of higher priority
    205  * is set.  This tells us whether the reported syndrome and address are valid
    206  * for this ereport. If the error in hand is Pn, use Pn-1 to bitwise & with
    207  * the l2-afsr value.  If result is 0, then this ereport's afsr is valid.
    208  */
    209 #define	NI_L2AFSR_P01	(NI_L2AFSR_LVU)
    210 #define	NI_L2AFSR_P02	(NI_L2AFSR_P01 | NI_L2AFSR_LRU)
    211 #define	NI_L2AFSR_P03	(NI_L2AFSR_P02 | NI_L2AFSR_LDAU | NI_L2AFSR_LDSU)
    212 #define	NI_L2AFSR_P04	(NI_L2AFSR_P03 | NI_L2AFSR_LDWU)
    213 #define	NI_L2AFSR_P05	(NI_L2AFSR_P04 | NI_L2AFSR_LDRU)
    214 #define	NI_L2AFSR_P06	(NI_L2AFSR_P05 | NI_L2AFSR_DAU | NI_L2AFSR_DRU)
    215 #define	NI_L2AFSR_P07   (NI_L2AFSR_P06 | NI_L2AFSR_LVC)
    216 #define	NI_L2AFSR_P08	(NI_L2AFSR_P07 | NI_L2AFSR_LTC)
    217 #define	NI_L2AFSR_P09	(NI_L2AFSR_P08 | NI_L2AFSR_LDAC | NI_L2AFSR_LDSC)
    218 #define	NI_L2AFSR_P10	(NI_L2AFSR_P09 | NI_L2AFSR_LDWC)
    219 #define	NI_L2AFSR_P11	(NI_L2AFSR_P10 | NI_L2AFSR_LDRC)
    220 #define	NI_L2AFSR_P12	(NI_L2AFSR_P11 | NI_L2AFSR_DAC | NI_L2AFSR_DRC)
    221 
    222 /*
    223  * Bits defined in DRAM Error Status Register (Niagara-2)
    224  * Niagara-1 is strict subset
    225  *
    226  * +---+---+---+---+---+---+---+---+---+---+----------+------+
    227  * |MEU|MEC|DAC|DAU|DSC|DSU|DBU|MEB|FBU|FBR| RESERVED | SYND |
    228  * +---+---+---+---+---+---+---+---+---+---+----------+------+
    229  *  63  62  61  60  59  58  57  56  55  54    53-16     15-0
    230  *
    231  */
    232 #define	NI_DMAFSR_MEU 	0x8000000000000000ULL
    233 #define	NI_DMAFSR_MEC	0x4000000000000000ULL
    234 #define	NI_DMAFSR_DAC 	0x2000000000000000ULL
    235 #define	NI_DMAFSR_DAU	0x1000000000000000ULL
    236 #define	NI_DMAFSR_DSC	0x0800000000000000ULL
    237 #define	NI_DMAFSR_DSU	0x0400000000000000ULL
    238 #define	NI_DMAFSR_DBU	0x0200000000000000ULL
    239 #define	NI_DMAFSR_MEB	0x0100000000000000ULL
    240 #define	NI_DMAFSR_FBU	0x0080000000000000ULL
    241 #define	NI_DMAFSR_FBR	0x0040000000000000ULL
    242 #define	NI_DMAFSR_SYND	0x000000000000FFFFULL
    243 
    244 /* Bit mask for DRAM priority determination */
    245 #define	NI_DMAFSR_P01	(NI_DMAFSR_DSU | NI_DMAFSR_DAU | NI_DMAFSR_FBU)
    246 
    247 /*
    248  * The following is the syndrome value placed in memory
    249  * when an uncorrectable error is written back from L2 cache.
    250  */
    251 #define	NI_DRAM_POISON_SYND_FROM_LDWU		0x1118
    252 #define	N2_DRAM_POISON_SYND_FROM_LDWU		0x8221
    253 
    254 /*
    255  * This L2 poison syndrome is placed on 4 byte checkwords of L2
    256  * when a UE is loaded or DMA'ed into L2
    257  */
    258 #define	NI_L2_POISON_SYND_FROM_DAU		0x3
    259 #define	NI_L2_POISON_SYND_MASK			0x7F
    260 #define	NI_L2_POISON_SYND_SIZE			7
    261 
    262 #ifdef __cplusplus
    263 }
    264 #endif
    265 
    266 #endif /* _SYS_NIAGARAREGS_H */
    267