1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NIAGARA2REGS_H 27 #define _SYS_NIAGARA2REGS_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define MB(n) ((n) * 1024 * 1024) 34 35 #define L2CACHE_SIZE MB(4) 36 #define L2CACHE_LINESIZE 64 37 #define L2CACHE_ASSOCIATIVITY 16 38 39 #define NIAGARA2_HSVC_MAJOR 1 40 #define NIAGARA2_HSVC_MINOR 0 41 42 #define VFALLS_HSVC_MAJOR 1 43 #define VFALLS_HSVC_MINOR 0 44 45 #define KT_HSVC_MAJOR 1 46 #define KT_HSVC_MINOR 0 47 48 #ifdef KT_IMPL 49 50 /* Sample PIC overflow range is -2 to -1 */ 51 #define SAMPLE_PIC_IN_OV_RANGE(x) (((uint32_t)x >= 0xfffffffe) ? 1 : 0) 52 53 #endif 54 55 /* PIC overflow range is -16 to -1 */ 56 #define PIC_IN_OV_RANGE(x) (((uint32_t)x >= 0xfffffff0) ? 1 : 0) 57 58 /* 59 * SPARC Performance Instrumentation Counter 60 */ 61 #define PIC0_MASK (((uint64_t)1 << 32) - 1) /* pic0 in bits 31:0 */ 62 #define PIC1_SHIFT 32 /* pic1 in bits 64:32 */ 63 64 /* 65 * SPARC Performance Control Register 66 */ 67 #define CPC_PCR_PRIV_SHIFT 0 68 #define CPC_PCR_ST_SHIFT 1 69 #define CPC_PCR_UT_SHIFT 2 70 71 #define CPC_PCR_HT_SHIFT 3 72 #define CPC_PCR_HT (1ull << CPC_PCR_HT_SHIFT) 73 74 #define CPC_PCR_TOE0_SHIFT 4 75 #define CPC_PCR_TOE1_SHIFT 5 76 #define CPC_PCR_TOE0 (1ull << CPC_PCR_TOE0_SHIFT) 77 #define CPC_PCR_TOE1 (1ull << CPC_PCR_TOE1_SHIFT) 78 79 #define CPC_PCR_PIC0_SHIFT 6 80 #define CPC_PCR_PIC1_SHIFT 19 81 #define CPC_PCR_PIC0_MASK UINT64_C(0xfff) 82 #define CPC_PCR_PIC1_MASK UINT64_C(0xfff) 83 84 #define CPC_PCR_OV0_SHIFT 18 85 #define CPC_PCR_OV1_SHIFT 30 86 #define CPC_PCR_OV0_MASK UINT64_C(0x40000) 87 #define CPC_PCR_OV1_MASK UINT64_C(0x80000000) 88 89 #if defined(KT_IMPL) 90 91 #define CPC_PCR_SAMPLE_MODE_SHIFT 32 92 #define CPC_PCR_SAMPLE_MODE_MASK (1ull << CPC_PCR_SAMPLE_MODE_SHIFT) 93 94 #endif 95 96 #define CPC_PCR_HOLDOV0_SHIFT 62 97 #define CPC_PCR_HOLDOV1_SHIFT 63 98 #define CPC_PCR_HOLDOV0 (1ull << CPC_PCR_HOLDOV0_SHIFT) 99 #define CPC_PCR_HOLDOV1 (1ull << CPC_PCR_HOLDOV1_SHIFT) 100 101 /* 102 * Hypervisor FAST_TRAP API function numbers to get/set DRAM 103 * performance counters for Niagara2 104 */ 105 #define HV_NIAGARA2_GETPERF 0x104 106 #define HV_NIAGARA2_SETPERF 0x105 107 108 /* 109 * Hypervisor FAST_TRAP API function numbers to get/set DRAM 110 * performance counters for Victoria Falls 111 */ 112 #define HV_VFALLS_GETPERF 0x106 113 #define HV_VFALLS_SETPERF 0x107 114 115 /* 116 * Hypervisor FAST_TRAP API function numbers to get/set DRAM 117 * performance counters for KT 118 */ 119 #define HV_KT_GETPERF 0x122 120 #define HV_KT_SETPERF 0x123 121 122 #if defined(KT_IMPL) 123 124 /* 125 * KT DRAM performance counters 126 */ 127 #define DRAM_PIC0_SEL_SHIFT 0x0 128 #define DRAM_PIC1_SEL_SHIFT 0x4 129 130 #define DRAM_PIC0_SHIFT 0x0 131 #define DRAM_PIC0_MASK 0x7fffffff 132 #define DRAM_PIC1_SHIFT 0x20 133 #define DRAM_PIC1_MASK 0x7fffffff 134 135 #else 136 137 /* 138 * Niagara2 and VF DRAM performance counters 139 */ 140 #define DRAM_PIC0_SEL_SHIFT 0x4 141 #define DRAM_PIC1_SEL_SHIFT 0x0 142 143 #define DRAM_PIC0_SHIFT 0x20 144 #define DRAM_PIC0_MASK 0x7fffffff 145 #define DRAM_PIC1_SHIFT 0x0 146 #define DRAM_PIC1_MASK 0x7fffffff 147 148 #endif 149 150 #if defined(NIAGARA2_IMPL) 151 /* 152 * SPARC/DRAM performance counter register numbers for HV_NIAGARA2_GETPERF 153 * and HV_NIAGARA2_SETPERF for Niagara2 154 */ 155 #define DRAM_BANKS 0x4 156 157 #define HV_SPARC_CTL 0x0 158 #define HV_DRAM_CTL0 0x1 159 #define HV_DRAM_COUNT0 0x2 160 #define HV_DRAM_CTL1 0x3 161 #define HV_DRAM_COUNT1 0x4 162 #define HV_DRAM_CTL2 0x5 163 #define HV_DRAM_COUNT2 0x6 164 #define HV_DRAM_CTL3 0x7 165 #define HV_DRAM_COUNT3 0x8 166 167 #elif defined(VFALLS_IMPL) 168 /* 169 * SPARC/DRAM performance counter register numbers for HV_VFALLS_GETPERF 170 * and HV_VFALLS_SETPERF for Victoria Falls 171 * Support for 4-node configuration 172 */ 173 #define DRAM_BANKS 0x8 174 175 #define HV_SPARC_CTL 0x0 176 #define HV_L2_CTL 0x1 177 #define HV_DRAM_CTL0 0x2 178 #define HV_DRAM_COUNT0 0x3 179 #define HV_DRAM_CTL1 0x4 180 #define HV_DRAM_COUNT1 0x5 181 #define HV_DRAM_CTL2 0x6 182 #define HV_DRAM_COUNT2 0x7 183 #define HV_DRAM_CTL3 0x8 184 #define HV_DRAM_COUNT3 0x9 185 #define HV_DRAM_CTL4 0xa 186 #define HV_DRAM_COUNT4 0xb 187 #define HV_DRAM_CTL5 0xc 188 #define HV_DRAM_COUNT5 0xd 189 #define HV_DRAM_CTL6 0xe 190 #define HV_DRAM_COUNT6 0xf 191 #define HV_DRAM_CTL7 0x10 192 #define HV_DRAM_COUNT7 0x11 193 194 #define L2_CTL_MASK 0x3 195 #define SL3_MASK 0x300 196 197 #elif defined(KT_IMPL) 198 /* 199 * SPARC/DRAM performance counter register numbers for HV_KT_GETPERF 200 * and HV_KT_SETPERF for KT 201 * Support for 4-node configuration 202 */ 203 204 #define DRAM_BANKS 0x8 205 206 #define HV_SPARC_CTL 0x0 207 #define HV_L2_CTL 0x1 208 #define HV_DRAM_CTL0 0x2 209 #define HV_DRAM_COUNT0 0x3 210 #define HV_DRAM_CTL1 0x5 211 #define HV_DRAM_COUNT1 0x6 212 #define HV_DRAM_CTL2 0x8 213 #define HV_DRAM_COUNT2 0x9 214 #define HV_DRAM_CTL3 0xb 215 #define HV_DRAM_COUNT3 0xc 216 #define HV_DRAM_CTL4 0xe 217 #define HV_DRAM_COUNT4 0xf 218 #define HV_DRAM_CTL5 0x11 219 #define HV_DRAM_COUNT5 0x12 220 #define HV_DRAM_CTL6 0x14 221 #define HV_DRAM_COUNT6 0x15 222 #define HV_DRAM_CTL7 0x17 223 #define HV_DRAM_COUNT7 0x18 224 225 #define L2_CTL_MASK 0x3 226 #define SL3_MASK 0x300 227 228 #endif 229 230 #ifdef VFALLS_IMPL 231 /* 232 * Performance counters for Zambezi. Zambezi is only supported with 233 * Victoria Falls (UltraSPARC-T2+). 234 */ 235 236 #define ZAMBEZI_PIC0_SEL_SHIFT 0x0 237 #define ZAMBEZI_PIC1_SEL_SHIFT 0x8 238 239 #define ZAMBEZI_LPU_COUNTERS 0x10 240 #define ZAMBEZI_GPD_COUNTERS 0x4 241 #define ZAMBEZI_ASU_COUNTERS 0x4 242 243 #define HV_ZAM0_LPU_A_PCR 0x12 244 #define HV_ZAM0_LPU_A_PIC0 0x13 245 #define HV_ZAM0_LPU_A_PIC1 0x14 246 #define HV_ZAM0_LPU_B_PCR 0x15 247 #define HV_ZAM0_LPU_B_PIC0 0x16 248 #define HV_ZAM0_LPU_B_PIC1 0x17 249 #define HV_ZAM0_LPU_C_PCR 0x18 250 #define HV_ZAM0_LPU_C_PIC0 0x19 251 #define HV_ZAM0_LPU_C_PIC1 0x1a 252 #define HV_ZAM0_LPU_D_PCR 0x1b 253 #define HV_ZAM0_LPU_D_PIC0 0x1c 254 #define HV_ZAM0_LPU_D_PIC1 0x1d 255 #define HV_ZAM0_GPD_PCR 0x1e 256 #define HV_ZAM0_GPD_PIC0 0x1f 257 #define HV_ZAM0_GPD_PIC1 0x20 258 #define HV_ZAM0_ASU_PCR 0x21 259 #define HV_ZAM0_ASU_PIC0 0x22 260 #define HV_ZAM0_ASU_PIC1 0x23 261 262 #define HV_ZAM1_LPU_A_PCR 0x24 263 #define HV_ZAM1_LPU_A_PIC0 0x25 264 #define HV_ZAM1_LPU_A_PIC1 0x26 265 #define HV_ZAM1_LPU_B_PCR 0x27 266 #define HV_ZAM1_LPU_B_PIC0 0x28 267 #define HV_ZAM1_LPU_B_PIC1 0x29 268 #define HV_ZAM1_LPU_C_PCR 0x2a 269 #define HV_ZAM1_LPU_C_PIC0 0x2b 270 #define HV_ZAM1_LPU_C_PIC1 0x2c 271 #define HV_ZAM1_LPU_D_PCR 0x2d 272 #define HV_ZAM1_LPU_D_PIC0 0x2e 273 #define HV_ZAM1_LPU_D_PIC1 0x2f 274 #define HV_ZAM1_GPD_PCR 0x30 275 #define HV_ZAM1_GPD_PIC0 0x31 276 #define HV_ZAM1_GPD_PIC1 0x32 277 #define HV_ZAM1_ASU_PCR 0x33 278 #define HV_ZAM1_ASU_PIC0 0x34 279 #define HV_ZAM1_ASU_PIC1 0x35 280 281 #define HV_ZAM2_LPU_A_PCR 0x36 282 #define HV_ZAM2_LPU_A_PIC0 0x37 283 #define HV_ZAM2_LPU_A_PIC1 0x38 284 #define HV_ZAM2_LPU_B_PCR 0x39 285 #define HV_ZAM2_LPU_B_PIC0 0x3a 286 #define HV_ZAM2_LPU_B_PIC1 0x3b 287 #define HV_ZAM2_LPU_C_PCR 0x3c 288 #define HV_ZAM2_LPU_C_PIC0 0x3d 289 #define HV_ZAM2_LPU_C_PIC1 0x3e 290 #define HV_ZAM2_LPU_D_PCR 0x3f 291 #define HV_ZAM2_LPU_D_PIC0 0x40 292 #define HV_ZAM2_LPU_D_PIC1 0x41 293 #define HV_ZAM2_GPD_PCR 0x42 294 #define HV_ZAM2_GPD_PIC0 0x43 295 #define HV_ZAM2_GPD_PIC1 0x44 296 #define HV_ZAM2_ASU_PCR 0x45 297 #define HV_ZAM2_ASU_PIC0 0x46 298 #define HV_ZAM2_ASU_PIC1 0x47 299 300 #define HV_ZAM3_LPU_A_PCR 0x48 301 #define HV_ZAM3_LPU_A_PIC0 0x49 302 #define HV_ZAM3_LPU_A_PIC1 0x4a 303 #define HV_ZAM3_LPU_B_PCR 0x4b 304 #define HV_ZAM3_LPU_B_PIC0 0x4c 305 #define HV_ZAM3_LPU_B_PIC1 0x4d 306 #define HV_ZAM3_LPU_C_PCR 0x4e 307 #define HV_ZAM3_LPU_C_PIC0 0x4f 308 #define HV_ZAM3_LPU_C_PIC1 0x50 309 #define HV_ZAM3_LPU_D_PCR 0x51 310 #define HV_ZAM3_LPU_D_PIC0 0x52 311 #define HV_ZAM3_LPU_D_PIC1 0x53 312 #define HV_ZAM3_GPD_PCR 0x54 313 #define HV_ZAM3_GPD_PIC0 0x55 314 #define HV_ZAM3_GPD_PIC1 0x56 315 #define HV_ZAM3_ASU_PCR 0x57 316 #define HV_ZAM3_ASU_PIC0 0x58 317 #define HV_ZAM3_ASU_PIC1 0x59 318 319 #endif 320 321 #ifndef _ASM 322 /* 323 * prototypes for hypervisor interface to get/set SPARC and DRAM 324 * performance counters 325 */ 326 extern uint64_t hv_niagara_setperf(uint64_t regnum, uint64_t val); 327 extern uint64_t hv_niagara_getperf(uint64_t regnum, uint64_t *val); 328 #endif 329 330 #ifdef __cplusplus 331 } 332 #endif 333 334 #endif /* _SYS_NIAGARA2REGS_H */ 335
Indexes created Wed Feb 10 12:32:28 UTC 2010
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