Home | History | Annotate | Download | only in px
      1 /*
      2  * CDDL HEADER START
      3  *
      4  * The contents of this file are subject to the terms of the
      5  * Common Development and Distribution License (the "License").
      6  * You may not use this file except in compliance with the License.
      7  *
      8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
      9  * or http://www.opensolaris.org/os/licensing.
     10  * See the License for the specific language governing permissions
     11  * and limitations under the License.
     12  *
     13  * When distributing Covered Code, include this CDDL HEADER in each
     14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
     15  * If applicable, add the following below this CDDL HEADER, with the
     16  * fields enclosed by brackets "[]" replaced with your own identifying
     17  * information: Portions Copyright [yyyy] [name of copyright owner]
     18  *
     19  * CDDL HEADER END
     20  */
     21 /*
     22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
     23  * Use is subject to license terms.
     24  */
     25 
     26 #ifndef _SYS_PX_LIB4U_H
     27 #define	_SYS_PX_LIB4U_H
     28 
     29 #ifdef	__cplusplus
     30 extern "C" {
     31 #endif
     32 
     33 /*
     34  * Errors returned.
     35  */
     36 #define	H_EOK			0	/* Successful return */
     37 #define	H_ENOINTR		1	/* Invalid interrupt id */
     38 #define	H_EINVAL		2	/* Invalid argument */
     39 #define	H_ENOACCESS		3	/* No access to resource */
     40 #define	H_EIO			4	/* I/O error */
     41 #define	H_ENOTSUPPORTED		5	/* Function not supported */
     42 #define	H_ENOMAP		6	/* Mapping is not valid, */
     43 					/* no translation exists */
     44 
     45 /*
     46  * Register base definitions.
     47  *
     48  * The specific numeric values for CSR, XBUS, Configuration,
     49  * Interrupt blocks and other register bases.
     50  */
     51 typedef enum {
     52 	PX_REG_CSR = 0,
     53 	PX_REG_XBC,
     54 	PX_REG_CFG,
     55 	PX_REG_IC,
     56 	PX_REG_MAX
     57 } px_reg_bank_t;
     58 
     59 /*
     60  * Registers/state/variables that need to be saved and restored during
     61  * suspend/resume.
     62  *
     63  * SUN4U px specific data structure.
     64  */
     65 
     66 /* Control block soft state structure */
     67 typedef struct px_cb_list {
     68 	px_t			*pxp;
     69 	struct px_cb_list	*next;
     70 } px_cb_list_t;
     71 
     72 /* IO chip type */
     73 typedef enum {
     74 	PX_CHIP_UNIDENTIFIED = 0,
     75 	PX_CHIP_FIRE = 1,
     76 	PX_CHIP_OBERON = 2
     77 } px_chip_type_t;
     78 
     79 #define	PX_CHIP_TYPE(pxu_p)	((pxu_p)->chip_type)
     80 
     81 typedef struct px_cb {
     82 	px_cb_list_t	*pxl;		/* linked list px */
     83 	kmutex_t	cb_mutex;	/* lock for CB */
     84 	sysino_t	sysino;		/* proxy sysino */
     85 	cpuid_t		cpuid;		/* proxy cpuid */
     86 	int		attachcnt;	/* number of attached px */
     87 	uint_t		(*px_cb_func)(caddr_t); /* CB intr dispatcher */
     88 } px_cb_t;
     89 
     90 typedef struct pxu {
     91 	px_chip_type_t	chip_type;
     92 	uint8_t		portid;
     93 	uint16_t	tsb_cookie;
     94 	uint32_t	tsb_size;
     95 	uint64_t	*tsb_vaddr;
     96 	uint64_t	tsb_paddr;	/* Only used for Oberon */
     97 	sysino_t	hp_sysino;	/* Oberon hotplug interrupt */
     98 
     99 	void		*msiq_mapped_p;
    100 	px_cb_t		*px_cb_p;
    101 
    102 	/* Soft state for suspend/resume */
    103 	uint64_t	*pec_config_state;
    104 	uint64_t	*mmu_config_state;
    105 	uint64_t	*ib_intr_map;
    106 	uint64_t	*ib_config_state;
    107 	uint64_t	*xcb_config_state;
    108 	uint64_t	*msiq_config_state;
    109 	uint_t		cpr_flag;
    110 
    111 	/* sun4u specific vars */
    112 	caddr_t			px_address[4];
    113 	ddi_acc_handle_t	px_ac[4];
    114 
    115 	/* PCItool */
    116 	caddr_t		pcitool_addr;
    117 } pxu_t;
    118 
    119 #define	PX2CB(px_p) (((pxu_t *)px_p->px_plat_p)->px_cb_p)
    120 
    121 /* cpr_flag */
    122 #define	PX_NOT_CPR	0
    123 #define	PX_ENTERED_CPR	1
    124 
    125 /*
    126  * Event Queue data structure.
    127  */
    128 typedef	struct eq_rec {
    129 	uint64_t	eq_rec_rsvd0 : 1,	/* DW 0 - 63 */
    130 			eq_rec_fmt_type : 7,	/* DW 0 - 62:56 */
    131 			eq_rec_len : 10,	/* DW 0 - 55:46 */
    132 			eq_rec_addr0 : 14,	/* DW 0 - 45:32 */
    133 			eq_rec_rid : 16,	/* DW 0 - 31:16 */
    134 			eq_rec_data0 : 16;	/* DW 0 - 15:00 */
    135 	uint64_t	eq_rec_addr1 : 48,	/* DW 1 - 63:16 */
    136 			eq_rec_data1 : 16;	/* DW 1 - 15:0 */
    137 	uint64_t	eq_rec_rsvd[6];		/* DW 2-7 */
    138 } eq_rec_t;
    139 
    140 /*
    141  * EQ record type
    142  *
    143  * Upper 4 bits of eq_rec_fmt_type is used
    144  * to identify the EQ record type.
    145  */
    146 #define	EQ_REC_MSG	0x6			/* MSG   - 0x3X */
    147 #define	EQ_REC_MSI32	0xB			/* MSI32 - 0x58 */
    148 #define	EQ_REC_MSI64	0xF			/* MSI64 - 0x78 */
    149 
    150 /* EQ State */
    151 #define	EQ_IDLE_STATE	0x1			/* IDLE */
    152 #define	EQ_ACTIVE_STATE	0x2			/* ACTIVE */
    153 #define	EQ_ERROR_STATE	0x4			/* ERROR */
    154 
    155 /*
    156  * Default EQ Configurations
    157  */
    158 #define	EQ_CNT		36
    159 #define	EQ_REC_CNT	128
    160 #define	EQ_1ST_ID	0
    161 #define	EQ_1ST_DEVINO	24
    162 
    163 #define	MMU_INVALID_TTE		0ull
    164 #define	MMU_TTE_VALID(tte)	(((tte) & MMU_TTE_V) == MMU_TTE_V)
    165 #define	MMU_OBERON_PADDR_MASK	0x7fffffffffff
    166 #define	MMU_FIRE_PADDR_MASK	0x7ffffffffff
    167 
    168 /*
    169  * control register decoding
    170  */
    171 /* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */
    172 #define	MMU_CTL_TO_TSBSIZE(ctl)		((ctl) >> 16)
    173 #define	MMU_TSBSIZE_TO_TSBENTRIES(s)	((1 << (s)) << (13 - 3))
    174 
    175 /*
    176  * For Fire mmu bypass addresses, bit 43 specifies cacheability.
    177  */
    178 #define	MMU_FIRE_BYPASS_NONCACHE	 (1ull << 43)
    179 
    180 /*
    181  * For Oberon mmu bypass addresses, bit 47 specifies cacheability.
    182  */
    183 #define	MMU_OBERON_BYPASS_NONCACHE	 (1ull << 47)
    184 
    185 /*
    186  * The following macros define the address ranges supported for DVMA
    187  * and mmu bypass transfers. For Oberon, bit 63 is used for ordering.
    188  */
    189 #define	MMU_FIRE_BYPASS_BASE		0xFFFC000000000000ull
    190 #define	MMU_FIRE_BYPASS_END		0xFFFC03FFFFFFFFFFull
    191 
    192 #define	MMU_OBERON_BYPASS_BASE		0x7FFC000000000000ull
    193 #define	MMU_OBERON_BYPASS_END		0x7FFC7FFFFFFFFFFFull
    194 
    195 #define	MMU_OBERON_BYPASS_RO		0x8000000000000000ull
    196 
    197 #define	MMU_TSB_PA_MASK		0x7FFFFFFFE000
    198 
    199 /*
    200  * The following macros are for loading and unloading io tte
    201  * entries.
    202  */
    203 #define	MMU_TTE_SIZE		8
    204 #define	MMU_TTE_V		(1ull << 63)
    205 #define	MMU_TTE_W		(1ull << 1)
    206 #define	MMU_TTE_RO		(1ull << 62)	/* Oberon Relaxed Ordering */
    207 
    208 #define	INO_BITS		6	/* INO#s are 6 bits long */
    209 #define	INO_MASK		0x3F	/* INO#s mask */
    210 
    211 #define	SYSINO_TO_DEVINO(sysino)	(sysino & INO_MASK)
    212 
    213 #define	FIRE_IGN_MASK		0x1F	/* IGN#s mask, 5 bits long for Fire */
    214 #define	OBERON_IGN_MASK		0xFF	/* IGN#s mask, 8 bits long for Oberon */
    215 
    216 #define	ID_TO_IGN(chip, portid) ((portid) & ((chip) == PX_CHIP_OBERON ? \
    217 	OBERON_IGN_MASK : FIRE_IGN_MASK))
    218 
    219 #define	DEVINO_TO_SYSINO(portid, devino) \
    220 	(((portid) << INO_BITS) | ((devino) & INO_MASK))
    221 
    222 /* Interrupt states */
    223 #define	INTERRUPT_IDLE_STATE		0
    224 #define	INTERRUPT_RECEIVED_STATE	1
    225 #define	INTERRUPT_PENDING_STATE		3
    226 
    227 /*
    228  * Defines for link width and max packet size for ACKBAK Latency Threshold Timer
    229  * and TxLink Replay Timer Latency Table array sizes
    230  * Num		Link Width		Packet Size
    231  * 0		1			128
    232  * 1		4			256
    233  * 2		8			512
    234  * 3		16			1024
    235  * 4		-			2048
    236  * 5		-			4096
    237  */
    238 #define	LINK_WIDTH_ARR_SIZE		4
    239 #define	LINK_MAX_PKT_ARR_SIZE		6
    240 
    241 /*
    242  * Defines for registers which have multi-bit fields.
    243  */
    244 #define	TLU_LINK_CONTROL_ASPM_DISABLED			0x0
    245 #define	TLU_LINK_CONTROL_ASPM_L0S_EN			0x1
    246 #define	TLU_LINK_CONTROL_ASPM_L1_EN			0x2
    247 #define	TLU_LINK_CONTROL_ASPM_L0S_L1_EN			0x3
    248 
    249 #define	TLU_CONTROL_CONFIG_DEFAULT			0x1
    250 #define	TLU_CONTROL_L0S_TIM_DEFAULT			0xdaull
    251 #define	TLU_CONTROL_MPS_MASK				0x1C
    252 #define	TLU_CONTROL_MPS_SHIFT				2
    253 
    254 #define	LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_0	0x0
    255 #define	LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_1	0x1
    256 #define	LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_2	0x2
    257 #define	LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_3	0x3
    258 
    259 #define	LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT	0xFFFFull
    260 #define	LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT	0x0ull
    261 
    262 #define	LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_CNTR_DEFAULT	0xFFF
    263 #define	LPU_TXLINK_SEQUENCE_COUNTER_NXT_TX_SEQ_CNTR_DEFAULT	0x0
    264 #define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_DEF	0x157
    265 
    266 #define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_TLPTR_DEFAULT	0xFFF
    267 #define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_HDPTR_DEFAULT	0x0
    268 
    269 #define	LPU_LTSSM_CONFIG1_LTSSM_8_TO_DEFAULT		0x2
    270 #define	LPU_LTSSM_CONFIG1_LTSSM_20_TO_DEFAULT		0x5
    271 #define	LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT		0x2DC6C0
    272 #define	LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT		0x7A120
    273 #define	LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT		0x2
    274 #define	LPU_LTSSM_CONFIG4_N_FTS_DEFAULT			0x8c
    275 
    276 /* LPU LTSSM states */
    277 #define	LPU_LTSSM_L0			0x0
    278 #define	LPU_LTSSM_L1_IDLE		0x15
    279 
    280 /* TLU Control register bits */
    281 #define	TLU_REMAIN_DETECT_QUIET		8
    282 
    283 /*
    284  * Fire hardware specific version definitions.
    285  * All Fire versions > 2.0 will be numerically greater than FIRE_MOD_REV_20
    286  */
    287 #define	FIRE_MOD_REV_20	0x03
    288 
    289 /*
    290  * Oberon specific definitions.
    291  */
    292 #define	OBERON_RANGE_PROP_MASK	0x7fff
    293 
    294 /*
    295  * HW specific paddr mask.
    296  */
    297 extern uint64_t px_paddr_mask;
    298 
    299 extern void hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p);
    300 extern void hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p);
    301 extern void hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p);
    302 extern void hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p);
    303 
    304 extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p,
    305     devino_t devino, sysino_t *sysino);
    306 extern uint64_t hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino,
    307     intr_valid_state_t *intr_valid_state);
    308 extern uint64_t hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino,
    309     intr_valid_state_t intr_valid_state);
    310 extern uint64_t hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino,
    311     intr_state_t *intr_state);
    312 extern uint64_t hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino,
    313     intr_state_t intr_state);
    314 extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p,
    315     sysino_t sysino, cpuid_t *cpuid);
    316 extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p,
    317     sysino_t sysino, cpuid_t cpuid);
    318 
    319 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid,
    320     pages_t pages, io_attributes_t attr, void *addr, size_t pfn_index,
    321     int flags);
    322 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p,
    323     tsbid_t tsbid, pages_t pages);
    324 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p,
    325     tsbid_t tsbid, io_attributes_t *attr_p, r_addr_t *r_addr_p);
    326 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p,
    327     r_addr_t ra, io_attributes_t attr, io_addr_t *io_addr_p);
    328 extern uint64_t hvio_get_bypass_base(pxu_t *pxu_p);
    329 extern uint64_t hvio_get_bypass_end(pxu_t *pxu_p);
    330 extern uint64_t px_get_range_prop(px_t *px_p, pci_ranges_t *rp, int bank);
    331 
    332 
    333 /*
    334  * MSIQ Functions:
    335  */
    336 extern uint64_t hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p);
    337 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
    338     pci_msiq_valid_state_t *msiq_valid_state);
    339 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
    340     pci_msiq_valid_state_t msiq_valid_state);
    341 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
    342     pci_msiq_state_t *msiq_state);
    343 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
    344     pci_msiq_state_t msiq_state);
    345 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
    346     msiqhead_t *msiq_head);
    347 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
    348     msiqhead_t msiq_head);
    349 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
    350     msiqtail_t *msiq_tail);
    351 
    352 /*
    353  * MSI Functions:
    354  */
    355 extern uint64_t hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32,
    356     uint64_t addr64);
    357 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num,
    358     msiqid_t *msiq_id);
    359 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num,
    360     msiqid_t msiq_id);
    361 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num,
    362     pci_msi_valid_state_t *msi_valid_state);
    363 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num,
    364     pci_msi_valid_state_t msi_valid_state);
    365 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num,
    366     pci_msi_state_t *msi_state);
    367 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num,
    368     pci_msi_state_t msi_state);
    369 
    370 /*
    371  * MSG Functions:
    372  */
    373 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
    374     msiqid_t *msiq_id);
    375 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
    376     msiqid_t msiq_id);
    377 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
    378     pcie_msg_valid_state_t *msg_valid_state);
    379 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
    380     pcie_msg_valid_state_t msg_valid_state);
    381 
    382 /*
    383  * Suspend/Resume Functions:
    384  */
    385 extern uint64_t hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p);
    386 extern void hvio_resume(devhandle_t dev_hdl,
    387     devino_t devino, pxu_t *pxu_p);
    388 extern uint64_t hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p);
    389 extern void hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl,
    390     devino_t devino, pxu_t *pxu_p);
    391 extern int px_send_pme_turnoff(caddr_t csr_base);
    392 extern int px_link_wait4l1idle(caddr_t csr_base);
    393 extern int px_link_retrain(caddr_t csr_base);
    394 extern void px_enable_detect_quiet(caddr_t csr_base);
    395 
    396 extern void px_lib_clr_errs(px_t *px_p, dev_info_t *rdip, uint64_t addr);
    397 
    398 /*
    399  * Hotplug functions:
    400  */
    401 extern int hvio_hotplug_init(dev_info_t *dip, void *arg);
    402 extern int hvio_hotplug_uninit(dev_info_t *dip);
    403 
    404 #ifdef	__cplusplus
    405 }
    406 #endif
    407 
    408 #endif	/* _SYS_PX_LIB4U_H */
    409