1 1772 jl139090 /* 2 1772 jl139090 * CDDL HEADER START 3 1772 jl139090 * 4 1772 jl139090 * The contents of this file are subject to the terms of the 5 1772 jl139090 * Common Development and Distribution License (the "License"). 6 1772 jl139090 * You may not use this file except in compliance with the License. 7 1772 jl139090 * 8 1772 jl139090 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 1772 jl139090 * or http://www.opensolaris.org/os/licensing. 10 1772 jl139090 * See the License for the specific language governing permissions 11 1772 jl139090 * and limitations under the License. 12 1772 jl139090 * 13 1772 jl139090 * When distributing Covered Code, include this CDDL HEADER in each 14 1772 jl139090 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 1772 jl139090 * If applicable, add the following below this CDDL HEADER, with the 16 1772 jl139090 * fields enclosed by brackets "[]" replaced with your own identifying 17 1772 jl139090 * information: Portions Copyright [yyyy] [name of copyright owner] 18 1772 jl139090 * 19 1772 jl139090 * CDDL HEADER END 20 1772 jl139090 */ 21 1772 jl139090 /* 22 8664 James * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 1772 jl139090 * Use is subject to license terms. 24 5037 jl139090 */ 25 5037 jl139090 26 5037 jl139090 /* 27 5037 jl139090 * Support for Olympus-C (SPARC64-VI) and Jupiter (SPARC64-VII). 28 1772 jl139090 */ 29 1772 jl139090 30 1772 jl139090 #include <sys/types.h> 31 1772 jl139090 #include <sys/systm.h> 32 1772 jl139090 #include <sys/ddi.h> 33 1772 jl139090 #include <sys/sysmacros.h> 34 1772 jl139090 #include <sys/archsystm.h> 35 1772 jl139090 #include <sys/vmsystm.h> 36 1772 jl139090 #include <sys/machparam.h> 37 1772 jl139090 #include <sys/machsystm.h> 38 1772 jl139090 #include <sys/machthread.h> 39 1772 jl139090 #include <sys/cpu.h> 40 1772 jl139090 #include <sys/cmp.h> 41 1772 jl139090 #include <sys/elf_SPARC.h> 42 1772 jl139090 #include <vm/vm_dep.h> 43 1772 jl139090 #include <vm/hat_sfmmu.h> 44 1772 jl139090 #include <vm/seg_kpm.h> 45 3309 jimand #include <vm/seg_kmem.h> 46 1772 jl139090 #include <sys/cpuvar.h> 47 1772 jl139090 #include <sys/opl_olympus_regs.h> 48 1772 jl139090 #include <sys/opl_module.h> 49 1772 jl139090 #include <sys/async.h> 50 1772 jl139090 #include <sys/cmn_err.h> 51 1772 jl139090 #include <sys/debug.h> 52 1772 jl139090 #include <sys/dditypes.h> 53 1772 jl139090 #include <sys/cpu_module.h> 54 1772 jl139090 #include <sys/sysmacros.h> 55 1772 jl139090 #include <sys/intreg.h> 56 1772 jl139090 #include <sys/clock.h> 57 1772 jl139090 #include <sys/platform_module.h> 58 1772 jl139090 #include <sys/ontrap.h> 59 1772 jl139090 #include <sys/panic.h> 60 1772 jl139090 #include <sys/memlist.h> 61 1772 jl139090 #include <sys/ndifm.h> 62 1772 jl139090 #include <sys/ddifm.h> 63 1772 jl139090 #include <sys/fm/protocol.h> 64 1772 jl139090 #include <sys/fm/util.h> 65 1772 jl139090 #include <sys/fm/cpu/SPARC64-VI.h> 66 1772 jl139090 #include <sys/dtrace.h> 67 1772 jl139090 #include <sys/watchpoint.h> 68 1772 jl139090 #include <sys/promif.h> 69 1772 jl139090 70 1772 jl139090 /* 71 1772 jl139090 * Internal functions. 72 1772 jl139090 */ 73 1772 jl139090 static int cpu_sync_log_err(void *flt); 74 1772 jl139090 static void cpu_payload_add_aflt(struct async_flt *, nvlist_t *, nvlist_t *); 75 1772 jl139090 static void opl_cpu_sync_error(struct regs *, ulong_t, ulong_t, uint_t, uint_t); 76 1772 jl139090 static int cpu_flt_in_memory(opl_async_flt_t *, uint64_t); 77 5394 jimand static int prom_SPARC64VII_support_enabled(void); 78 5414 mb158278 static void opl_ta3(); 79 5584 jimand static int plat_prom_preserve_kctx_is_supported(void); 80 1772 jl139090 81 1772 jl139090 /* 82 1772 jl139090 * Error counters resetting interval. 83 1772 jl139090 */ 84 1772 jl139090 static int opl_async_check_interval = 60; /* 1 min */ 85 1772 jl139090 86 2241 huah uint_t cpu_impl_dual_pgsz = 1; 87 1772 jl139090 88 1772 jl139090 /* 89 1772 jl139090 * PA[22:0] represent Displacement in Jupiter 90 1772 jl139090 * configuration space. 91 1772 jl139090 */ 92 1772 jl139090 uint_t root_phys_addr_lo_mask = 0x7fffffu; 93 1772 jl139090 94 1772 jl139090 /* 95 1772 jl139090 * set in /etc/system to control logging of user BERR/TO's 96 1772 jl139090 */ 97 1772 jl139090 int cpu_berr_to_verbose = 0; 98 5037 jl139090 99 5037 jl139090 /* 100 5037 jl139090 * Set to 1 if booted with all Jupiter cpus (all-Jupiter features enabled). 101 5037 jl139090 */ 102 5037 jl139090 int cpu_alljupiter = 0; 103 6127 sm142603 104 6127 sm142603 /* 105 6127 sm142603 * The sfmmu_cext field to be used by processes in a shared context domain. 106 6127 sm142603 */ 107 6127 sm142603 static uchar_t shctx_cext = TAGACCEXT_MKSZPAIR(DEFAULT_ISM_PAGESZC, TTE8K); 108 1772 jl139090 109 1772 jl139090 static int min_ecache_size; 110 1772 jl139090 static uint_t priv_hcl_1; 111 1772 jl139090 static uint_t priv_hcl_2; 112 1772 jl139090 static uint_t priv_hcl_4; 113 1772 jl139090 static uint_t priv_hcl_8; 114 1772 jl139090 115 1772 jl139090 /* 116 1772 jl139090 * Olympus error log 117 1772 jl139090 */ 118 1772 jl139090 static opl_errlog_t *opl_err_log; 119 6259 mb158278 static int opl_cpu0_log_setup; 120 5414 mb158278 121 5414 mb158278 /* 122 5414 mb158278 * OPL ta 3 save area. 123 5414 mb158278 */ 124 5414 mb158278 char *opl_ta3_save; 125 1772 jl139090 126 1772 jl139090 /* 127 1772 jl139090 * UE is classified into four classes (MEM, CHANNEL, CPU, PATH). 128 1772 jl139090 * No any other ecc_type_info insertion is allowed in between the following 129 1772 jl139090 * four UE classess. 130 1772 jl139090 */ 131 1772 jl139090 ecc_type_to_info_t ecc_type_to_info[] = { 132 1772 jl139090 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 133 1772 jl139090 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 134 1772 jl139090 FM_EREPORT_CPU_UE_MEM, 135 1772 jl139090 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 136 1772 jl139090 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 137 1772 jl139090 FM_EREPORT_CPU_UE_CHANNEL, 138 1772 jl139090 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 139 1772 jl139090 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 140 1772 jl139090 FM_EREPORT_CPU_UE_CPU, 141 1772 jl139090 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 142 1772 jl139090 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 143 1772 jl139090 FM_EREPORT_CPU_UE_PATH, 144 1772 jl139090 SFSR_BERR, "BERR ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 145 1772 jl139090 "Bus Error", FM_EREPORT_PAYLOAD_SYNC, 146 1772 jl139090 FM_EREPORT_CPU_BERR, 147 1772 jl139090 SFSR_TO, "TO ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 148 1772 jl139090 "Bus Timeout", FM_EREPORT_PAYLOAD_SYNC, 149 1772 jl139090 FM_EREPORT_CPU_BTO, 150 1772 jl139090 SFSR_TLB_MUL, "TLB_MUL ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 151 1772 jl139090 "TLB MultiHit", FM_EREPORT_PAYLOAD_SYNC, 152 1772 jl139090 FM_EREPORT_CPU_MTLB, 153 1772 jl139090 SFSR_TLB_PRT, "TLB_PRT ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 154 1772 jl139090 "TLB Parity", FM_EREPORT_PAYLOAD_SYNC, 155 1772 jl139090 FM_EREPORT_CPU_TLBP, 156 1772 jl139090 157 1772 jl139090 UGESR_IAUG_CRE, "IAUG_CRE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 158 1772 jl139090 "IAUG CRE", FM_EREPORT_PAYLOAD_URGENT, 159 1772 jl139090 FM_EREPORT_CPU_CRE, 160 1772 jl139090 UGESR_IAUG_TSBCTXT, "IAUG_TSBCTXT", 161 1772 jl139090 OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 162 1772 jl139090 "IAUG TSBCTXT", FM_EREPORT_PAYLOAD_URGENT, 163 1772 jl139090 FM_EREPORT_CPU_TSBCTX, 164 1772 jl139090 UGESR_IUG_TSBP, "IUG_TSBP", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 165 1772 jl139090 "IUG TSBP", FM_EREPORT_PAYLOAD_URGENT, 166 1772 jl139090 FM_EREPORT_CPU_TSBP, 167 1772 jl139090 UGESR_IUG_PSTATE, "IUG_PSTATE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 168 1772 jl139090 "IUG PSTATE", FM_EREPORT_PAYLOAD_URGENT, 169 1772 jl139090 FM_EREPORT_CPU_PSTATE, 170 1772 jl139090 UGESR_IUG_TSTATE, "IUG_TSTATE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 171 1772 jl139090 "IUG TSTATE", FM_EREPORT_PAYLOAD_URGENT, 172 1772 jl139090 FM_EREPORT_CPU_TSTATE, 173 1772 jl139090 UGESR_IUG_F, "IUG_F", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 174 1772 jl139090 "IUG FREG", FM_EREPORT_PAYLOAD_URGENT, 175 1772 jl139090 FM_EREPORT_CPU_IUG_F, 176 1772 jl139090 UGESR_IUG_R, "IUG_R", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 177 1772 jl139090 "IUG RREG", FM_EREPORT_PAYLOAD_URGENT, 178 1772 jl139090 FM_EREPORT_CPU_IUG_R, 179 1772 jl139090 UGESR_AUG_SDC, "AUG_SDC", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 180 1772 jl139090 "AUG SDC", FM_EREPORT_PAYLOAD_URGENT, 181 1772 jl139090 FM_EREPORT_CPU_SDC, 182 1772 jl139090 UGESR_IUG_WDT, "IUG_WDT", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 183 1772 jl139090 "IUG WDT", FM_EREPORT_PAYLOAD_URGENT, 184 1772 jl139090 FM_EREPORT_CPU_WDT, 185 1772 jl139090 UGESR_IUG_DTLB, "IUG_DTLB", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 186 1772 jl139090 "IUG DTLB", FM_EREPORT_PAYLOAD_URGENT, 187 1772 jl139090 FM_EREPORT_CPU_DTLB, 188 1772 jl139090 UGESR_IUG_ITLB, "IUG_ITLB", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 189 1772 jl139090 "IUG ITLB", FM_EREPORT_PAYLOAD_URGENT, 190 1772 jl139090 FM_EREPORT_CPU_ITLB, 191 1772 jl139090 UGESR_IUG_COREERR, "IUG_COREERR", 192 1772 jl139090 OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 193 1772 jl139090 "IUG COREERR", FM_EREPORT_PAYLOAD_URGENT, 194 1772 jl139090 FM_EREPORT_CPU_CORE, 195 1772 jl139090 UGESR_MULTI_DAE, "MULTI_DAE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 196 1772 jl139090 "MULTI DAE", FM_EREPORT_PAYLOAD_URGENT, 197 1772 jl139090 FM_EREPORT_CPU_DAE, 198 1772 jl139090 UGESR_MULTI_IAE, "MULTI_IAE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 199 1772 jl139090 "MULTI IAE", FM_EREPORT_PAYLOAD_URGENT, 200 1772 jl139090 FM_EREPORT_CPU_IAE, 201 1772 jl139090 UGESR_MULTI_UGE, "MULTI_UGE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 202 1772 jl139090 "MULTI UGE", FM_EREPORT_PAYLOAD_URGENT, 203 1772 jl139090 FM_EREPORT_CPU_UGE, 204 1772 jl139090 0, NULL, 0, 0, 205 1772 jl139090 NULL, 0, 0, 206 1772 jl139090 }; 207 1772 jl139090 208 1772 jl139090 int (*p2get_mem_info)(int synd_code, uint64_t paddr, 209 1772 jl139090 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 210 1772 jl139090 int *segsp, int *banksp, int *mcidp); 211 1772 jl139090 212 1772 jl139090 213 1772 jl139090 /* 214 5414 mb158278 * Setup trap handlers for 0xA, 0x32, 0x40 trap types 215 5414 mb158278 * and "ta 3" and "ta 4". 216 1772 jl139090 */ 217 1772 jl139090 void 218 1772 jl139090 cpu_init_trap(void) 219 1772 jl139090 { 220 1772 jl139090 OPL_SET_TRAP(tt0_iae, opl_serr_instr); 221 1772 jl139090 OPL_SET_TRAP(tt1_iae, opl_serr_instr); 222 1772 jl139090 OPL_SET_TRAP(tt0_dae, opl_serr_instr); 223 1772 jl139090 OPL_SET_TRAP(tt1_dae, opl_serr_instr); 224 1772 jl139090 OPL_SET_TRAP(tt0_asdat, opl_ugerr_instr); 225 1772 jl139090 OPL_SET_TRAP(tt1_asdat, opl_ugerr_instr); 226 5414 mb158278 OPL_SET_TRAP(tt0_flushw, opl_ta3_instr); 227 5414 mb158278 OPL_PATCH_28(opl_cleanw_patch, opl_ta4_instr); 228 1772 jl139090 } 229 1772 jl139090 230 1772 jl139090 static int 231 1772 jl139090 getintprop(pnode_t node, char *name, int deflt) 232 1772 jl139090 { 233 1772 jl139090 int value; 234 1772 jl139090 235 1772 jl139090 switch (prom_getproplen(node, name)) { 236 1772 jl139090 case sizeof (int): 237 1772 jl139090 (void) prom_getprop(node, name, (caddr_t)&value); 238 1772 jl139090 break; 239 1772 jl139090 240 1772 jl139090 default: 241 1772 jl139090 value = deflt; 242 1772 jl139090 break; 243 1772 jl139090 } 244 1772 jl139090 245 1772 jl139090 return (value); 246 1772 jl139090 } 247 1772 jl139090 248 1772 jl139090 /* 249 1772 jl139090 * Set the magic constants of the implementation. 250 1772 jl139090 */ 251 1772 jl139090 /*ARGSUSED*/ 252 1772 jl139090 void 253 1772 jl139090 cpu_fiximp(pnode_t dnode) 254 1772 jl139090 { 255 1772 jl139090 int i, a; 256 1772 jl139090 extern int vac_size, vac_shift; 257 1772 jl139090 extern uint_t vac_mask; 258 1772 jl139090 259 1772 jl139090 static struct { 260 1772 jl139090 char *name; 261 1772 jl139090 int *var; 262 1772 jl139090 int defval; 263 1772 jl139090 } prop[] = { 264 1772 jl139090 "l1-dcache-size", &dcache_size, OPL_DCACHE_SIZE, 265 1772 jl139090 "l1-dcache-line-size", &dcache_linesize, OPL_DCACHE_LSIZE, 266 1772 jl139090 "l1-icache-size", &icache_size, OPL_ICACHE_SIZE, 267 1772 jl139090 "l1-icache-line-size", &icache_linesize, OPL_ICACHE_LSIZE, 268 1772 jl139090 "l2-cache-size", &ecache_size, OPL_ECACHE_SIZE, 269 1772 jl139090 "l2-cache-line-size", &ecache_alignsize, OPL_ECACHE_LSIZE, 270 1772 jl139090 "l2-cache-associativity", &ecache_associativity, OPL_ECACHE_NWAY 271 1772 jl139090 }; 272 1772 jl139090 273 1772 jl139090 for (i = 0; i < sizeof (prop) / sizeof (prop[0]); i++) 274 1772 jl139090 *prop[i].var = getintprop(dnode, prop[i].name, prop[i].defval); 275 1772 jl139090 276 1772 jl139090 ecache_setsize = ecache_size / ecache_associativity; 277 1772 jl139090 278 1772 jl139090 vac_size = OPL_VAC_SIZE; 279 1772 jl139090 vac_mask = MMU_PAGEMASK & (vac_size - 1); 280 1772 jl139090 i = 0; a = vac_size; 281 1772 jl139090 while (a >>= 1) 282 1772 jl139090 ++i; 283 1772 jl139090 vac_shift = i; 284 1772 jl139090 shm_alignment = vac_size; 285 1772 jl139090 vac = 1; 286 1772 jl139090 } 287 2149 hyw 288 5037 jl139090 /* 289 5037 jl139090 * Enable features for Jupiter-only domains. 290 5037 jl139090 */ 291 5037 jl139090 void 292 5037 jl139090 cpu_fix_alljupiter(void) 293 5037 jl139090 { 294 5394 jimand if (!prom_SPARC64VII_support_enabled()) { 295 5394 jimand /* 296 5394 jimand * Do not enable all-Jupiter features and do not turn on 297 5394 jimand * the cpu_alljupiter flag. 298 5394 jimand */ 299 5394 jimand return; 300 5394 jimand } 301 5394 jimand 302 5037 jl139090 cpu_alljupiter = 1; 303 5037 jl139090 304 5037 jl139090 /* 305 5037 jl139090 * Enable ima hwcap for Jupiter-only domains. DR will prevent 306 5037 jl139090 * addition of Olympus-C to all-Jupiter domains to preserve ima 307 5037 jl139090 * hwcap semantics. 308 5037 jl139090 */ 309 5037 jl139090 cpu_hwcap_flags |= AV_SPARC_IMA; 310 6127 sm142603 311 6127 sm142603 /* 312 7869 Sean * Enable shared context support. 313 6127 sm142603 */ 314 7869 Sean shctx_on = 1; 315 5037 jl139090 } 316 5037 jl139090 317 2149 hyw #ifdef OLYMPUS_C_REV_B_ERRATA_XCALL 318 2149 hyw /* 319 2149 hyw * Quick and dirty way to redefine locally in 320 2149 hyw * OPL the value of IDSR_BN_SETS to 31 instead 321 2149 hyw * of the standard 32 value. This is to workaround 322 2149 hyw * REV_B of Olympus_c processor's problem in handling 323 2149 hyw * more than 31 xcall broadcast. 324 2149 hyw */ 325 2149 hyw #undef IDSR_BN_SETS 326 2149 hyw #define IDSR_BN_SETS 31 327 2149 hyw #endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */ 328 1772 jl139090 329 1772 jl139090 void 330 1772 jl139090 send_mondo_set(cpuset_t set) 331 1772 jl139090 { 332 1772 jl139090 int lo, busy, nack, shipped = 0; 333 1772 jl139090 uint16_t i, cpuids[IDSR_BN_SETS]; 334 1772 jl139090 uint64_t idsr, nackmask = 0, busymask, curnack, curbusy; 335 1772 jl139090 uint64_t starttick, endtick, tick, lasttick; 336 1772 jl139090 #if (NCPU > IDSR_BN_SETS) 337 1772 jl139090 int index = 0; 338 1772 jl139090 int ncpuids = 0; 339 1772 jl139090 #endif 340 1888 hyw #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 341 1772 jl139090 int bn_sets = IDSR_BN_SETS; 342 1772 jl139090 uint64_t ver; 343 1772 jl139090 344 1772 jl139090 ASSERT(NCPU > bn_sets); 345 1772 jl139090 #endif 346 1772 jl139090 347 1772 jl139090 ASSERT(!CPUSET_ISNULL(set)); 348 1772 jl139090 starttick = lasttick = gettick(); 349 1772 jl139090 350 1888 hyw #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 351 1772 jl139090 ver = ultra_getver(); 352 1772 jl139090 if (((ULTRA_VER_IMPL(ver)) == OLYMPUS_C_IMPL) && 353 5037 jl139090 ((OLYMPUS_REV_MASK(ver)) == OLYMPUS_C_A)) 354 1772 jl139090 bn_sets = 1; 355 1772 jl139090 #endif 356 1772 jl139090 357 1772 jl139090 #if (NCPU <= IDSR_BN_SETS) 358 1772 jl139090 for (i = 0; i < NCPU; i++) 359 1772 jl139090 if (CPU_IN_SET(set, i)) { 360 1772 jl139090 shipit(i, shipped); 361 1772 jl139090 nackmask |= IDSR_NACK_BIT(shipped); 362 1772 jl139090 cpuids[shipped++] = i; 363 1772 jl139090 CPUSET_DEL(set, i); 364 1772 jl139090 if (CPUSET_ISNULL(set)) 365 1772 jl139090 break; 366 1772 jl139090 } 367 1772 jl139090 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 368 1772 jl139090 #else 369 1772 jl139090 for (i = 0; i < NCPU; i++) 370 1772 jl139090 if (CPU_IN_SET(set, i)) { 371 1772 jl139090 ncpuids++; 372 1772 jl139090 373 1772 jl139090 /* 374 1772 jl139090 * Ship only to the first (IDSR_BN_SETS) CPUs. If we 375 1772 jl139090 * find we have shipped to more than (IDSR_BN_SETS) 376 1772 jl139090 * CPUs, set "index" to the highest numbered CPU in 377 1772 jl139090 * the set so we can ship to other CPUs a bit later on. 378 1772 jl139090 */ 379 1888 hyw #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 380 1772 jl139090 if (shipped < bn_sets) { 381 1772 jl139090 #else 382 1772 jl139090 if (shipped < IDSR_BN_SETS) { 383 1772 jl139090 #endif 384 1772 jl139090 shipit(i, shipped); 385 1772 jl139090 nackmask |= IDSR_NACK_BIT(shipped); 386 1772 jl139090 cpuids[shipped++] = i; 387 1772 jl139090 CPUSET_DEL(set, i); 388 1772 jl139090 if (CPUSET_ISNULL(set)) 389 1772 jl139090 break; 390 1772 jl139090 } else 391 1772 jl139090 index = (int)i; 392 1772 jl139090 } 393 1772 jl139090 394 1772 jl139090 CPU_STATS_ADDQ(CPU, sys, xcalls, ncpuids); 395 1772 jl139090 #endif 396 1772 jl139090 397 1772 jl139090 busymask = IDSR_NACK_TO_BUSY(nackmask); 398 1772 jl139090 busy = nack = 0; 399 1772 jl139090 endtick = starttick + xc_tick_limit; 400 1772 jl139090 for (;;) { 401 1772 jl139090 idsr = getidsr(); 402 1772 jl139090 #if (NCPU <= IDSR_BN_SETS) 403 1772 jl139090 if (idsr == 0) 404 1772 jl139090 break; 405 1772 jl139090 #else 406 1772 jl139090 if (idsr == 0 && shipped == ncpuids) 407 1772 jl139090 break; 408 1772 jl139090 #endif 409 1772 jl139090 tick = gettick(); 410 1772 jl139090 /* 411 1772 jl139090 * If there is a big jump between the current tick 412 1772 jl139090 * count and lasttick, we have probably hit a break 413 1772 jl139090 * point. Adjust endtick accordingly to avoid panic. 414 1772 jl139090 */ 415 1772 jl139090 if (tick > (lasttick + xc_tick_jump_limit)) 416 1772 jl139090 endtick += (tick - lasttick); 417 1772 jl139090 lasttick = tick; 418 1772 jl139090 if (tick > endtick) { 419 1772 jl139090 if (panic_quiesce) 420 1772 jl139090 return; 421 5037 jl139090 cmn_err(CE_CONT, "send mondo timeout [%d NACK %d " 422 5037 jl139090 "BUSY]\nIDSR 0x%" PRIx64 " cpuids:", 423 5037 jl139090 nack, busy, idsr); 424 1888 hyw #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 425 1772 jl139090 for (i = 0; i < bn_sets; i++) { 426 1772 jl139090 #else 427 1772 jl139090 for (i = 0; i < IDSR_BN_SETS; i++) { 428 1772 jl139090 #endif 429 1772 jl139090 if (idsr & (IDSR_NACK_BIT(i) | 430 1772 jl139090 IDSR_BUSY_BIT(i))) { 431 5037 jl139090 cmn_err(CE_CONT, " 0x%x", cpuids[i]); 432 1772 jl139090 } 433 1772 jl139090 } 434 1772 jl139090 cmn_err(CE_CONT, "\n"); 435 1772 jl139090 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 436 1772 jl139090 } 437 1772 jl139090 curnack = idsr & nackmask; 438 1772 jl139090 curbusy = idsr & busymask; 439 1888 hyw 440 1888 hyw #ifdef OLYMPUS_C_REV_B_ERRATA_XCALL 441 1888 hyw /* 442 1888 hyw * Only proceed to send more xcalls if all the 443 1888 hyw * cpus in the previous IDSR_BN_SETS were completed. 444 1888 hyw */ 445 1888 hyw if (curbusy) { 446 1888 hyw busy++; 447 1888 hyw continue; 448 1888 hyw } 449 1888 hyw #endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */ 450 1888 hyw 451 1772 jl139090 #if (NCPU > IDSR_BN_SETS) 452 1772 jl139090 if (shipped < ncpuids) { 453 1772 jl139090 uint64_t cpus_left; 454 1772 jl139090 uint16_t next = (uint16_t)index; 455 1772 jl139090 456 1772 jl139090 cpus_left = ~(IDSR_NACK_TO_BUSY(curnack) | curbusy) & 457 1772 jl139090 busymask; 458 1772 jl139090 459 1772 jl139090 if (cpus_left) { 460 1772 jl139090 do { 461 1772 jl139090 /* 462 1772 jl139090 * Sequence through and ship to the 463 1772 jl139090 * remainder of the CPUs in the system 464 1772 jl139090 * (e.g. other than the first 465 1772 jl139090 * (IDSR_BN_SETS)) in reverse order. 466 1772 jl139090 */ 467 1772 jl139090 lo = lowbit(cpus_left) - 1; 468 1772 jl139090 i = IDSR_BUSY_IDX(lo); 469 1772 jl139090 shipit(next, i); 470 1772 jl139090 shipped++; 471 1772 jl139090 cpuids[i] = next; 472 1772 jl139090 473 1772 jl139090 /* 474 1772 jl139090 * If we've processed all the CPUs, 475 1772 jl139090 * exit the loop now and save 476 1772 jl139090 * instructions. 477 1772 jl139090 */ 478 1772 jl139090 if (shipped == ncpuids) 479 1772 jl139090 break; 480 1772 jl139090 481 1772 jl139090 for ((index = ((int)next - 1)); 482 5037 jl139090 index >= 0; index--) 483 1772 jl139090 if (CPU_IN_SET(set, index)) { 484 1772 jl139090 next = (uint16_t)index; 485 1772 jl139090 break; 486 1772 jl139090 } 487 1772 jl139090 488 1772 jl139090 cpus_left &= ~(1ull << lo); 489 1772 jl139090 } while (cpus_left); 490 1772 jl139090 continue; 491 1772 jl139090 } 492 1772 jl139090 } 493 1772 jl139090 #endif 494 1888 hyw #ifndef OLYMPUS_C_REV_B_ERRATA_XCALL 495 1772 jl139090 if (curbusy) { 496 1772 jl139090 busy++; 497 1772 jl139090 continue; 498 1772 jl139090 } 499 1888 hyw #endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */ 500 1772 jl139090 #ifdef SEND_MONDO_STATS 501 1772 jl139090 { 502 1772 jl139090 int n = gettick() - starttick; 503 1772 jl139090 if (n < 8192) 504 1772 jl139090 x_nack_stimes[n >> 7]++; 505 1772 jl139090 } 506 1772 jl139090 #endif 507 1772 jl139090 while (gettick() < (tick + sys_clock_mhz)) 508 1772 jl139090 ; 509 1772 jl139090 do { 510 1772 jl139090 lo = lowbit(curnack) - 1; 511 1772 jl139090 i = IDSR_NACK_IDX(lo); 512 1772 jl139090 shipit(cpuids[i], i); 513 1772 jl139090 curnack &= ~(1ull << lo); 514 1772 jl139090 } while (curnack); 515 1772 jl139090 nack++; 516 1772 jl139090 busy = 0; 517 1772 jl139090 } 518 1772 jl139090 #ifdef SEND_MONDO_STATS 519 1772 jl139090 { 520 1772 jl139090 int n = gettick() - starttick; 521 1772 jl139090 if (n < 8192) 522 1772 jl139090 x_set_stimes[n >> 7]++; 523 1772 jl139090 else 524 1772 jl139090 x_set_ltimes[(n >> 13) & 0xf]++; 525 1772 jl139090 } 526 1772 jl139090 x_set_cpus[shipped]++; 527 1772 jl139090 #endif 528 1772 jl139090 } 529 1772 jl139090 530 1772 jl139090 /* 531 1772 jl139090 * Cpu private initialization. 532 1772 jl139090 */ 533 1772 jl139090 void 534 1772 jl139090 cpu_init_private(struct cpu *cp) 535 1772 jl139090 { 536 5037 jl139090 if (!((IS_OLYMPUS_C(cpunodes[cp->cpu_id].implementation)) || 537 5037 jl139090 (IS_JUPITER(cpunodes[cp->cpu_id].implementation)))) { 538 5037 jl139090 cmn_err(CE_PANIC, "CPU%d Impl %d: Only SPARC64-VI(I) is " 539 5037 jl139090 "supported", cp->cpu_id, 540 5037 jl139090 cpunodes[cp->cpu_id].implementation); 541 1772 jl139090 } 542 1772 jl139090 543 1772 jl139090 adjust_hw_copy_limits(cpunodes[cp->cpu_id].ecache_size); 544 1772 jl139090 } 545 1772 jl139090 546 1772 jl139090 void 547 1772 jl139090 cpu_setup(void) 548 1772 jl139090 { 549 1772 jl139090 extern int at_flags; 550 1772 jl139090 extern int cpc_has_overflow_intr; 551 1772 jl139090 uint64_t cpu0_log; 552 1772 jl139090 extern uint64_t opl_cpu0_err_log; 553 1772 jl139090 554 1772 jl139090 /* 555 1772 jl139090 * Initialize Error log Scratch register for error handling. 556 1772 jl139090 */ 557 1772 jl139090 558 1772 jl139090 cpu0_log = va_to_pa(&opl_cpu0_err_log); 559 1772 jl139090 opl_error_setup(cpu0_log); 560 6259 mb158278 opl_cpu0_log_setup = 1; 561 1772 jl139090 562 1772 jl139090 /* 563 1772 jl139090 * Enable MMU translating multiple page sizes for 564 1772 jl139090 * sITLB and sDTLB. 565 1772 jl139090 */ 566 8664 James cpu_early_feature_init(); 567 1772 jl139090 568 1772 jl139090 /* 569 1772 jl139090 * Setup chip-specific trap handlers. 570 1772 jl139090 */ 571 1772 jl139090 cpu_init_trap(); 572 1772 jl139090 573 1772 jl139090 cache |= (CACHE_VAC | CACHE_PTAG | CACHE_IOCOHERENT); 574 1772 jl139090 575 1772 jl139090 at_flags = EF_SPARC_32PLUS | EF_SPARC_SUN_US1 | EF_SPARC_SUN_US3; 576 1772 jl139090 577 1772 jl139090 /* 578 1772 jl139090 * Due to the number of entries in the fully-associative tlb 579 1772 jl139090 * this may have to be tuned lower than in spitfire. 580 1772 jl139090 */ 581 1772 jl139090 pp_slots = MIN(8, MAXPP_SLOTS); 582 1772 jl139090 583 1772 jl139090 /* 584 1772 jl139090 * Block stores do not invalidate all pages of the d$, pagecopy 585 1772 jl139090 * et. al. need virtual translations with virtual coloring taken 586 1772 jl139090 * into consideration. prefetch/ldd will pollute the d$ on the 587 1772 jl139090 * load side. 588 1772 jl139090 */ 589 1772 jl139090 pp_consistent_coloring = PPAGE_STORE_VCOLORING | PPAGE_LOADS_POLLUTE; 590 1772 jl139090 591 1772 jl139090 if (use_page_coloring) { 592 1772 jl139090 do_pg_coloring = 1; 593 1772 jl139090 } 594 1772 jl139090 595 1772 jl139090 isa_list = 596 1772 jl139090 "sparcv9+vis2 sparcv9+vis sparcv9 " 597 1772 jl139090 "sparcv8plus+vis2 sparcv8plus+vis sparcv8plus " 598 1772 jl139090 "sparcv8 sparcv8-fsmuld sparcv7 sparc"; 599 1772 jl139090 600 2801 hyw cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2 | 601 2801 hyw AV_SPARC_POPC | AV_SPARC_FMAF; 602 1772 jl139090 603 1772 jl139090 /* 604 1772 jl139090 * On SPARC64-VI, there's no hole in the virtual address space 605 1772 jl139090 */ 606 1772 jl139090 hole_start = hole_end = 0; 607 1772 jl139090 608 1772 jl139090 /* 609 1772 jl139090 * The kpm mapping window. 610 1772 jl139090 * kpm_size: 611 1772 jl139090 * The size of a single kpm range. 612 1772 jl139090 * The overall size will be: kpm_size * vac_colors. 613 1772 jl139090 * kpm_vbase: 614 1772 jl139090 * The virtual start address of the kpm range within the kernel 615 1772 jl139090 * virtual address space. kpm_vbase has to be kpm_size aligned. 616 1772 jl139090 */ 617 1772 jl139090 kpm_size = (size_t)(128ull * 1024 * 1024 * 1024 * 1024); /* 128TB */ 618 1772 jl139090 kpm_size_shift = 47; 619 1772 jl139090 kpm_vbase = (caddr_t)0x8000000000000000ull; /* 8EB */ 620 1772 jl139090 kpm_smallpages = 1; 621 1772 jl139090 622 1772 jl139090 /* 623 1772 jl139090 * The traptrace code uses either %tick or %stick for 624 1772 jl139090 * timestamping. We have %stick so we can use it. 625 1772 jl139090 */ 626 1772 jl139090 traptrace_use_stick = 1; 627 1772 jl139090 628 1772 jl139090 /* 629 1772 jl139090 * SPARC64-VI has a performance counter overflow interrupt 630 1772 jl139090 */ 631 1772 jl139090 cpc_has_overflow_intr = 1; 632 1772 jl139090 633 1772 jl139090 /* 634 1772 jl139090 * Declare that this architecture/cpu combination does not support 635 1772 jl139090 * fpRAS. 636 1772 jl139090 */ 637 1772 jl139090 fpras_implemented = 0; 638 1772 jl139090 } 639 1772 jl139090 640 1772 jl139090 /* 641 1772 jl139090 * Called by setcpudelay 642 1772 jl139090 */ 643 1772 jl139090 void 644 1772 jl139090 cpu_init_tick_freq(void) 645 1772 jl139090 { 646 1772 jl139090 /* 647 1772 jl139090 * For SPARC64-VI we want to use the system clock rate as 648 1772 jl139090 * the basis for low level timing, due to support of mixed 649 1772 jl139090 * speed CPUs and power managment. 650 1772 jl139090 */ 651 1772 jl139090 if (system_clock_freq == 0) 652 1772 jl139090 cmn_err(CE_PANIC, "setcpudelay: invalid system_clock_freq"); 653 1772 jl139090 654 1772 jl139090 sys_tick_freq = system_clock_freq; 655 1772 jl139090 } 656 1772 jl139090 657 1772 jl139090 #ifdef SEND_MONDO_STATS 658 1772 jl139090 uint32_t x_one_stimes[64]; 659 1772 jl139090 uint32_t x_one_ltimes[16]; 660 1772 jl139090 uint32_t x_set_stimes[64]; 661 1772 jl139090 uint32_t x_set_ltimes[16]; 662 1772 jl139090 uint32_t x_set_cpus[NCPU]; 663 1772 jl139090 uint32_t x_nack_stimes[64]; 664 1772 jl139090 #endif 665 1772 jl139090 666 1772 jl139090 /* 667 1772 jl139090 * Note: A version of this function is used by the debugger via the KDI, 668 1772 jl139090 * and must be kept in sync with this version. Any changes made to this 669 1772 jl139090 * function to support new chips or to accomodate errata must also be included 670 1772 jl139090 * in the KDI-specific version. See us3_kdi.c. 671 1772 jl139090 */ 672 1772 jl139090 void 673 1772 jl139090 send_one_mondo(int cpuid) 674 1772 jl139090 { 675 1772 jl139090 int busy, nack; 676 1772 jl139090 uint64_t idsr, starttick, endtick, tick, lasttick; 677 1772 jl139090 uint64_t busymask; 678 1772 jl139090 679 1772 jl139090 CPU_STATS_ADDQ(CPU, sys, xcalls, 1); 680 1772 jl139090 starttick = lasttick = gettick(); 681 1772 jl139090 shipit(cpuid, 0); 682 1772 jl139090 endtick = starttick + xc_tick_limit; 683 1772 jl139090 busy = nack = 0; 684 1772 jl139090 busymask = IDSR_BUSY; 685 1772 jl139090 for (;;) { 686 1772 jl139090 idsr = getidsr(); 687 1772 jl139090 if (idsr == 0) 688 1772 jl139090 break; 689 1772 jl139090 690 1772 jl139090 tick = gettick(); 691 1772 jl139090 /* 692 1772 jl139090 * If there is a big jump between the current tick 693 1772 jl139090 * count and lasttick, we have probably hit a break 694 1772 jl139090 * point. Adjust endtick accordingly to avoid panic. 695 1772 jl139090 */ 696 1772 jl139090 if (tick > (lasttick + xc_tick_jump_limit)) 697 1772 jl139090 endtick += (tick - lasttick); 698 1772 jl139090 lasttick = tick; 699 1772 jl139090 if (tick > endtick) { 700 1772 jl139090 if (panic_quiesce) 701 1772 jl139090 return; 702 5037 jl139090 cmn_err(CE_PANIC, "send mondo timeout (target 0x%x) " 703 5037 jl139090 "[%d NACK %d BUSY]", cpuid, nack, busy); 704 1772 jl139090 } 705 1772 jl139090 706 1772 jl139090 if (idsr & busymask) { 707 1772 jl139090 busy++; 708 1772 jl139090 continue; 709 1772 jl139090 } 710 1772 jl139090 drv_usecwait(1); 711 1772 jl139090 shipit(cpuid, 0); 712 1772 jl139090 nack++; 713 1772 jl139090 busy = 0; 714 1772 jl139090 } 715 1772 jl139090 #ifdef SEND_MONDO_STATS 716 1772 jl139090 { 717 1772 jl139090 int n = gettick() - starttick; 718 1772 jl139090 if (n < 8192) 719 1772 jl139090 x_one_stimes[n >> 7]++; 720 1772 jl139090 else 721 1772 jl139090 x_one_ltimes[(n >> 13) & 0xf]++; 722 1772 jl139090 } 723 1772 jl139090 #endif 724 1772 jl139090 } 725 1772 jl139090 726 1772 jl139090 /* 727 1772 jl139090 * init_mmu_page_sizes is set to one after the bootup time initialization 728 1772 jl139090 * via mmu_init_mmu_page_sizes, to indicate that mmu_page_sizes has a 729 1772 jl139090 * valid value. 730 1772 jl139090 * 731 1772 jl139090 * mmu_disable_ism_large_pages and mmu_disable_large_pages are the mmu-specific 732 1772 jl139090 * versions of disable_ism_large_pages and disable_large_pages, and feed back 733 1772 jl139090 * into those two hat variables at hat initialization time. 734 1772 jl139090 * 735 1772 jl139090 */ 736 1772 jl139090 int init_mmu_page_sizes = 0; 737 2991 susans 738 2991 susans static uint_t mmu_disable_large_pages = 0; 739 2991 susans static uint_t mmu_disable_ism_large_pages = ((1 << TTE64K) | 740 2659 susans (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 741 2991 susans static uint_t mmu_disable_auto_data_large_pages = ((1 << TTE64K) | 742 2659 susans (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 743 2991 susans static uint_t mmu_disable_auto_text_large_pages = ((1 << TTE64K) | 744 2991 susans (1 << TTE512K)); 745 1772 jl139090 746 1772 jl139090 /* 747 1772 jl139090 * Re-initialize mmu_page_sizes and friends, for SPARC64-VI mmu support. 748 1772 jl139090 * Called during very early bootup from check_cpus_set(). 749 1772 jl139090 * Can be called to verify that mmu_page_sizes are set up correctly. 750 1772 jl139090 * 751 1772 jl139090 * Set Olympus defaults. We do not use the function parameter. 752 1772 jl139090 */ 753 1772 jl139090 /*ARGSUSED*/ 754 7869 Sean void 755 7869 Sean mmu_init_scd(sf_scd_t *scdp) 756 7869 Sean { 757 7869 Sean scdp->scd_sfmmup->sfmmu_cext = shctx_cext; 758 7869 Sean } 759 7869 Sean 760 7869 Sean /*ARGSUSED*/ 761 1772 jl139090 int 762 1772 jl139090 mmu_init_mmu_page_sizes(int32_t not_used) 763 1772 jl139090 { 764 1772 jl139090 if (!init_mmu_page_sizes) { 765 1772 jl139090 mmu_page_sizes = MMU_PAGE_SIZES; 766 1772 jl139090 mmu_hashcnt = MAX_HASHCNT; 767 2659 susans mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE; 768 1772 jl139090 mmu_exported_pagesize_mask = (1 << TTE8K) | 769 1772 jl139090 (1 << TTE64K) | (1 << TTE512K) | (1 << TTE4M) | 770 1772 jl139090 (1 << TTE32M) | (1 << TTE256M); 771 1772 jl139090 init_mmu_page_sizes = 1; 772 1772 jl139090 return (0); 773 1772 jl139090 } 774 1772 jl139090 return (1); 775 1772 jl139090 } 776 1772 jl139090 777 1772 jl139090 /* SPARC64-VI worst case DTLB parameters */ 778 1772 jl139090 #ifndef LOCKED_DTLB_ENTRIES 779 1772 jl139090 #define LOCKED_DTLB_ENTRIES 5 /* 2 user TSBs, 2 nucleus, + OBP */ 780 1772 jl139090 #endif 781 1772 jl139090 #define TOTAL_DTLB_ENTRIES 32 782 1772 jl139090 #define AVAIL_32M_ENTRIES 0 783 1772 jl139090 #define AVAIL_256M_ENTRIES 0 784 1772 jl139090 #define AVAIL_DTLB_ENTRIES (TOTAL_DTLB_ENTRIES - LOCKED_DTLB_ENTRIES) 785 1772 jl139090 static uint64_t ttecnt_threshold[MMU_PAGE_SIZES] = { 786 1772 jl139090 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES, 787 1772 jl139090 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES, 788 1772 jl139090 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES}; 789 1772 jl139090 790 1772 jl139090 /* 791 1772 jl139090 * The function returns the mmu-specific values for the 792 2368 jimand * hat's disable_large_pages, disable_ism_large_pages, and 793 2991 susans * disable_auto_data_large_pages and 794 2991 susans * disable_text_data_large_pages variables. 795 1772 jl139090 */ 796 2991 susans uint_t 797 1772 jl139090 mmu_large_pages_disabled(uint_t flag) 798 1772 jl139090 { 799 2991 susans uint_t pages_disable = 0; 800 2991 susans extern int use_text_pgsz64K; 801 2991 susans extern int use_text_pgsz512K; 802 1772 jl139090 803 1772 jl139090 if (flag == HAT_LOAD) { 804 1772 jl139090 pages_disable = mmu_disable_large_pages; 805 1772 jl139090 } else if (flag == HAT_LOAD_SHARE) { 806 1772 jl139090 pages_disable = mmu_disable_ism_large_pages; 807 2991 susans } else if (flag == HAT_AUTO_DATA) { 808 2991 susans pages_disable = mmu_disable_auto_data_large_pages; 809 2991 susans } else if (flag == HAT_AUTO_TEXT) { 810 2991 susans pages_disable = mmu_disable_auto_text_large_pages; 811 2991 susans if (use_text_pgsz512K) { 812 2991 susans pages_disable &= ~(1 << TTE512K); 813 2991 susans } 814 2991 susans if (use_text_pgsz64K) { 815 2991 susans pages_disable &= ~(1 << TTE64K); 816 2991 susans } 817 1772 jl139090 } 818 1772 jl139090 return (pages_disable); 819 1772 jl139090 } 820 1772 jl139090 821 1772 jl139090 /* 822 1772 jl139090 * mmu_init_large_pages is called with the desired ism_pagesize parameter. 823 6127 sm142603 * It may be called from set_platform_defaults, if some value other than 4M 824 1772 jl139090 * is desired. mmu_ism_pagesize is the tunable. If it has a bad value, 825 1772 jl139090 * then only warn, since it would be bad form to panic due to a user typo. 826 1772 jl139090 * 827 1772 jl139090 * The function re-initializes the mmu_disable_ism_large_pages variable. 828 1772 jl139090 */ 829 1772 jl139090 void 830 1772 jl139090 mmu_init_large_pages(size_t ism_pagesize) 831 1772 jl139090 { 832 6127 sm142603 833 1772 jl139090 switch (ism_pagesize) { 834 1772 jl139090 case MMU_PAGESIZE4M: 835 1772 jl139090 mmu_disable_ism_large_pages = ((1 << TTE64K) | 836 1772 jl139090 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 837 2991 susans mmu_disable_auto_data_large_pages = ((1 << TTE64K) | 838 2368 jimand (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 839 6127 sm142603 shctx_cext = TAGACCEXT_MKSZPAIR(TTE4M, TTE8K); 840 1772 jl139090 break; 841 1772 jl139090 case MMU_PAGESIZE32M: 842 1772 jl139090 mmu_disable_ism_large_pages = ((1 << TTE64K) | 843 1772 jl139090 (1 << TTE512K) | (1 << TTE256M)); 844 2991 susans mmu_disable_auto_data_large_pages = ((1 << TTE64K) | 845 2368 jimand (1 << TTE512K) | (1 << TTE4M) | (1 << TTE256M)); 846 2991 susans adjust_data_maxlpsize(ism_pagesize); 847 6127 sm142603 shctx_cext = TAGACCEXT_MKSZPAIR(TTE32M, TTE8K); 848 1772 jl139090 break; 849 1772 jl139090 case MMU_PAGESIZE256M: 850 1772 jl139090 mmu_disable_ism_large_pages = ((1 << TTE64K) | 851 1772 jl139090 (1 << TTE512K) | (1 << TTE32M)); 852 2991 susans mmu_disable_auto_data_large_pages = ((1 << TTE64K) | 853 2368 jimand (1 << TTE512K) | (1 << TTE4M) | (1 << TTE32M)); 854 2991 susans adjust_data_maxlpsize(ism_pagesize); 855 6127 sm142603 shctx_cext = TAGACCEXT_MKSZPAIR(TTE256M, TTE8K); 856 1772 jl139090 break; 857 1772 jl139090 default: 858 1772 jl139090 cmn_err(CE_WARN, "Unrecognized mmu_ism_pagesize value 0x%lx", 859 1772 jl139090 ism_pagesize); 860 1772 jl139090 break; 861 1772 jl139090 } 862 1772 jl139090 } 863 1772 jl139090 864 1772 jl139090 /* 865 1772 jl139090 * Function to reprogram the TLBs when page sizes used 866 1772 jl139090 * by a process change significantly. 867 1772 jl139090 */ 868 6127 sm142603 static void 869 2272 jimand mmu_setup_page_sizes(struct hat *hat, uint64_t *ttecnt, uint8_t *tmp_pgsz) 870 1772 jl139090 { 871 1772 jl139090 uint8_t pgsz0, pgsz1; 872 1772 jl139090 873 1772 jl139090 /* 874 1772 jl139090 * Don't program 2nd dtlb for kernel and ism hat 875 1772 jl139090 */ 876 2272 jimand ASSERT(hat->sfmmu_ismhat == NULL); 877 2272 jimand ASSERT(hat != ksfmmup); 878 1772 jl139090 879 1772 jl139090 /* 880 1772 jl139090 * hat->sfmmu_pgsz[] is an array whose elements 881 1772 jl139090 * contain a sorted order of page sizes. Element 882 1772 jl139090 * 0 is the most commonly used page size, followed 883 1772 jl139090 * by element 1, and so on. 884 1772 jl139090 * 885 1772 jl139090 * ttecnt[] is an array of per-page-size page counts 886 1772 jl139090 * mapped into the process. 887 1772 jl139090 * 888 1772 jl139090 * If the HAT's choice for page sizes is unsuitable, 889 1772 jl139090 * we can override it here. The new values written 890 1772 jl139090 * to the array will be handed back to us later to 891 1772 jl139090 * do the actual programming of the TLB hardware. 892 1772 jl139090 * 893 1772 jl139090 */ 894 2272 jimand pgsz0 = (uint8_t)MIN(tmp_pgsz[0], tmp_pgsz[1]); 895 2272 jimand pgsz1 = (uint8_t)MAX(tmp_pgsz[0], tmp_pgsz[1]); 896 1772 jl139090 897 1772 jl139090 /* 898 1772 jl139090 * This implements PAGESIZE programming of the sTLB 899 1772 jl139090 * if large TTE counts don't exceed the thresholds. 900 1772 jl139090 */ 901 1772 jl139090 if (ttecnt[pgsz0] < ttecnt_threshold[pgsz0]) 902 1772 jl139090 pgsz0 = page_szc(MMU_PAGESIZE); 903 1772 jl139090 if (ttecnt[pgsz1] < ttecnt_threshold[pgsz1]) 904 1772 jl139090 pgsz1 = page_szc(MMU_PAGESIZE); 905 2272 jimand tmp_pgsz[0] = pgsz0; 906 2272 jimand tmp_pgsz[1] = pgsz1; 907 1772 jl139090 /* otherwise, accept what the HAT chose for us */ 908 1772 jl139090 } 909 1772 jl139090 910 1772 jl139090 /* 911 1772 jl139090 * The HAT calls this function when an MMU context is allocated so that we 912 1772 jl139090 * can reprogram the large TLBs appropriately for the new process using 913 1772 jl139090 * the context. 914 1772 jl139090 * 915 1772 jl139090 * The caller must hold the HAT lock. 916 1772 jl139090 */ 917 1772 jl139090 void 918 1772 jl139090 mmu_set_ctx_page_sizes(struct hat *hat) 919 1772 jl139090 { 920 1772 jl139090 uint8_t pgsz0, pgsz1; 921 1772 jl139090 uint8_t new_cext; 922 1772 jl139090 923 1772 jl139090 ASSERT(sfmmu_hat_lock_held(hat)); 924 1772 jl139090 /* 925 1772 jl139090 * Don't program 2nd dtlb for kernel and ism hat 926 1772 jl139090 */ 927 1772 jl139090 if (hat->sfmmu_ismhat || hat == ksfmmup) 928 1772 jl139090 return; 929 1772 jl139090 930 1772 jl139090 /* 931 1772 jl139090 * If supported, reprogram the TLBs to a larger pagesize. 932 1772 jl139090 */ 933 6127 sm142603 if (hat->sfmmu_scdp != NULL) { 934 7869 Sean new_cext = hat->sfmmu_scdp->scd_sfmmup->sfmmu_cext; 935 7869 Sean ASSERT(new_cext == shctx_cext); 936 6127 sm142603 } else { 937 6127 sm142603 pgsz0 = hat->sfmmu_pgsz[0]; 938 6127 sm142603 pgsz1 = hat->sfmmu_pgsz[1]; 939 6127 sm142603 ASSERT(pgsz0 < mmu_page_sizes); 940 6127 sm142603 ASSERT(pgsz1 < mmu_page_sizes); 941 6127 sm142603 new_cext = TAGACCEXT_MKSZPAIR(pgsz1, pgsz0); 942 6127 sm142603 } 943 1772 jl139090 if (hat->sfmmu_cext != new_cext) { 944 2241 huah #ifdef DEBUG 945 2241 huah int i; 946 2241 huah /* 947 2241 huah * assert cnum should be invalid, this is because pagesize 948 2241 huah * can only be changed after a proc's ctxs are invalidated. 949 2241 huah */ 950 2241 huah for (i = 0; i < max_mmu_ctxdoms; i++) { 951 2241 huah ASSERT(hat->sfmmu_ctxs[i].cnum == INVALID_CONTEXT); 952 2241 huah } 953 2241 huah #endif /* DEBUG */ 954 1772 jl139090 hat->sfmmu_cext = new_cext; 955 1772 jl139090 } 956 1772 jl139090 /* 957 1772 jl139090 * sfmmu_setctx_sec() will take care of the 958 1772 jl139090 * rest of the dirty work for us. 959 1772 jl139090 */ 960 2272 jimand } 961 2272 jimand 962 2272 jimand /* 963 2272 jimand * This function assumes that there are either four or six supported page 964 2272 jimand * sizes and at most two programmable TLBs, so we need to decide which 965 2272 jimand * page sizes are most important and then adjust the TLB page sizes 966 2272 jimand * accordingly (if supported). 967 2272 jimand * 968 2272 jimand * If these assumptions change, this function will need to be 969 2272 jimand * updated to support whatever the new limits are. 970 2272 jimand */ 971 2272 jimand void 972 2272 jimand mmu_check_page_sizes(sfmmu_t *sfmmup, uint64_t *ttecnt) 973 2272 jimand { 974 2272 jimand uint64_t sortcnt[MMU_PAGE_SIZES]; 975 2272 jimand uint8_t tmp_pgsz[MMU_PAGE_SIZES]; 976 2272 jimand uint8_t i, j, max; 977 2272 jimand uint16_t oldval, newval; 978 2272 jimand 979 2272 jimand /* 980 2272 jimand * We only consider reprogramming the TLBs if one or more of 981 2272 jimand * the two most used page sizes changes and we're using 982 2272 jimand * large pages in this process. 983 2272 jimand */ 984 4528 paulsan if (SFMMU_LGPGS_INUSE(sfmmup)) { 985 2272 jimand /* Sort page sizes. */ 986 2272 jimand for (i = 0; i < mmu_page_sizes; i++) { 987 2272 jimand sortcnt[i] = ttecnt[i]; 988 2272 jimand } 989 2272 jimand for (j = 0; j < mmu_page_sizes; j++) { 990 2272 jimand for (i = mmu_page_sizes - 1, max = 0; i > 0; i--) { 991 2272 jimand if (sortcnt[i] > sortcnt[max]) 992 2272 jimand max = i; 993 2272 jimand } 994 2272 jimand tmp_pgsz[j] = max; 995 2272 jimand sortcnt[max] = 0; 996 2272 jimand } 997 2272 jimand 998 2272 jimand oldval = sfmmup->sfmmu_pgsz[0] << 8 | sfmmup->sfmmu_pgsz[1]; 999 2272 jimand 1000 2272 jimand mmu_setup_page_sizes(sfmmup, ttecnt, tmp_pgsz); 1001 2272 jimand 1002 2272 jimand /* Check 2 largest values after the sort. */ 1003 2272 jimand newval = tmp_pgsz[0] << 8 | tmp_pgsz[1]; 1004 2272 jimand if (newval != oldval) { 1005 2272 jimand sfmmu_reprog_pgsz_arr(sfmmup, tmp_pgsz); 1006 2272 jimand } 1007 2272 jimand } 1008 1772 jl139090 } 1009 1772 jl139090 1010 1772 jl139090 /* 1011 1772 jl139090 * Return processor specific async error structure 1012 1772 jl139090 * size used. 1013 1772 jl139090 */ 1014 1772 jl139090 int 1015 1772 jl139090 cpu_aflt_size(void) 1016 1772 jl139090 { 1017 1772 jl139090 return (sizeof (opl_async_flt_t)); 1018 1772 jl139090 } 1019 1772 jl139090 1020 1772 jl139090 /* 1021 1772 jl139090 * The cpu_sync_log_err() function is called via the [uc]e_drain() function to 1022 1772 jl139090 * post-process CPU events that are dequeued. As such, it can be invoked 1023 1772 jl139090 * from softint context, from AST processing in the trap() flow, or from the 1024 1772 jl139090 * panic flow. We decode the CPU-specific data, and take appropriate actions. 1025 1772 jl139090 * Historically this entry point was used to log the actual cmn_err(9F) text; 1026 1772 jl139090 * now with FMA it is used to prepare 'flt' to be converted into an ereport. 1027 1772 jl139090 * With FMA this function now also returns a flag which indicates to the 1028 1772 jl139090 * caller whether the ereport should be posted (1) or suppressed (0). 1029 1772 jl139090 */ 1030 1772 jl139090 /*ARGSUSED*/ 1031 1772 jl139090 static int 1032 1772 jl139090 cpu_sync_log_err(void *flt) 1033 1772 jl139090 { 1034 1772 jl139090 opl_async_flt_t *opl_flt = (opl_async_flt_t *)flt; 1035 1772 jl139090 struct async_flt *aflt = (struct async_flt *)flt; 1036 1772 jl139090 1037 1772 jl139090 /* 1038 1772 jl139090 * No extra processing of urgent error events. 1039 1772 jl139090 * Always generate ereports for these events. 1040 1772 jl139090 */ 1041 1772 jl139090 if (aflt->flt_status == OPL_ECC_URGENT_TRAP) 1042 1772 jl139090 return (1); 1043 1772 jl139090 1044 1772 jl139090 /* 1045 1772 jl139090 * Additional processing for synchronous errors. 1046 1772 jl139090 */ 1047 1772 jl139090 switch (opl_flt->flt_type) { 1048 1772 jl139090 case OPL_CPU_INV_SFSR: 1049 1772 jl139090 return (1); 1050 1772 jl139090 1051 1772 jl139090 case OPL_CPU_SYNC_UE: 1052 1772 jl139090 /* 1053 1772 jl139090 * The validity: SFSR_MK_UE bit has been checked 1054 1772 jl139090 * in opl_cpu_sync_error() 1055 1772 jl139090 * No more check is required. 1056 1772 jl139090 * 1057 1772 jl139090 * opl_flt->flt_eid_mod and flt_eid_sid have been set by H/W, 1058 1772 jl139090 * and they have been retrieved in cpu_queue_events() 1059 1772 jl139090 */ 1060 1772 jl139090 1061 1772 jl139090 if (opl_flt->flt_eid_mod == OPL_ERRID_MEM) { 1062 1772 jl139090 ASSERT(aflt->flt_in_memory); 1063 1772 jl139090 /* 1064 1772 jl139090 * We want to skip logging only if ALL the following 1065 1772 jl139090 * conditions are true: 1066 1772 jl139090 * 1067 1772 jl139090 * 1. We are not panicing already. 1068 1772 jl139090 * 2. The error is a memory error. 1069 1772 jl139090 * 3. There is only one error. 1070 1772 jl139090 * 4. The error is on a retired page. 1071 1772 jl139090 * 5. The error occurred under on_trap 1072 1772 jl139090 * protection AFLT_PROT_EC 1073 1772 jl139090 */ 1074 1772 jl139090 if (!panicstr && aflt->flt_prot == AFLT_PROT_EC && 1075 1772 jl139090 page_retire_check(aflt->flt_addr, NULL) == 0) { 1076 1772 jl139090 /* 1077 1772 jl139090 * Do not log an error from 1078 1772 jl139090 * the retired page 1079 1772 jl139090 */ 1080 1772 jl139090 softcall(ecc_page_zero, (void *)aflt->flt_addr); 1081 1772 jl139090 return (0); 1082 1772 jl139090 } 1083 1772 jl139090 if (!panicstr) 1084 1772 jl139090 cpu_page_retire(opl_flt); 1085 1772 jl139090 } 1086 1772 jl139090 return (1); 1087 1772 jl139090 1088 1772 jl139090 case OPL_CPU_SYNC_OTHERS: 1089 1772 jl139090 /* 1090 1772 jl139090 * For the following error cases, the processor HW does 1091 1772 jl139090 * not set the flt_eid_mod/flt_eid_sid. Instead, SW will attempt 1092 1772 jl139090 * to assign appropriate values here to reflect what we 1093 1772 jl139090 * think is the most likely cause of the problem w.r.t to 1094 1772 jl139090 * the particular error event. For Buserr and timeout 1095 1772 jl139090 * error event, we will assign OPL_ERRID_CHANNEL as the 1096 1772 jl139090 * most likely reason. For TLB parity or multiple hit 1097 1772 jl139090 * error events, we will assign the reason as 1098 1772 jl139090 * OPL_ERRID_CPU (cpu related problem) and set the 1099 1772 jl139090 * flt_eid_sid to point to the cpuid. 1100 1772 jl139090 */ 1101 1772 jl139090 1102 1772 jl139090 if (opl_flt->flt_bit & (SFSR_BERR|SFSR_TO)) { 1103 1772 jl139090 /* 1104 1772 jl139090 * flt_eid_sid will not be used for this case. 1105 1772 jl139090 */ 1106 1772 jl139090 opl_flt->flt_eid_mod = OPL_ERRID_CHANNEL; 1107 1772 jl139090 } 1108 1772 jl139090 if (opl_flt->flt_bit & (SFSR_TLB_MUL|SFSR_TLB_PRT)) { 1109 5037 jl139090 opl_flt->flt_eid_mod = OPL_ERRID_CPU; 1110 5037 jl139090 opl_flt->flt_eid_sid = aflt->flt_inst; 1111 1772 jl139090 } 1112 1772 jl139090 1113 1772 jl139090 /* 1114 1772 jl139090 * In case of no effective error bit 1115 1772 jl139090 */ 1116 1772 jl139090 if ((opl_flt->flt_bit & SFSR_ERRS) == 0) { 1117 5037 jl139090 opl_flt->flt_eid_mod = OPL_ERRID_CPU; 1118 5037 jl139090 opl_flt->flt_eid_sid = aflt->flt_inst; 1119 1772 jl139090 } 1120 1772 jl139090 break; 1121 1772 jl139090 1122 1772 jl139090 default: 1123 1772 jl139090 return (1); 1124 1772 jl139090 } 1125 1772 jl139090 return (1); 1126 1772 jl139090 } 1127 1772 jl139090 1128 1772 jl139090 /* 1129 1772 jl139090 * Retire the bad page that may contain the flushed error. 1130 1772 jl139090 */ 1131 1772 jl139090 void 1132 1772 jl139090 cpu_page_retire(opl_async_flt_t *opl_flt) 1133 1772 jl139090 { 1134 1772 jl139090 struct async_flt *aflt = (struct async_flt *)opl_flt; 1135 1772 jl139090 (void) page_retire(aflt->flt_addr, PR_UE); 1136 1772 jl139090 } 1137 1772 jl139090 1138 1772 jl139090 /* 1139 1772 jl139090 * Invoked by error_init() early in startup and therefore before 1140 1772 jl139090 * startup_errorq() is called to drain any error Q - 1141 1772 jl139090 * 1142 1772 jl139090 * startup() 1143 1772 jl139090 * startup_end() 1144 1772 jl139090 * error_init() 1145 1772 jl139090 * cpu_error_init() 1146 1772 jl139090 * errorq_init() 1147 1772 jl139090 * errorq_drain() 1148 1772 jl139090 * start_other_cpus() 1149 1772 jl139090 * 1150 1772 jl139090 * The purpose of this routine is to create error-related taskqs. Taskqs 1151 1772 jl139090 * are used for this purpose because cpu_lock can't be grabbed from interrupt 1152 1772 jl139090 * context. 1153 1772 jl139090 * 1154 1772 jl139090 */ 1155 1772 jl139090 /*ARGSUSED*/ 1156 1772 jl139090 void 1157 1772 jl139090 cpu_error_init(int items) 1158 1772 jl139090 { 1159 1772 jl139090 opl_err_log = (opl_errlog_t *) 1160 1772 jl139090 kmem_alloc(ERRLOG_ALLOC_SZ, KM_SLEEP); 1161 1772 jl139090 if ((uint64_t)opl_err_log & MMU_PAGEOFFSET) 1162 1772 jl139090 cmn_err(CE_PANIC, "The base address of the error log " 1163 1772 jl139090 "is not page aligned"); 1164 1772 jl139090 } 1165 1772 jl139090 1166 1772 jl139090 /* 1167 1772 jl139090 * We route all errors through a single switch statement. 1168 1772 jl139090 */ 1169 1772 jl139090 void 1170 1772 jl139090 cpu_ue_log_err(struct async_flt *aflt) 1171 1772 jl139090 { 1172 1772 jl139090 switch (aflt->flt_class) { 1173 1772 jl139090 case CPU_FAULT: 1174 1772 jl139090 if (cpu_sync_log_err(aflt)) 1175 1772 jl139090 cpu_ereport_post(aflt); 1176 1772 jl139090 break; 1177 1772 jl139090 1178 1772 jl139090 case BUS_FAULT: 1179 1772 jl139090 bus_async_log_err(aflt); 1180 1772 jl139090 break; 1181 1772 jl139090 1182 1772 jl139090 default: 1183 1772 jl139090 cmn_err(CE_WARN, "discarding async error %p with invalid " 1184 1772 jl139090 "fault class (0x%x)", (void *)aflt, aflt->flt_class); 1185 1772 jl139090 return; 1186 1772 jl139090 } 1187 1772 jl139090 } 1188 1772 jl139090 1189 1772 jl139090 /* 1190 1772 jl139090 * Routine for panic hook callback from panic_idle(). 1191 1772 jl139090 * 1192 1772 jl139090 * Nothing to do here. 1193 1772 jl139090 */ 1194 1772 jl139090 void 1195 1772 jl139090 cpu_async_panic_callb(void) 1196 1772 jl139090 { 1197 1772 jl139090 } 1198 1772 jl139090 1199 1772 jl139090 /* 1200 1772 jl139090 * Routine to return a string identifying the physical name 1201 1772 jl139090 * associated with a memory/cache error. 1202 1772 jl139090 */ 1203 1772 jl139090 /*ARGSUSED*/ 1204 1772 jl139090 int 1205 1772 jl139090 cpu_get_mem_unum(int synd_status, ushort_t flt_synd, uint64_t flt_stat, 1206 1772 jl139090 uint64_t flt_addr, int flt_bus_id, int flt_in_memory, 1207 1772 jl139090 ushort_t flt_status, char *buf, int buflen, int *lenp) 1208 1772 jl139090 { 1209 1772 jl139090 int synd_code; 1210 1772 jl139090 int ret; 1211 1772 jl139090 1212 1772 jl139090 /* 1213 1772 jl139090 * An AFSR of -1 defaults to a memory syndrome. 1214 1772 jl139090 */ 1215 1772 jl139090 synd_code = (int)flt_synd; 1216 1772 jl139090 1217 1772 jl139090 if (&plat_get_mem_unum) { 1218 1772 jl139090 if ((ret = plat_get_mem_unum(synd_code, flt_addr, flt_bus_id, 1219 5037 jl139090 flt_in_memory, flt_status, buf, buflen, lenp)) != 0) { 1220 1772 jl139090 buf[0] = '\0'; 1221 1772 jl139090 *lenp = 0; 1222 1772 jl139090 } 1223 1772 jl139090 return (ret); 1224 1772 jl139090 } 1225 1772 jl139090 buf[0] = '\0'; 1226 1772 jl139090 *lenp = 0; 1227 1772 jl139090 return (ENOTSUP); 1228 1772 jl139090 } 1229 1772 jl139090 1230 1772 jl139090 /* 1231 1772 jl139090 * Wrapper for cpu_get_mem_unum() routine that takes an 1232 1772 jl139090 * async_flt struct rather than explicit arguments. 1233 1772 jl139090 */ 1234 1772 jl139090 int 1235 1772 jl139090 cpu_get_mem_unum_aflt(int synd_status, struct async_flt *aflt, 1236 1772 jl139090 char *buf, int buflen, int *lenp) 1237 1772 jl139090 { 1238 1772 jl139090 /* 1239 1772 jl139090 * We always pass -1 so that cpu_get_mem_unum will interpret this as a 1240 1772 jl139090 * memory error. 1241 1772 jl139090 */ 1242 1772 jl139090 return (cpu_get_mem_unum(synd_status, aflt->flt_synd, 1243 1772 jl139090 (uint64_t)-1, 1244 1772 jl139090 aflt->flt_addr, aflt->flt_bus_id, aflt->flt_in_memory, 1245 1772 jl139090 aflt->flt_status, buf, buflen, lenp)); 1246 1772 jl139090 } 1247 1772 jl139090 1248 1772 jl139090 /* 1249 1772 jl139090 * This routine is a more generic interface to cpu_get_mem_unum() 1250 1772 jl139090 * that may be used by other modules (e.g. mm). 1251 1772 jl139090 */ 1252 1772 jl139090 /*ARGSUSED*/ 1253 1772 jl139090 int 1254 1772 jl139090 cpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar, 1255 1772 jl139090 char *buf, int buflen, int *lenp) 1256 1772 jl139090 { 1257 1772 jl139090 int synd_status, flt_in_memory, ret; 1258 1772 jl139090 ushort_t flt_status = 0; 1259 1772 jl139090 char unum[UNUM_NAMLEN]; 1260 1772 jl139090 1261 1772 jl139090 /* 1262 1772 jl139090 * Check for an invalid address. 1263 1772 jl139090 */ 1264 1772 jl139090 if (afar == (uint64_t)-1) 1265 1772 jl139090 return (ENXIO); 1266 1772 jl139090 1267 1772 jl139090 if (synd == (uint64_t)-1) 1268 1772 jl139090 synd_status = AFLT_STAT_INVALID; 1269 1772 jl139090 else 1270 1772 jl139090 synd_status = AFLT_STAT_VALID; 1271 1772 jl139090 1272 1772 jl139090 flt_in_memory = (*afsr & SFSR_MEMORY) && 1273 5037 jl139090 pf_is_memory(afar >> MMU_PAGESHIFT); 1274 1772 jl139090 1275 1772 jl139090 ret = cpu_get_mem_unum(synd_status, (ushort_t)synd, *afsr, afar, 1276 5037 jl139090 CPU->cpu_id, flt_in_memory, flt_status, unum, UNUM_NAMLEN, lenp); 1277 1772 jl139090 if (ret != 0) 1278 1772 jl139090 return (ret); 1279 1772 jl139090 1280 1772 jl139090 if (*lenp >= buflen) 1281 1772 jl139090 return (ENAMETOOLONG); 1282 1772 jl139090 1283 1772 jl139090 (void) strncpy(buf, unum, buflen); 1284 1772 jl139090 1285 1772 jl139090 return (0); 1286 1772 jl139090 } 1287 1772 jl139090 1288 1772 jl139090 /* 1289 1772 jl139090 * Routine to return memory information associated 1290 1772 jl139090 * with a physical address and syndrome. 1291 1772 jl139090 */ 1292 1772 jl139090 /*ARGSUSED*/ 1293 1772 jl139090 int 1294 1772 jl139090 cpu_get_mem_info(uint64_t synd, uint64_t afar, 1295 1772 jl139090 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 1296 1772 jl139090 int *segsp, int *banksp, int *mcidp) 1297 1772 jl139090 { 1298 1772 jl139090 int synd_code = (int)synd; 1299 1772 jl139090 1300 1772 jl139090 if (afar == (uint64_t)-1) 1301 1772 jl139090 return (ENXIO); 1302 1772 jl139090 1303 1772 jl139090 if (p2get_mem_info != NULL) 1304 5037 jl139090 return ((p2get_mem_info)(synd_code, afar, mem_sizep, seg_sizep, 1305 5037 jl139090 bank_sizep, segsp, banksp, mcidp)); 1306 1772 jl139090 else 1307 1772 jl139090 return (ENOTSUP); 1308 1772 jl139090 } 1309 1772 jl139090 1310 1772 jl139090 /* 1311 1772 jl139090 * Routine to return a string identifying the physical 1312 1772 jl139090 * name associated with a cpuid. 1313 1772 jl139090 */ 1314 1772 jl139090 int 1315 1772 jl139090 cpu_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 1316 1772 jl139090 { 1317 1772 jl139090 int ret; 1318 1772 jl139090 char unum[UNUM_NAMLEN]; 1319 1772 jl139090 1320 1772 jl139090 if (&plat_get_cpu_unum) { 1321 5037 jl139090 if ((ret = plat_get_cpu_unum(cpuid, unum, UNUM_NAMLEN, 1322 5037 jl139090 lenp)) != 0) 1323 1772 jl139090 return (ret); 1324 1772 jl139090 } else { 1325 1772 jl139090 return (ENOTSUP); 1326 1772 jl139090 } 1327 1772 jl139090 1328 1772 jl139090 if (*lenp >= buflen) 1329 1772 jl139090 return (ENAMETOOLONG); 1330 1772 jl139090 1331 1772 jl139090 (void) strncpy(buf, unum, *lenp); 1332 1772 jl139090 1333 1772 jl139090 return (0); 1334 1772 jl139090 } 1335 1772 jl139090 1336 1772 jl139090 /* 1337 1772 jl139090 * This routine exports the name buffer size. 1338 1772 jl139090 */ 1339 1772 jl139090 size_t 1340 1772 jl139090 cpu_get_name_bufsize() 1341 1772 jl139090 { 1342 1772 jl139090 return (UNUM_NAMLEN); 1343 1772 jl139090 } 1344 1772 jl139090 1345 1772 jl139090 /* 1346 1772 jl139090 * Flush the entire ecache by ASI_L2_CNTL.U2_FLUSH 1347 1772 jl139090 */ 1348 1772 jl139090 void 1349 1772 jl139090 cpu_flush_ecache(void) 1350 1772 jl139090 { 1351 1772 jl139090 flush_ecache(ecache_flushaddr, cpunodes[CPU->cpu_id].ecache_size, 1352 1772 jl139090 cpunodes[CPU->cpu_id].ecache_linesize); 1353 1772 jl139090 } 1354 1772 jl139090 1355 1772 jl139090 static uint8_t 1356 1772 jl139090 flt_to_trap_type(struct async_flt *aflt) 1357 1772 jl139090 { 1358 1772 jl139090 if (aflt->flt_status & OPL_ECC_ISYNC_TRAP) 1359 1772 jl139090 return (TRAP_TYPE_ECC_I); 1360 1772 jl139090 if (aflt->flt_status & OPL_ECC_DSYNC_TRAP) 1361 1772 jl139090 return (TRAP_TYPE_ECC_D); 1362 1772 jl139090 if (aflt->flt_status & OPL_ECC_URGENT_TRAP) 1363 1772 jl139090 return (TRAP_TYPE_URGENT); 1364 3382 jimand return (TRAP_TYPE_UNKNOWN); 1365 1772 jl139090 } 1366 1772 jl139090 1367 1772 jl139090 /* 1368 1772 jl139090 * Encode the data saved in the opl_async_flt_t struct into 1369 1772 jl139090 * the FM ereport payload. 1370 1772 jl139090 */ 1371 1772 jl139090 /* ARGSUSED */ 1372 1772 jl139090 static void 1373 1772 jl139090 cpu_payload_add_aflt(struct async_flt *aflt, nvlist_t *payload, 1374 1772 jl139090 nvlist_t *resource) 1375 1772 jl139090 { 1376 1772 jl139090 opl_async_flt_t *opl_flt = (opl_async_flt_t *)aflt; 1377 1772 jl139090 char unum[UNUM_NAMLEN]; 1378 1772 jl139090 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1379 1772 jl139090 int len; 1380 1772 jl139090 1381 1772 jl139090 1382 1772 jl139090 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_SFSR) { 1383 1772 jl139090 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_SFSR, 1384 5037 jl139090 DATA_TYPE_UINT64, aflt->flt_stat, NULL); 1385 1772 jl139090 } 1386 1772 jl139090 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_SFAR) { 1387 1772 jl139090 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_SFAR, 1388 5037 jl139090 DATA_TYPE_UINT64, aflt->flt_addr, NULL); 1389 1772 jl139090 } 1390 1772 jl139090 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_UGESR) { 1391 1772 jl139090 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_UGESR, 1392 5037 jl139090 DATA_TYPE_UINT64, aflt->flt_stat, NULL); 1393 1772 jl139090 } 1394 1772 jl139090 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_PC) { 1395 1772 jl139090 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_PC, 1396 1772 jl139090 DATA_TYPE_UINT64, (uint64_t)aflt->flt_pc, NULL); 1397 1772 jl139090 } 1398 1772 jl139090 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_TL) { 1399 1772 jl139090 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_TL, 1400 1772 jl139090 DATA_TYPE_UINT8, (uint8_t)aflt->flt_tl, NULL); 1401 1772 jl139090 } 1402 1772 jl139090 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_TT) { 1403 1772 jl139090 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_TT, 1404 1772 jl139090 DATA_TYPE_UINT8, flt_to_trap_type(aflt), NULL); 1405 1772 jl139090 } 1406 1772 jl139090 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_PRIV) { 1407 1772 jl139090 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_PRIV, 1408 1772 jl139090 DATA_TYPE_BOOLEAN_VALUE, 1409 1772 jl139090 (aflt->flt_priv ? B_TRUE : B_FALSE), NULL); 1410 1772 jl139090 } 1411 1772 jl139090 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_FLT_STATUS) { 1412 1772 jl139090 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_FLT_STATUS, 1413 5037 jl139090 DATA_TYPE_UINT64, (uint64_t)aflt->flt_status, NULL); 1414 1772 jl139090 } 1415 1772 jl139090 1416 1772 jl139090 switch (opl_flt->flt_eid_mod) { 1417 1772 jl139090 case OPL_ERRID_CPU: 1418 1772 jl139090 (void) snprintf(sbuf, sizeof (sbuf), "%llX", 1419 5037 jl139090 (u_longlong_t)cpunodes[opl_flt->flt_eid_sid].device_id); 1420 1772 jl139090 (void) fm_fmri_cpu_set(resource, FM_CPU_SCHEME_VERSION, 1421 5037 jl139090 NULL, opl_flt->flt_eid_sid, 1422 5037 jl139090 (uint8_t *)&cpunodes[opl_flt->flt_eid_sid].version, sbuf); 1423 5037 jl139090 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RESOURCE, 1424 5037 jl139090 DATA_TYPE_NVLIST, resource, NULL); 1425 1772 jl139090 break; 1426 1772 jl139090 1427 1772 jl139090 case OPL_ERRID_CHANNEL: 1428 1772 jl139090 /* 1429 1772 jl139090 * No resource is created but the cpumem DE will find 1430 1772 jl139090 * the defective path by retreiving EID from SFSR which is 1431 1772 jl139090 * included in the payload. 1432 1772 jl139090 */ 1433 1772 jl139090 break; 1434 1772 jl139090 1435 1772 jl139090 case OPL_ERRID_MEM: 1436 1772 jl139090 (void) cpu_get_mem_unum_aflt(0, aflt, unum, UNUM_NAMLEN, &len); 1437 5037 jl139090 (void) fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, NULL, 1438 5037 jl139090 unum, NULL, (uint64_t)-1); 1439 1772 jl139090 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RESOURCE, 1440 5037 jl139090 DATA_TYPE_NVLIST, resource, NULL); 1441 1772 jl139090 break; 1442 1772 jl139090 1443 1772 jl139090 case OPL_ERRID_PATH: 1444 1772 jl139090 /* 1445 1772 jl139090 * No resource is created but the cpumem DE will find 1446 1772 jl139090 * the defective path by retreiving EID from SFSR which is 1447 1772 jl139090 * included in the payload. 1448 1772 jl139090 */ 1449 1772 jl139090 break; 1450 1772 jl139090 } 1451 1772 jl139090 } 1452 1772 jl139090 1453 1772 jl139090 /* 1454 1772 jl139090 * Returns whether fault address is valid for this error bit and 1455 1772 jl139090 * whether the address is "in memory" (i.e. pf_is_memory returns 1). 1456 1772 jl139090 */ 1457 1772 jl139090 /*ARGSUSED*/ 1458 1772 jl139090 static int 1459 1772 jl139090 cpu_flt_in_memory(opl_async_flt_t *opl_flt, uint64_t t_afsr_bit) 1460 1772 jl139090 { 1461 1772 jl139090 struct async_flt *aflt = (struct async_flt *)opl_flt; 1462 1772 jl139090 1463 1772 jl139090 if (aflt->flt_status & (OPL_ECC_SYNC_TRAP)) { 1464 1772 jl139090 return ((t_afsr_bit & SFSR_MEMORY) && 1465 1772 jl139090 pf_is_memory(aflt->flt_addr >> MMU_PAGESHIFT)); 1466 1772 jl139090 } 1467 1772 jl139090 return (0); 1468 1772 jl139090 } 1469 1772 jl139090 1470 1772 jl139090 /* 1471 1772 jl139090 * In OPL SCF does the stick synchronization. 1472 1772 jl139090 */ 1473 1772 jl139090 void 1474 1772 jl139090 sticksync_slave(void) 1475 1772 jl139090 { 1476 1772 jl139090 } 1477 1772 jl139090 1478 1772 jl139090 /* 1479 1772 jl139090 * In OPL SCF does the stick synchronization. 1480 1772 jl139090 */ 1481 1772 jl139090 void 1482 1772 jl139090 sticksync_master(void) 1483 1772 jl139090 { 1484 1772 jl139090 } 1485 1772 jl139090 1486 1772 jl139090 /* 1487 1772 jl139090 * Cpu private unitialization. OPL cpus do not use the private area. 1488 1772 jl139090 */ 1489 1772 jl139090 void 1490 1772 jl139090 cpu_uninit_private(struct cpu *cp) 1491 1772 jl139090 { 1492 1772 jl139090 cmp_delete_cpu(cp->cpu_id); 1493 1772 jl139090 } 1494 1772 jl139090 1495 1772 jl139090 /* 1496 1772 jl139090 * Always flush an entire cache. 1497 1772 jl139090 */ 1498 1772 jl139090 void 1499 1772 jl139090 cpu_error_ecache_flush(void) 1500 1772 jl139090 { 1501 1772 jl139090 cpu_flush_ecache(); 1502 1772 jl139090 } 1503 1772 jl139090 1504 1772 jl139090 void 1505 1772 jl139090 cpu_ereport_post(struct async_flt *aflt) 1506 1772 jl139090 { 1507 1772 jl139090 char *cpu_type, buf[FM_MAX_CLASS]; 1508 1772 jl139090 nv_alloc_t *nva = NULL; 1509 1772 jl139090 nvlist_t *ereport, *detector, *resource; 1510 1772 jl139090 errorq_elem_t *eqep; 1511 1772 jl139090 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1512 1772 jl139090 1513 1772 jl139090 if (aflt->flt_panic || panicstr) { 1514 1772 jl139090 eqep = errorq_reserve(ereport_errorq); 1515 1772 jl139090 if (eqep == NULL) 1516 1772 jl139090 return; 1517 1772 jl139090 ereport = errorq_elem_nvl(ereport_errorq, eqep); 1518 1772 jl139090 nva = errorq_elem_nva(ereport_errorq, eqep); 1519 1772 jl139090 } else { 1520 1772 jl139090 ereport = fm_nvlist_create(nva); 1521 1772 jl139090 } 1522 1772 jl139090 1523 1772 jl139090 /* 1524 1772 jl139090 * Create the scheme "cpu" FMRI. 1525 1772 jl139090 */ 1526 1772 jl139090 detector = fm_nvlist_create(nva); 1527 1772 jl139090 resource = fm_nvlist_create(nva); 1528 1772 jl139090 switch (cpunodes[aflt->flt_inst].implementation) { 1529 1772 jl139090 case OLYMPUS_C_IMPL: 1530 1772 jl139090 cpu_type = FM_EREPORT_CPU_SPARC64_VI; 1531 5037 jl139090 break; 1532 5037 jl139090 case JUPITER_IMPL: 1533 5037 jl139090 cpu_type = FM_EREPORT_CPU_SPARC64_VII; 1534 1772 jl139090 break; 1535 1772 jl139090 default: 1536 1772 jl139090 cpu_type = FM_EREPORT_CPU_UNSUPPORTED; 1537 1772 jl139090 break; 1538 1772 jl139090 } 1539 1772 jl139090 (void) snprintf(sbuf, sizeof (sbuf), "%llX", 1540 1772 jl139090 (u_longlong_t)cpunodes[aflt->flt_inst].device_id); 1541 1772 jl139090 (void) fm_fmri_cpu_set(detector, FM_CPU_SCHEME_VERSION, NULL, 1542 1772 jl139090 aflt->flt_inst, (uint8_t *)&cpunodes[aflt->flt_inst].version, 1543 1772 jl139090 sbuf); 1544 1772 jl139090 1545 1772 jl139090 /* 1546 1772 jl139090 * Encode all the common data into the ereport. 1547 1772 jl139090 */ 1548 1772 jl139090 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s.%s", 1549 1772 jl139090 FM_ERROR_CPU, cpu_type, aflt->flt_erpt_class); 1550 1772 jl139090 1551 1772 jl139090 fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, 1552 1772 jl139090 fm_ena_generate(aflt->flt_id, FM_ENA_FMT1), detector, NULL); 1553 1772 jl139090 1554 1772 jl139090 /* 1555 1772 jl139090 * Encode the error specific data that was saved in 1556 1772 jl139090 * the async_flt structure into the ereport. 1557 1772 jl139090 */ 1558 1772 jl139090 cpu_payload_add_aflt(aflt, ereport, resource); 1559 1772 jl139090 1560 1772 jl139090 if (aflt->flt_panic || panicstr) { 1561 1772 jl139090 errorq_commit(ereport_errorq, eqep, ERRORQ_SYNC); 1562 1772 jl139090 } else { 1563 1772 jl139090 (void) fm_ereport_post(ereport, EVCH_TRYHARD); 1564 1772 jl139090 fm_nvlist_destroy(ereport, FM_NVA_FREE); 1565 1772 jl139090 fm_nvlist_destroy(detector, FM_NVA_FREE); 1566 1772 jl139090 fm_nvlist_destroy(resource, FM_NVA_FREE); 1567 1772 jl139090 } 1568 1772 jl139090 } 1569 1772 jl139090 1570 1772 jl139090 void 1571 1772 jl139090 cpu_run_bus_error_handlers(struct async_flt *aflt, int expected) 1572 1772 jl139090 { 1573 1772 jl139090 int status; 1574 1772 jl139090 ddi_fm_error_t de; 1575 1772 jl139090 1576 1772 jl139090 bzero(&de, sizeof (ddi_fm_error_t)); 1577 1772 jl139090 1578 1772 jl139090 de.fme_version = DDI_FME_VERSION; 1579 1772 jl139090 de.fme_ena = fm_ena_generate(aflt->flt_id, FM_ENA_FMT1); 1580 1772 jl139090 de.fme_flag = expected; 1581 1772 jl139090 de.fme_bus_specific = (void *)aflt->flt_addr; 1582 1772 jl139090 status = ndi_fm_handler_dispatch(ddi_root_node(), NULL, &de); 1583 1772 jl139090 if ((aflt->flt_prot == AFLT_PROT_NONE) && (status == DDI_FM_FATAL)) 1584 1772 jl139090 aflt->flt_panic = 1; 1585 1772 jl139090 } 1586 1772 jl139090 1587 1772 jl139090 void 1588 1772 jl139090 cpu_errorq_dispatch(char *error_class, void *payload, size_t payload_sz, 1589 1772 jl139090 errorq_t *eqp, uint_t flag) 1590 1772 jl139090 { 1591 1772 jl139090 struct async_flt *aflt = (struct async_flt *)payload; 1592 1772 jl139090 1593 1772 jl139090 aflt->flt_erpt_class = error_class; 1594 1772 jl139090 errorq_dispatch(eqp, payload, payload_sz, flag); 1595 1772 jl139090 } 1596 1772 jl139090 1597 1772 jl139090 void 1598 1772 jl139090 adjust_hw_copy_limits(int ecache_size) 1599 1772 jl139090 { 1600 1772 jl139090 /* 1601 1772 jl139090 * Set hw copy limits. 1602 1772 jl139090 * 1603 1772 jl139090 * /etc/system will be parsed later and can override one or more 1604 1772 jl139090 * of these settings. 1605 1772 jl139090 * 1606 1772 jl139090 * At this time, ecache size seems only mildly relevant. 1607 1772 jl139090 * We seem to run into issues with the d-cache and stalls 1608 1772 jl139090 * we see on misses. 1609 1772 jl139090 * 1610 1772 jl139090 * Cycle measurement indicates that 2 byte aligned copies fare 1611 1772 jl139090 * little better than doing things with VIS at around 512 bytes. 1612 1772 jl139090 * 4 byte aligned shows promise until around 1024 bytes. 8 Byte 1613 1772 jl139090 * aligned is faster whenever the source and destination data 1614 1772 jl139090 * in cache and the total size is less than 2 Kbytes. The 2K 1615 1772 jl139090 * limit seems to be driven by the 2K write cache. 1616 1772 jl139090 * When more than 2K of copies are done in non-VIS mode, stores 1617 1772 jl139090 * backup in the write cache. In VIS mode, the write cache is 1618 1772 jl139090 * bypassed, allowing faster cache-line writes aligned on cache 1619 1772 jl139090 * boundaries. 1620 1772 jl139090 * 1621 1772 jl139090 * In addition, in non-VIS mode, there is no prefetching, so 1622 1772 jl139090 * for larger copies, the advantage of prefetching to avoid even 1623 1772 jl139090 * occasional cache misses is enough to justify using the VIS code. 1624 1772 jl139090 * 1625 1772 jl139090 * During testing, it was discovered that netbench ran 3% slower 1626 1772 jl139090 * when hw_copy_limit_8 was 2K or larger. Apparently for server 1627 1772 jl139090 * applications, data is only used once (copied to the output 1628 1772 jl139090 * buffer, then copied by the network device off the system). Using 1629 1772 jl139090 * the VIS copy saves more L2 cache state. Network copies are 1630 1772 jl139090 * around 1.3K to 1.5K in size for historical reasons. 1631 1772 jl139090 * 1632 1772 jl139090 * Therefore, a limit of 1K bytes will be used for the 8 byte 1633 1772 jl139090 * aligned copy even for large caches and 8 MB ecache. The 1634 1772 jl139090 * infrastructure to allow different limits for different sized 1635 1772 jl139090 * caches is kept to allow further tuning in later releases. 1636 1772 jl139090 */ 1637 1772 jl139090 1638 1772 jl139090 if (min_ecache_size == 0 && use_hw_bcopy) { 1639 1772 jl139090 /* 1640 1772 jl139090 * First time through - should be before /etc/system 1641 1772 jl139090 * is read. 1642 1772 jl139090 * Could skip the checks for zero but this lets us 1643 1772 jl139090 * preserve any debugger rewrites. 1644 1772 jl139090 */ 1645 1772 jl139090 if (hw_copy_limit_1 == 0) { 1646 1772 jl139090 hw_copy_limit_1 = VIS_COPY_THRESHOLD; 1647 1772 jl139090 priv_hcl_1 = hw_copy_limit_1; 1648 1772 jl139090 } 1649 1772 jl139090 if (hw_copy_limit_2 == 0) { 1650 1772 jl139090 hw_copy_limit_2 = 2 * VIS_COPY_THRESHOLD; 1651 1772 jl139090 priv_hcl_2 = hw_copy_limit_2; 1652 1772 jl139090 } 1653 1772 jl139090 if (hw_copy_limit_4 == 0) { 1654 1772 jl139090 hw_copy_limit_4 = 4 * VIS_COPY_THRESHOLD; 1655 1772 jl139090 priv_hcl_4 = hw_copy_limit_4; 1656 1772 jl139090 } 1657 1772 jl139090 if (hw_copy_limit_8 == 0) { 1658 1772 jl139090 hw_copy_limit_8 = 4 * VIS_COPY_THRESHOLD; 1659 1772 jl139090 priv_hcl_8 = hw_copy_limit_8; 1660 1772 jl139090 } 1661 1772 jl139090 min_ecache_size = ecache_size; 1662 1772 jl139090 } else { 1663 1772 jl139090 /* 1664 1772 jl139090 * MP initialization. Called *after* /etc/system has 1665 1772 jl139090 * been parsed. One CPU has already been initialized. 1666 1772 jl139090 * Need to cater for /etc/system having scragged one 1667 1772 jl139090 * of our values. 1668 1772 jl139090 */ 1669 1772 jl139090 if (ecache_size == min_ecache_size) { 1670 1772 jl139090 /* 1671 1772 jl139090 * Same size ecache. We do nothing unless we 1672 1772 jl139090 * have a pessimistic ecache setting. In that 1673 1772 jl139090 * case we become more optimistic (if the cache is 1674 1772 jl139090 * large enough). 1675 1772 jl139090 */ 1676 1772 jl139090 if (hw_copy_limit_8 == 4 * VIS_COPY_THRESHOLD) { 1677 1772 jl139090 /* 1678 1772 jl139090 * Need to adjust hw_copy_limit* from our 1679 1772 jl139090 * pessimistic uniprocessor value to a more 1680 1772 jl139090 * optimistic UP value *iff* it hasn't been 1681 1772 jl139090 * reset. 1682 1772 jl139090 */ 1683 1772 jl139090 if ((ecache_size > 1048576) && 1684 1772 jl139090 (priv_hcl_8 == hw_copy_limit_8)) { 1685 1772 jl139090 if (ecache_size <= 2097152) 1686 1772 jl139090 hw_copy_limit_8 = 4 * 1687 1772 jl139090 VIS_COPY_THRESHOLD; 1688 1772 jl139090 else if (ecache_size <= 4194304) 1689 1772 jl139090 hw_copy_limit_8 = 4 * 1690 1772 jl139090 VIS_COPY_THRESHOLD; 1691 1772 jl139090 else 1692 1772 jl139090 hw_copy_limit_8 = 4 * 1693 1772 jl139090 VIS_COPY_THRESHOLD; 1694 1772 jl139090 priv_hcl_8 = hw_copy_limit_8; 1695 1772 jl139090 } 1696 1772 jl139090 } 1697 1772 jl139090 } else if (ecache_size < min_ecache_size) { 1698 1772 jl139090 /* 1699 1772 jl139090 * A different ecache size. Can this even happen? 1700 1772 jl139090 */ 1701 1772 jl139090 if (priv_hcl_8 == hw_copy_limit_8) { 1702 1772 jl139090 /* 1703 1772 jl139090 * The previous value that we set 1704 1772 jl139090 * is unchanged (i.e., it hasn't been 1705 1772 jl139090 * scragged by /etc/system). Rewrite it. 1706 1772 jl139090 */ 1707 1772 jl139090 if (ecache_size <= 1048576) 1708 1772 jl139090 hw_copy_limit_8 = 8 * 1709 1772 jl139090 VIS_COPY_THRESHOLD; 1710 1772 jl139090 else if (ecache_size <= 2097152) 1711 1772 jl139090 hw_copy_limit_8 = 8 * 1712 1772 jl139090 VIS_COPY_THRESHOLD; 1713 1772 jl139090 else if (ecache_size <= 4194304) 1714 1772 jl139090 hw_copy_limit_8 = 8 * 1715 1772 jl139090 VIS_COPY_THRESHOLD; 1716 1772 jl139090 else 1717 1772 jl139090 hw_copy_limit_8 = 10 * 1718 1772 jl139090 VIS_COPY_THRESHOLD; 1719 1772 jl139090 priv_hcl_8 = hw_copy_limit_8; 1720 1772 jl139090 min_ecache_size = ecache_size; 1721 1772 jl139090 } 1722 1772 jl139090 } 1723 1772 jl139090 } 1724 1772 jl139090 } 1725 1772 jl139090 1726 1772 jl139090 #define VIS_BLOCKSIZE 64 1727 1772 jl139090 1728 1772 jl139090 int 1729 1772 jl139090 dtrace_blksuword32_err(uintptr_t addr, uint32_t *data) 1730 1772 jl139090 { 1731 1772 jl139090 int ret, watched; 1732 1772 jl139090 1733 1772 jl139090 watched = watch_disable_addr((void *)addr, VIS_BLOCKSIZE, S_WRITE); 1734 1772 jl139090 ret = dtrace_blksuword32(addr, data, 0); 1735 1772 jl139090 if (watched) 1736 1772 jl139090 watch_enable_addr((void *)addr, VIS_BLOCKSIZE, S_WRITE); 1737 1772 jl139090 1738 1772 jl139090 return (ret); 1739 1772 jl139090 } 1740 1772 jl139090 1741 1772 jl139090 void 1742 1772 jl139090 opl_cpu_reg_init() 1743 1772 jl139090 { 1744 1772 jl139090 uint64_t this_cpu_log; 1745 1772 jl139090 1746 6259 mb158278 if (cpu[getprocessorid()] == &cpu0 && opl_cpu0_log_setup == 1) { 1747 5414 mb158278 /* 1748 5414 mb158278 * Support for "ta 3" 1749 5414 mb158278 */ 1750 5414 mb158278 opl_ta3(); 1751 6259 mb158278 1752 6259 mb158278 /* 1753 6259 mb158278 * If we are being called at boot time on cpu0 the error 1754 6259 mb158278 * log is already set up in cpu_setup. Clear the 1755 6259 mb158278 * opl_cpu0_log_setup flag so that a subsequent DR of cpu0 will 1756 6259 mb158278 * do the proper initialization. 1757 6259 mb158278 */ 1758 6259 mb158278 opl_cpu0_log_setup = 0; 1759 1772 jl139090 return; 1760 5414 mb158278 } 1761 1772 jl139090 1762 1772 jl139090 /* 1763 1772 jl139090 * Initialize Error log Scratch register for error handling. 1764 1772 jl139090 */ 1765 1772 jl139090 1766 1772 jl139090 this_cpu_log = va_to_pa((void*)(((uint64_t)opl_err_log) + 1767 5037 jl139090 ERRLOG_BUFSZ * (getprocessorid()))); 1768 1772 jl139090 opl_error_setup(this_cpu_log); 1769 1772 jl139090 } 1770 1772 jl139090 1771 1772 jl139090 /* 1772 1772 jl139090 * Queue one event in ue_queue based on ecc_type_to_info entry. 1773 1772 jl139090 */ 1774 1772 jl139090 static void 1775 1772 jl139090 cpu_queue_one_event(opl_async_flt_t *opl_flt, char *reason, 1776 1772 jl139090 ecc_type_to_info_t *eccp) 1777 1772 jl139090 { 1778 1772 jl139090 struct async_flt *aflt = (struct async_flt *)opl_flt; 1779 1772 jl139090 1780 1772 jl139090 if (reason && 1781 1772 jl139090 strlen(reason) + strlen(eccp->ec_reason) < MAX_REASON_STRING) { 1782 1772 jl139090 (void) strcat(reason, eccp->ec_reason); 1783 1772 jl139090 } 1784 1772 jl139090 1785 1772 jl139090 opl_flt->flt_bit = eccp->ec_afsr_bit; 1786 1772 jl139090 opl_flt->flt_type = eccp->ec_flt_type; 1787 1772 jl139090 aflt->flt_in_memory = cpu_flt_in_memory(opl_flt, opl_flt->flt_bit); 1788 1772 jl139090 aflt->flt_payload = eccp->ec_err_payload; 1789 1772 jl139090 1790 1772 jl139090 ASSERT(aflt->flt_status & (OPL_ECC_SYNC_TRAP|OPL_ECC_URGENT_TRAP)); 1791 5037 jl139090 cpu_errorq_dispatch(eccp->ec_err_class, (void *)opl_flt, 1792 5037 jl139090 sizeof (opl_async_flt_t), ue_queue, aflt->flt_panic); 1793 1772 jl139090 } 1794 1772 jl139090 1795 1772 jl139090 /* 1796 1772 jl139090 * Queue events on async event queue one event per error bit. 1797 1772 jl139090 * Return number of events queued. 1798 1772 jl139090 */ 1799 1772 jl139090 int 1800 1772 jl139090 cpu_queue_events(opl_async_flt_t *opl_flt, char *reason, uint64_t t_afsr_errs) 1801 1772 jl139090 { 1802 1772 jl139090 struct async_flt *aflt = (struct async_flt *)opl_flt; 1803 1772 jl139090 ecc_type_to_info_t *eccp; 1804 1772 jl139090 int nevents = 0; 1805 1772 jl139090 1806 1772 jl139090 /* 1807 1772 jl139090 * Queue expected errors, error bit and fault type must must match 1808 1772 jl139090 * in the ecc_type_to_info table. 1809 1772 jl139090 */ 1810 1772 jl139090 for (eccp = ecc_type_to_info; t_afsr_errs != 0 && eccp->ec_desc != NULL; 1811 5037 jl139090 eccp++) { 1812 1772 jl139090 if ((eccp->ec_afsr_bit & t_afsr_errs) != 0 && 1813 1772 jl139090 (eccp->ec_flags & aflt->flt_status) != 0) { 1814 1772 jl139090 /* 1815 1772 jl139090 * UE error event can be further 1816 1772 jl139090 * classified/breakdown into finer granularity 1817 1772 jl139090 * based on the flt_eid_mod value set by HW. We do 1818 1772 jl139090 * special handling here so that we can report UE 1819 1772 jl139090 * error in finer granularity as ue_mem, 1820 1772 jl139090 * ue_channel, ue_cpu or ue_path. 1821 1772 jl139090 */ 1822 1772 jl139090 if (eccp->ec_flt_type == OPL_CPU_SYNC_UE) { 1823 5037 jl139090 opl_flt->flt_eid_mod = (aflt->flt_stat & 1824 5037 jl139090 SFSR_EID_MOD) >> SFSR_EID_MOD_SHIFT; 1825 5037 jl139090 opl_flt->flt_eid_sid = (aflt->flt_stat & 1826 5037 jl139090 SFSR_EID_SID) >> SFSR_EID_SID_SHIFT; 1827 1772 jl139090 /* 1828 1772 jl139090 * Need to advance eccp pointer by flt_eid_mod 1829 1772 jl139090 * so that we get an appropriate ecc pointer 1830 1772 jl139090 * 1831 1772 jl139090 * EID # of advances 1832 1772 jl139090 * ---------------------------------- 1833 1772 jl139090 * OPL_ERRID_MEM 0 1834 1772 jl139090 * OPL_ERRID_CHANNEL 1 1835 1772 jl139090 * OPL_ERRID_CPU 2 1836 1772 jl139090 * OPL_ERRID_PATH 3 1837 1772 jl139090 */ 1838 1772 jl139090 eccp += opl_flt->flt_eid_mod; 1839 1772 jl139090 } 1840 1772 jl139090 cpu_queue_one_event(opl_flt, reason, eccp); 1841 1772 jl139090 t_afsr_errs &= ~eccp->ec_afsr_bit; 1842 1772 jl139090 nevents++; 1843 1772 jl139090 } 1844 1772 jl139090 } 1845 1772 jl139090 1846 1772 jl139090 return (nevents); 1847 1772 jl139090 } 1848 1772 jl139090 1849 1772 jl139090 /* 1850 1772 jl139090 * Sync. error wrapper functions. 1851 1772 jl139090 * We use these functions in order to transfer here from the 1852 1772 jl139090 * nucleus trap handler information about trap type (data or 1853 1772 jl139090 * instruction) and trap level (0 or above 0). This way we 1854 1772 jl139090 * get rid of using SFSR's reserved bits. 1855 1772 jl139090 */ 1856 1772 jl139090 1857 1772 jl139090 #define OPL_SYNC_TL0 0 1858 1772 jl139090 #define OPL_SYNC_TL1 1 1859 1772 jl139090 #define OPL_ISYNC_ERR 0 1860 1772 jl139090 #define OPL_DSYNC_ERR 1 1861 1772 jl139090 1862 1772 jl139090 void 1863 1772 jl139090 opl_cpu_isync_tl0_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1864 1772 jl139090 { 1865 1772 jl139090 uint64_t t_sfar = p_sfar; 1866 1772 jl139090 uint64_t t_sfsr = p_sfsr; 1867 1772 jl139090 1868 1772 jl139090 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1869 1772 jl139090 OPL_SYNC_TL0, OPL_ISYNC_ERR); 1870 1772 jl139090 } 1871 1772 jl139090 1872 1772 jl139090 void 1873 1772 jl139090 opl_cpu_isync_tl1_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1874 1772 jl139090 { 1875 1772 jl139090 uint64_t t_sfar = p_sfar; 1876 1772 jl139090 uint64_t t_sfsr = p_sfsr; 1877 1772 jl139090 1878 1772 jl139090 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1879 1772 jl139090 OPL_SYNC_TL1, OPL_ISYNC_ERR); 1880 1772 jl139090 } 1881 1772 jl139090 1882 1772 jl139090 void 1883 1772 jl139090 opl_cpu_dsync_tl0_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1884 1772 jl139090 { 1885 1772 jl139090 uint64_t t_sfar = p_sfar; 1886 1772 jl139090 uint64_t t_sfsr = p_sfsr; 1887 1772 jl139090 1888 1772 jl139090 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1889 1772 jl139090 OPL_SYNC_TL0, OPL_DSYNC_ERR); 1890 1772 jl139090 } 1891 1772 jl139090 1892 1772 jl139090 void 1893 1772 jl139090 opl_cpu_dsync_tl1_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1894 1772 jl139090 { 1895 1772 jl139090 uint64_t t_sfar = p_sfar; 1896 1772 jl139090 uint64_t t_sfsr = p_sfsr; 1897 1772 jl139090 1898 1772 jl139090 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1899 1772 jl139090 OPL_SYNC_TL1, OPL_DSYNC_ERR); 1900 1772 jl139090 } 1901 1772 jl139090 1902 1772 jl139090 /* 1903 1772 jl139090 * The fj sync err handler transfers control here for UE, BERR, TO, TLB_MUL 1904 1772 jl139090 * and TLB_PRT. 1905 1772 jl139090 * This function is designed based on cpu_deferred_error(). 1906 1772 jl139090 */ 1907 1772 jl139090 1908 1772 jl139090 static void 1909 1772 jl139090 opl_cpu_sync_error(struct regs *rp, ulong_t t_sfar, ulong_t t_sfsr, 1910 1772 jl139090 uint_t tl, uint_t derr) 1911 1772 jl139090 { 1912 1772 jl139090 opl_async_flt_t opl_flt; 1913 1772 jl139090 struct async_flt *aflt; 1914 1772 jl139090 int trampolined = 0; 1915 1772 jl139090 char pr_reason[MAX_REASON_STRING]; 1916 1772 jl139090 uint64_t log_sfsr; 1917 1772 jl139090 int expected = DDI_FM_ERR_UNEXPECTED; 1918 1772 jl139090 ddi_acc_hdl_t *hp; 1919 1772 jl139090 1920 1772 jl139090 /* 1921 1772 jl139090 * We need to look at p_flag to determine if the thread detected an 1922 1772 jl139090 * error while dumping core. We can't grab p_lock here, but it's ok 1923 1772 jl139090 * because we just need a consistent snapshot and we know that everyone 1924 1772 jl139090 * else will store a consistent set of bits while holding p_lock. We 1925 1772 jl139090 * don't have to worry about a race because SDOCORE is set once prior 1926 1772 jl139090 * to doing i/o from the process's address space and is never cleared. 1927 1772 jl139090 */ 1928 1772 jl139090 uint_t pflag = ttoproc(curthread)->p_flag; 1929 1772 jl139090 1930 1772 jl139090 pr_reason[0] = '\0'; 1931 1772 jl139090 1932 1772 jl139090 /* 1933 1772 jl139090 * handle the specific error 1934 1772 jl139090 */ 1935 1772 jl139090 bzero(&opl_flt, sizeof (opl_async_flt_t)); 1936 1772 jl139090 aflt = (struct async_flt *)&opl_flt; 1937 1772 jl139090 aflt->flt_id = gethrtime_waitfree(); 1938 1772 jl139090 aflt->flt_bus_id = getprocessorid(); 1939 1772 jl139090 aflt->flt_inst = CPU->cpu_id; 1940 1772 jl139090 aflt->flt_stat = t_sfsr; 1941 1772 jl139090 aflt->flt_addr = t_sfar; 1942 1772 jl139090 aflt->flt_pc = (caddr_t)rp->r_pc; 1943 1772 jl139090 aflt->flt_prot = (uchar_t)AFLT_PROT_NONE; 1944 1772 jl139090 aflt->flt_class = (uchar_t)CPU_FAULT; 1945 5037 jl139090 aflt->flt_priv = (uchar_t)(tl == 1 ? 1 : ((rp->r_tstate & 1946 5037 jl139090 TSTATE_PRIV) ? 1 : 0)); 1947 1772 jl139090 aflt->flt_tl = (uchar_t)tl; 1948 1772 jl139090 aflt->flt_panic = (uchar_t)(tl != 0 || aft_testfatal != 0 || 1949 1772 jl139090 (t_sfsr & (SFSR_TLB_MUL|SFSR_TLB_PRT)) != 0); 1950 1772 jl139090 aflt->flt_core = (pflag & SDOCORE) ? 1 : 0; 1951 1772 jl139090 aflt->flt_status = (derr) ? OPL_ECC_DSYNC_TRAP : OPL_ECC_ISYNC_TRAP; 1952 1772 jl139090 1953 1772 jl139090 /* 1954 1772 jl139090 * If SFSR.FV is not set, both SFSR and SFAR/SFPAR values are uncertain. 1955 1772 jl139090 * So, clear all error bits to avoid mis-handling and force the system 1956 1772 jl139090 * panicked. 1957 1772 jl139090 * We skip all the procedures below down to the panic message call. 1958 1772 jl139090 */ 1959 1772 jl139090 if (!(t_sfsr & SFSR_FV)) { 1960 1772 jl139090 opl_flt.flt_type = OPL_CPU_INV_SFSR; 1961 1772 jl139090 aflt->flt_panic = 1; 1962 1772 jl139090 aflt->flt_payload = FM_EREPORT_PAYLOAD_SYNC; 1963 5037 jl139090 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_SFSR, (void *)&opl_flt, 1964 5037 jl139090 sizeof (opl_async_flt_t), ue_queue, aflt->flt_panic); 1965 1772 jl139090 fm_panic("%sErrors(s)", "invalid SFSR"); 1966 1772 jl139090 } 1967 1772 jl139090 1968 1772 jl139090 /* 1969 1772 jl139090 * If either UE and MK bit is off, this is not valid UE error. 1970 1772 jl139090 * If it is not valid UE error, clear UE & MK_UE bits to prevent 1971 1772 jl139090 * mis-handling below. 1972 1772 jl139090 * aflt->flt_stat keeps the original bits as a reference. 1973 1772 jl139090 */ 1974 1772 jl139090 if ((t_sfsr & (SFSR_MK_UE|SFSR_UE)) != 1975 1772 jl139090 (SFSR_MK_UE|SFSR_UE)) { 1976 1772 jl139090 t_sfsr &= ~(SFSR_MK_UE|SFSR_UE); 1977 1772 jl139090 } 1978 1772 jl139090 1979 1772 jl139090 /* 1980 1772 jl139090 * If the trap occurred in privileged mode at TL=0, we need to check to 1981 1772 jl139090 * see if we were executing in the kernel under on_trap() or t_lofault 1982 1772 jl139090 * protection. If so, modify the saved registers so that we return 1983 1772 jl139090 * from the trap to the appropriate trampoline routine. 1984 1772 jl139090 */ 1985 1772 jl139090 if (!aflt->flt_panic && aflt->flt_priv && tl == 0) { 1986 1772 jl139090 if (curthread->t_ontrap != NULL) { 1987 1772 jl139090 on_trap_data_t *otp = curthread->t_ontrap; 1988 1772 jl139090 1989 1772 jl139090 if (otp->ot_prot & OT_DATA_EC) { 1990 1772 jl139090 aflt->flt_prot = (uchar_t)AFLT_PROT_EC; 1991 1772 jl139090 otp->ot_trap |= (ushort_t)OT_DATA_EC; 1992 1772 jl139090 rp->r_pc = otp->ot_trampoline; 1993 1772 jl139090 rp->r_npc = rp->r_pc + 4; 1994 1772 jl139090 trampolined = 1; 1995 1772 jl139090 } 1996 1772 jl139090 1997 1772 jl139090 if ((t_sfsr & (SFSR_TO | SFSR_BERR)) && 1998 1772 jl139090 (otp->ot_prot & OT_DATA_ACCESS)) { 1999 1772 jl139090 aflt->flt_prot = (uchar_t)AFLT_PROT_ACCESS; 2000 1772 jl139090 otp->ot_trap |= (ushort_t)OT_DATA_ACCESS; 2001 1772 jl139090 rp->r_pc = otp->ot_trampoline; 2002 1772 jl139090 rp->r_npc = rp->r_pc + 4; 2003 1772 jl139090 trampolined = 1; 2004 1772 jl139090 /* 2005 1772 jl139090 * for peeks and caut_gets errors are expected 2006 1772 jl139090 */ 2007 1772 jl139090 hp = (ddi_acc_hdl_t *)otp->ot_handle; 2008 1772 jl139090 if (!hp) 2009 1772 jl139090 expected = DDI_FM_ERR_PEEK; 2010 1772 jl139090 else if (hp->ah_acc.devacc_attr_access == 2011 1772 jl139090 DDI_CAUTIOUS_ACC) 2012 1772 jl139090 expected = DDI_FM_ERR_EXPECTED; 2013 1772 jl139090 } 2014 1772 jl139090 2015 1772 jl139090 } else if (curthread->t_lofault) { 2016 1772 jl139090 aflt->flt_prot = AFLT_PROT_COPY; 2017 1772 jl139090 rp->r_g1 = EFAULT; 2018 1772 jl139090 rp->r_pc = curthread->t_lofault; 2019 1772 jl139090 rp->r_npc = rp->r_pc + 4; 2020 1772 jl139090 trampolined = 1; 2021 1772 jl139090 } 2022 1772 jl139090 } 2023 1772 jl139090 2024 1772 jl139090 /* 2025 1772 jl139090 * If we're in user mode or we're doing a protected copy, we either 2026 1772 jl139090 * want the ASTON code below to send a signal to the user process 2027 1772 jl139090 * or we want to panic if aft_panic is set. 2028 1772 jl139090 * 2029 1772 jl139090 * If we're in privileged mode and we're not doing a copy, then we 2030 1772 jl139090 * need to check if we've trampolined. If we haven't trampolined, 2031 1772 jl139090 * we should panic. 2032 1772 jl139090 */ 2033 1772 jl139090 if (!aflt->flt_priv || aflt->flt_prot == AFLT_PROT_COPY) { 2034 1772 jl139090 if (t_sfsr & (SFSR_ERRS & ~(SFSR_BERR | SFSR_TO))) 2035 1772 jl139090 aflt->flt_panic |= aft_panic; 2036 1772 jl139090 } else if (!trampolined) { 2037 1772 jl139090 aflt->flt_panic = 1; 2038 1772 jl139090 } 2039 1772 jl139090 2040 1772 jl139090 /* 2041 1772 jl139090 * If we've trampolined due to a privileged TO or BERR, or if an 2042 1772 jl139090 * unprivileged TO or BERR occurred, we don't want to enqueue an 2043 1772 jl139090 * event for that TO or BERR. Queue all other events (if any) besides 2044 1772 jl139090 * the TO/BERR. 2045 1772 jl139090 */ 2046 1772 jl139090 log_sfsr = t_sfsr; 2047 1772 jl139090 if (trampolined) { 2048 1772 jl139090 log_sfsr &= ~(SFSR_TO | SFSR_BERR); 2049 1772 jl139090 } else if (!aflt->flt_priv) { 2050 1772 jl139090 /* 2051 1772 jl139090 * User mode, suppress messages if 2052 1772 jl139090 * cpu_berr_to_verbose is not set. 2053 1772 jl139090 */ 2054 1772 jl139090 if (!cpu_berr_to_verbose) 2055 1772 jl139090 log_sfsr &= ~(SFSR_TO | SFSR_BERR); 2056 1772 jl139090 } 2057 1772 jl139090 2058 5037 jl139090 if (((log_sfsr & SFSR_ERRS) && (cpu_queue_events(&opl_flt, pr_reason, 2059 5037 jl139090 t_sfsr) == 0)) || ((t_sfsr & SFSR_ERRS) == 0)) { 2060 1772 jl139090 opl_flt.flt_type = OPL_CPU_INV_SFSR; 2061 1772 jl139090 aflt->flt_payload = FM_EREPORT_PAYLOAD_SYNC; 2062 5037 jl139090 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_SFSR, (void *)&opl_flt, 2063 5037 jl139090 sizeof (opl_async_flt_t), ue_queue, aflt->flt_panic); 2064 1772 jl139090 } 2065 1772 jl139090 2066 1772 jl139090 if (t_sfsr & (SFSR_UE|SFSR_TO|SFSR_BERR)) { 2067 1772 jl139090 cpu_run_bus_error_handlers(aflt, expected); 2068 1772 jl139090 } 2069 1772 jl139090 2070 1772 jl139090 /* 2071 1772 jl139090 * Panic here if aflt->flt_panic has been set. Enqueued errors will 2072 1772 jl139090 * be logged as part of the panic flow. 2073 1772 jl139090 */ 2074 1772 jl139090 if (aflt->flt_panic) { 2075 1772 jl139090 if (pr_reason[0] == 0) 2076 1772 jl139090 strcpy(pr_reason, "invalid SFSR "); 2077 1772 jl139090 2078 1772 jl139090 fm_panic("%sErrors(s)", pr_reason); 2079 1772 jl139090 } 2080 1772 jl139090 2081 1772 jl139090 /* 2082 1772 jl139090 * If we queued an error and we are going to return from the trap and 2083 1772 jl139090 * the error was in user mode or inside of a copy routine, set AST flag 2084 1772 jl139090 * so the queue will be drained before returning to user mode. The 2085 1772 jl139090 * AST processing will also act on our failure policy. 2086 1772 jl139090 */ 2087 1772 jl139090 if (!aflt->flt_priv || aflt->flt_prot == AFLT_PROT_COPY) { 2088 1772 jl139090 int pcb_flag = 0; 2089 1772 jl139090 2090 5037 jl139090 if (t_sfsr & (SFSR_ERRS & ~(SFSR_BERR | SFSR_TO))) 2091 1772 jl139090 pcb_flag |= ASYNC_HWERR; 2092 1772 jl139090 2093 1772 jl139090 if (t_sfsr & SFSR_BERR) 2094 1772 jl139090 pcb_flag |= ASYNC_BERR; 2095 1772 jl139090 2096 1772 jl139090 if (t_sfsr & SFSR_TO) 2097 1772 jl139090 pcb_flag |= ASYNC_BTO; 2098 1772 jl139090 2099 1772 jl139090 ttolwp(curthread)->lwp_pcb.pcb_flags |= pcb_flag; 2100 1772 jl139090 aston(curthread); 2101 1772 jl139090 } 2102 1772 jl139090 } 2103 1772 jl139090 2104 1772 jl139090 /*ARGSUSED*/ 2105 1772 jl139090 void 2106 1772 jl139090 opl_cpu_urgent_error(struct regs *rp, ulong_t p_ugesr, ulong_t tl) 2107 1772 jl139090 { 2108 1772 jl139090 opl_async_flt_t opl_flt; 2109 1772 jl139090 struct async_flt *aflt; 2110 1772 jl139090 char pr_reason[MAX_REASON_STRING]; 2111 1772 jl139090 2112 1772 jl139090 /* normalize tl */ 2113 1772 jl139090 tl = (tl >= 2 ? 1 : 0); 2114 1772 jl139090 pr_reason[0] = '\0'; 2115 1772 jl139090 2116 1772 jl139090 bzero(&opl_flt, sizeof (opl_async_flt_t)); 2117 1772 jl139090 aflt = (struct async_flt *)&opl_flt; 2118 1772 jl139090 aflt->flt_id = gethrtime_waitfree(); 2119 1772 jl139090 aflt->flt_bus_id = getprocessorid(); 2120 1772 jl139090 aflt->flt_inst = CPU->cpu_id; 2121 1772 jl139090 aflt->flt_stat = p_ugesr; 2122 1772 jl139090 aflt->flt_pc = (caddr_t)rp->r_pc; 2123 1772 jl139090 aflt->flt_class = (uchar_t)CPU_FAULT; 2124 1772 jl139090 aflt->flt_tl = tl; 2125 5037 jl139090 aflt->flt_priv = (uchar_t)(tl == 1 ? 1 : ((rp->r_tstate & TSTATE_PRIV) ? 2126 5037 jl139090 1 : 0)); 2127 1772 jl139090 aflt->flt_status = OPL_ECC_URGENT_TRAP; 2128 1772 jl139090 aflt->flt_panic = 1; 2129 1772 jl139090 /* 2130 1772 jl139090 * HW does not set mod/sid in case of urgent error. 2131 1772 jl139090 * So we have to set it here. 2132 1772 jl139090 */ 2133 1772 jl139090 opl_flt.flt_eid_mod = OPL_ERRID_CPU; 2134 1772 jl139090 opl_flt.flt_eid_sid = aflt->flt_inst; 2135 1772 jl139090 2136 1772 jl139090 if (cpu_queue_events(&opl_flt, pr_reason, p_ugesr) == 0) { 2137 1772 jl139090 opl_flt.flt_type = OPL_CPU_INV_UGESR; 2138 1772 jl139090 aflt->flt_payload = FM_EREPORT_PAYLOAD_URGENT; 2139 5037 jl139090 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_URG, (void *)&opl_flt, 2140 5037 jl139090 sizeof (opl_async_flt_t), ue_queue, aflt->flt_panic); 2141 1772 jl139090 } 2142 1772 jl139090 2143 1772 jl139090 fm_panic("Urgent Error"); 2144 1772 jl139090 } 2145 1772 jl139090 2146 1772 jl139090 /* 2147 1772 jl139090 * Initialization error counters resetting. 2148 1772 jl139090 */ 2149 1772 jl139090 /* ARGSUSED */ 2150 1772 jl139090 static void 2151 1772 jl139090 opl_ras_online(void *arg, cpu_t *cp, cyc_handler_t *hdlr, cyc_time_t *when) 2152 1772 jl139090 { 2153 1772 jl139090 hdlr->cyh_func = (cyc_func_t)ras_cntr_reset; 2154 1772 jl139090 hdlr->cyh_level = CY_LOW_LEVEL; 2155 1772 jl139090 hdlr->cyh_arg = (void *)(uintptr_t)cp->cpu_id; 2156 1772 jl139090 2157 1772 jl139090 when->cyt_when = cp->cpu_id * (((hrtime_t)NANOSEC * 10)/ NCPU); 2158 1772 jl139090 when->cyt_interval = (hrtime_t)NANOSEC * opl_async_check_interval; 2159 1772 jl139090 } 2160 1772 jl139090 2161 1772 jl139090 void 2162 1772 jl139090 cpu_mp_init(void) 2163 1772 jl139090 { 2164 1772 jl139090 cyc_omni_handler_t hdlr; 2165 1772 jl139090 2166 1772 jl139090 hdlr.cyo_online = opl_ras_online; 2167 1772 jl139090 hdlr.cyo_offline = NULL; 2168 1772 jl139090 hdlr.cyo_arg = NULL; 2169 1772 jl139090 mutex_enter(&cpu_lock); 2170 1772 jl139090 (void) cyclic_add_omni(&hdlr); 2171 1772 jl139090 mutex_exit(&cpu_lock); 2172 1772 jl139090 } 2173 1772 jl139090 2174 7029 jimand int heaplp_use_stlb = 0; 2175 3309 jimand 2176 1772 jl139090 void 2177 1772 jl139090 mmu_init_kernel_pgsz(struct hat *hat) 2178 1772 jl139090 { 2179 3309 jimand uint_t tte = page_szc(segkmem_lpsize); 2180 3309 jimand uchar_t new_cext_primary, new_cext_nucleus; 2181 3309 jimand 2182 3309 jimand if (heaplp_use_stlb == 0) { 2183 3309 jimand /* do not reprogram stlb */ 2184 3309 jimand tte = TTE8K; 2185 5584 jimand } else if (!plat_prom_preserve_kctx_is_supported()) { 2186 5584 jimand /* OBP does not support non-zero primary context */ 2187 5584 jimand tte = TTE8K; 2188 5584 jimand heaplp_use_stlb = 0; 2189 3309 jimand } 2190 3309 jimand 2191 3309 jimand new_cext_nucleus = TAGACCEXT_MKSZPAIR(tte, TTE8K); 2192 3309 jimand new_cext_primary = TAGACCEXT_MKSZPAIR(TTE8K, tte); 2193 3309 jimand 2194 3309 jimand hat->sfmmu_cext = new_cext_primary; 2195 3309 jimand kcontextreg = ((uint64_t)new_cext_nucleus << CTXREG_NEXT_SHIFT) | 2196 5037 jl139090 ((uint64_t)new_cext_primary << CTXREG_EXT_SHIFT); 2197 1772 jl139090 } 2198 1772 jl139090 2199 1772 jl139090 size_t 2200 1772 jl139090 mmu_get_kernel_lpsize(size_t lpsize) 2201 1772 jl139090 { 2202 1772 jl139090 uint_t tte; 2203 1772 jl139090 2204 1772 jl139090 if (lpsize == 0) { 2205 1772 jl139090 /* no setting for segkmem_lpsize in /etc/system: use default */ 2206 1772 jl139090 return (MMU_PAGESIZE4M); 2207 1772 jl139090 } 2208 1772 jl139090 2209 1772 jl139090 for (tte = TTE8K; tte <= TTE4M; tte++) { 2210 1772 jl139090 if (lpsize == TTEBYTES(tte)) 2211 1772 jl139090 return (lpsize); 2212 1772 jl139090 } 2213 1772 jl139090 2214 1772 jl139090 return (TTEBYTES(TTE8K)); 2215 1772 jl139090 } 2216 1772 jl139090 2217 1772 jl139090 /* 2218 5414 mb158278 * Support for ta 3. 2219 5414 mb158278 * We allocate here a buffer for each cpu 2220 5414 mb158278 * for saving the current register window. 2221 5414 mb158278 */ 2222 5414 mb158278 typedef struct win_regs { 2223 5414 mb158278 uint64_t l[8]; 2224 5414 mb158278 uint64_t i[8]; 2225 5414 mb158278 } win_regs_t; 2226 5414 mb158278 static void 2227 5414 mb158278 opl_ta3(void) 2228 5414 mb158278 { 2229 6259 mb158278 /* 2230 6259 mb158278 * opl_ta3 should only be called once at boot time. 2231 6259 mb158278 */ 2232 6259 mb158278 if (opl_ta3_save == NULL) 2233 6259 mb158278 opl_ta3_save = (char *)kmem_alloc(NCPU * sizeof (win_regs_t), 2234 6259 mb158278 KM_SLEEP); 2235 5414 mb158278 } 2236 5414 mb158278 2237 5414 mb158278 /* 2238 1772 jl139090 * The following are functions that are unused in 2239 1772 jl139090 * OPL cpu module. They are defined here to resolve 2240 1772 jl139090 * dependencies in the "unix" module. 2241 1772 jl139090 * Unused functions that should never be called in 2242 1772 jl139090 * OPL are coded with ASSERT(0). 2243 1772 jl139090 */ 2244 1772 jl139090 2245 1772 jl139090 void 2246 1772 jl139090 cpu_disable_errors(void) 2247 1772 jl139090 {} 2248 1772 jl139090 2249 1772 jl139090 void 2250 1772 jl139090 cpu_enable_errors(void) 2251 1772 jl139090 { ASSERT(0); } 2252 1772 jl139090 2253 1772 jl139090 /*ARGSUSED*/ 2254 1772 jl139090 void 2255 1772 jl139090 cpu_ce_scrub_mem_err(struct async_flt *ecc, boolean_t t) 2256 1772 jl139090 { ASSERT(0); } 2257 1772 jl139090 2258 1772 jl139090 /*ARGSUSED*/ 2259 1772 jl139090 void 2260 1772 jl139090 cpu_faulted_enter(struct cpu *cp) 2261 1772 jl139090 {} 2262 1772 jl139090 2263 1772 jl139090 /*ARGSUSED*/ 2264 1772 jl139090 void 2265 1772 jl139090 cpu_faulted_exit(struct cpu *cp) 2266 1772 jl139090 {} 2267 1772 jl139090 2268 1772 jl139090 /*ARGSUSED*/ 2269 1772 jl139090 void 2270 1772 jl139090 cpu_check_allcpus(struct async_flt *aflt) 2271 1772 jl139090 {} 2272 1772 jl139090 2273 1772 jl139090 /*ARGSUSED*/ 2274 1772 jl139090 void 2275 1772 jl139090 cpu_ce_log_err(struct async_flt *aflt, errorq_elem_t *t) 2276 1772 jl139090 { ASSERT(0); } 2277 1772 jl139090 2278 1772 jl139090 /*ARGSUSED*/ 2279 1772 jl139090 void 2280 1772 jl139090 cpu_check_ce(int flag, uint64_t pa, caddr_t va, uint_t psz) 2281 1772 jl139090 { ASSERT(0); } 2282 1772 jl139090 2283 1772 jl139090 /*ARGSUSED*/ 2284 1772 jl139090 void 2285 1772 jl139090 cpu_ce_count_unum(struct async_flt *ecc, int len, char *unum) 2286 1772 jl139090 { ASSERT(0); } 2287 1772 jl139090 2288 1772 jl139090 /*ARGSUSED*/ 2289 1772 jl139090 void 2290 1772 jl139090 cpu_busy_ecache_scrub(struct cpu *cp) 2291 1772 jl139090 {} 2292 1772 jl139090 2293 1772 jl139090 /*ARGSUSED*/ 2294 1772 jl139090 void 2295 1772 jl139090 cpu_idle_ecache_scrub(struct cpu *cp) 2296 1772 jl139090 {} 2297 1772 jl139090 2298 1772 jl139090 /* ARGSUSED */ 2299 1772 jl139090 void 2300 1772 jl139090 cpu_change_speed(uint64_t divisor, uint64_t arg2) 2301 1772 jl139090 { ASSERT(0); } 2302 1772 jl139090 2303 1772 jl139090 void 2304 1772 jl139090 cpu_init_cache_scrub(void) 2305 1772 jl139090 {} 2306 1772 jl139090 2307 1772 jl139090 /* ARGSUSED */ 2308 1772 jl139090 int 2309 1772 jl139090 cpu_get_mem_sid(char *unum, char *buf, int buflen, int *lenp) 2310 1772 jl139090 { 2311 2214 av145390 if (&plat_get_mem_sid) { 2312 2214 av145390 return (plat_get_mem_sid(unum, buf, buflen, lenp)); 2313 2214 av145390 } else { 2314 2214 av145390 return (ENOTSUP); 2315 2214 av145390 } 2316 1772 jl139090 } 2317 1772 jl139090 2318 1772 jl139090 /* ARGSUSED */ 2319 1772 jl139090 int 2320 1772 jl139090 cpu_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp) 2321 1772 jl139090 { 2322 2214 av145390 if (&plat_get_mem_addr) { 2323 2214 av145390 return (plat_get_mem_addr(unum, sid, offset, addrp)); 2324 2214 av145390 } else { 2325 2214 av145390 return (ENOTSUP); 2326 2214 av145390 } 2327 1772 jl139090 } 2328 1772 jl139090 2329 1772 jl139090 /* ARGSUSED */ 2330 1772 jl139090 int 2331 1772 jl139090 cpu_get_mem_offset(uint64_t flt_addr, uint64_t *offp) 2332 1772 jl139090 { 2333 2214 av145390 if (&plat_get_mem_offset) { 2334 2214 av145390 return (plat_get_mem_offset(flt_addr, offp)); 2335 2214 av145390 } else { 2336 2214 av145390 return (ENOTSUP); 2337 2214 av145390 } 2338 1772 jl139090 } 2339 1772 jl139090 2340 1772 jl139090 /*ARGSUSED*/ 2341 1772 jl139090 void 2342 1772 jl139090 itlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag) 2343 1772 jl139090 { ASSERT(0); } 2344 1772 jl139090 2345 1772 jl139090 /*ARGSUSED*/ 2346 1772 jl139090 void 2347 1772 jl139090 dtlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag) 2348 1772 jl139090 { ASSERT(0); } 2349 2203 hyw 2350 2203 hyw /*ARGSUSED*/ 2351 2203 hyw void 2352 2203 hyw read_ecc_data(struct async_flt *aflt, short verbose, short ce_err) 2353 2203 hyw { ASSERT(0); } 2354 2203 hyw 2355 2203 hyw /*ARGSUSED*/ 2356 2203 hyw int 2357 2203 hyw ce_scrub_xdiag_recirc(struct async_flt *aflt, errorq_t *eqp, 2358 2203 hyw errorq_elem_t *eqep, size_t afltoffset) 2359 2203 hyw { 2360 2203 hyw ASSERT(0); 2361 2203 hyw return (0); 2362 2203 hyw } 2363 2203 hyw 2364 2203 hyw /*ARGSUSED*/ 2365 2203 hyw char * 2366 2203 hyw flt_to_error_type(struct async_flt *aflt) 2367 2203 hyw { 2368 2203 hyw ASSERT(0); 2369 2203 hyw return (NULL); 2370 2203 hyw } 2371 5394 jimand 2372 5394 jimand #define PROM_SPARC64VII_MODE_PROPNAME "SPARC64-VII-mode" 2373 5394 jimand 2374 5394 jimand /* 2375 5394 jimand * Check for existence of OPL OBP property that indicates 2376 5394 jimand * SPARC64-VII support. By default, only enable Jupiter 2377 5394 jimand * features if the property is present. It will be 2378 5394 jimand * present in all-Jupiter domains by OBP if the domain has 2379 5394 jimand * been selected by the user on the system controller to 2380 5394 jimand * run in Jupiter mode. Basically, this OBP property must 2381 5394 jimand * be present to turn on the cpu_alljupiter flag. 2382 5394 jimand */ 2383 5394 jimand static int 2384 5394 jimand prom_SPARC64VII_support_enabled(void) 2385 5394 jimand { 2386 5394 jimand int val; 2387 5394 jimand 2388 5394 jimand return ((prom_getprop(prom_rootnode(), PROM_SPARC64VII_MODE_PROPNAME, 2389 5394 jimand (caddr_t)&val) == 0) ? 1 : 0); 2390 5394 jimand } 2391 5584 jimand 2392 5584 jimand #define PROM_KCTX_PRESERVED_PROPNAME "context0-page-size-preserved" 2393 5584 jimand 2394 5584 jimand /* 2395 5584 jimand * Check for existence of OPL OBP property that indicates support for 2396 5584 jimand * preserving Solaris kernel page sizes when entering OBP. We need to 2397 5584 jimand * check the prom tree since the ddi tree is not yet built when the 2398 5584 jimand * platform startup sequence is called. 2399 5584 jimand */ 2400 5584 jimand static int 2401 5584 jimand plat_prom_preserve_kctx_is_supported(void) 2402 5584 jimand { 2403 5584 jimand pnode_t pnode; 2404 5584 jimand int val; 2405 5584 jimand 2406 5584 jimand /* 2407 5584 jimand * Check for existence of context0-page-size-preserved property 2408 5584 jimand * in virtual-memory prom node. 2409 5584 jimand */ 2410 5584 jimand pnode = (pnode_t)prom_getphandle(prom_mmu_ihandle()); 2411 5584 jimand return ((prom_getprop(pnode, PROM_KCTX_PRESERVED_PROPNAME, 2412 5584 jimand (caddr_t)&val) == 0) ? 1 : 0); 2413 5584 jimand } 2414
Indexes created Sat Nov 28 14:09:03 UTC 2009
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