1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1995-1998 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 #ifndef _SYS_SCSI_ADAPTERS_ESPVAR_H 28 #define _SYS_SCSI_ADAPTERS_ESPVAR_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #include <sys/note.h> 33 34 /* 35 * Emulex ESP (Enhanced Scsi Processor) Definitions, 36 * Software && Hardware. 37 */ 38 39 /* 40 * General SCSI includes 41 */ 42 #include <sys/scsi/scsi.h> 43 44 45 /* 46 * Include hardware definitions for the ESP generation chips. 47 */ 48 #include <sys/scsi/adapters/espreg.h> 49 #include <sys/scsi/adapters/espcmd.h> 50 51 #ifdef __cplusplus 52 extern "C" { 53 #endif 54 55 /* 56 * Compile options 57 */ 58 #if DEBUG 59 60 #define ESPDEBUG /* turn on debugging code */ 61 #define ESPTEST 62 63 #ifdef ESPTEST 64 #define ESP_TEST_PARITY /* turn on parity test code */ 65 #define ESP_TEST_ABORT /* turn on abort test code */ 66 #define ESP_TEST_RESET /* turn on device reset code */ 67 #define ESP_TEST_TIMEOUT /* turn on timeout test code */ 68 #define ESP_TEST_BUS_RESET /* turn on bus reset code */ 69 #define ESP_TEST_RQSENSE /* test rqsense with renegotiation */ 70 #define ESP_NEW_HW_DEBUG /* turn on debug code for new h/w */ 71 #define ESP_TEST_UNTAGGED /* turn on untagged/tagged mix test */ 72 #endif /* ESPTEST */ 73 74 #endif /* DEBUG */ 75 76 /* 77 * Software Definitions 78 */ 79 80 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000) 81 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */ 82 #define ESP_MUTEX (&esp->e_mutex) 83 #define ESP_INIT_SOFT_STATE 5 84 85 /* 86 * Data Structure for this Host Adapter. 87 */ 88 89 90 /* 91 * Tag lookup array structure 92 */ 93 struct t_slots { 94 short e_dups; 95 uchar_t e_tags; 96 int e_timeout; 97 int e_timebase; 98 struct esp_cmd *t_slot[NTAGS]; 99 }; 100 101 102 /* 103 * this structure collects all info about a callback thread; this 104 * thread may be shared between a number of esps 105 */ 106 struct callback_info { 107 struct callback_info *c_next; 108 struct esp_cmd *c_qf; 109 struct esp_cmd *c_qb; 110 kmutex_t c_mutex; 111 kcondvar_t c_cv; 112 kthread_t *c_thread; 113 uint_t c_qlen; 114 uchar_t c_id; 115 uchar_t c_cb_now_qlen; 116 uchar_t c_spawned; 117 uchar_t c_count; 118 uchar_t c_signal_needed; 119 uchar_t c_exit; /* terminate this thread */ 120 kcondvar_t c_cvd; /* terminate cv */ 121 }; 122 123 _NOTE(MUTEX_PROTECTS_DATA(callback_info::c_mutex, callback_info)) 124 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", callback_info::c_next)) 125 126 #define N_SLOTS (NTARGETS*NLUNS_PER_TARGET) 127 128 129 /* 130 * HBA interface macros 131 */ 132 #define SDEV2TRAN(sd) ((sd)->sd_address.a_hba_tran) 133 #define SDEV2ADDR(sd) (&((sd)->sd_address)) 134 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran) 135 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 136 137 #define TRAN2ESP(tran) ((struct esp *)(tran)->tran_hba_private) 138 #define SDEV2ESP(sd) (TRAN2ESP(SDEV2TRAN(sd))) 139 #define PKT2ESP(pkt) (TRAN2ESP(PKT2TRAN(pkt))) 140 #define ADDR2ESP(ap) (TRAN2ESP(ADDR2TRAN(ap))) 141 142 143 /* 144 * Configuration information for this host adapter 145 */ 146 struct esp { 147 148 /* 149 * Transport structure for this instance of the hba 150 */ 151 scsi_hba_tran_t *e_tran; 152 153 /* 154 * dev_info_t reference 155 */ 156 dev_info_t *e_dev; 157 158 /* 159 * mutex 160 */ 161 kmutex_t e_mutex; 162 163 /* 164 * Interrupt block cookie 165 */ 166 ddi_iblock_cookie_t e_iblock; 167 168 /* 169 * Next in a linked list of host adapters 170 */ 171 172 struct esp *e_next; 173 174 /* 175 * Type byte for this host adapter (53C90, 53C90A, ESP-236), 176 * part unique id code, and rev of the dma engine 177 */ 178 uchar_t e_type; 179 uchar_t e_idcode; 180 uchar_t e_dma_rev; 181 182 /* 183 * value for configuration register 1. 184 * Also contains Initiator Id. 185 */ 186 uchar_t e_espconf; 187 188 /* 189 * value for configuration register 2 (ESP100A) 190 */ 191 uchar_t e_espconf2; 192 193 /* 194 * value for configuration register 3 (ESP236/FAS) 195 */ 196 uchar_t e_espconf3[NTARGETS]; 197 uchar_t e_espconf3_fastscsi; 198 uchar_t e_espconf3_last; 199 200 /* 201 * clock conversion register value for this host adapter. 202 * clock cycle value * 1000 for this host adapter, 203 * to retain 5 significant digits. 204 */ 205 uchar_t e_clock_conv; 206 ushort_t e_clock_cycle; 207 208 /* 209 * selection timeout register value 210 */ 211 uchar_t e_stval; 212 213 /* 214 * State of the host adapter 215 */ 216 uchar_t e_sdtr; /* Count of sync data negotiation messages: */ 217 /* zeroed for every selection attempt, */ 218 /* every reconnection, and every disconnect */ 219 /* interrupt. Each SYNCHRONOUS DATA TRANSFER */ 220 /* message, both coming from the target, and */ 221 /* sent to the target, causes this tag to be */ 222 /* incremented. This allows the received */ 223 /* message handling to determine whether */ 224 /* a received SYNCHRONOUS DATA TRANSFER */ 225 /* message is in response to one that we */ 226 /* sent. */ 227 uchar_t e_stat; /* soft copy of status register */ 228 uchar_t e_intr; /* soft copy of interrupt register */ 229 uchar_t e_step; /* soft copy of step register */ 230 uchar_t e_abort; /* indicates that an abort message went out */ 231 uchar_t e_reset; /* indicates that a device reset message */ 232 /* went out */ 233 uchar_t e_last_cmd; /* last cmd sent to esp chip */ 234 235 ushort_t e_state; /* state of the driver */ 236 ushort_t e_laststate; /* last state of the driver */ 237 uchar_t e_suspended; /* true if driver is suspended */ 238 239 /* 240 * Message handling: enough space is reserved for the expected length 241 * of all messages we could either send or receive. 242 * 243 * For sending, we expect to send only SYNCHRONOUS extended messages 244 * (5 bytes). We keep a history of the last message sent, and in order 245 * to control which message to send, an output message length is set 246 * to indicate whether and how much of the message area is to be used 247 * in sending a message. If a target shifts to message out phase 248 * unexpectedly, the default action will be to send a MSG_NOP message. 249 * 250 * After the successful transmission of a message, the initial message 251 * byte is moved to the e_last_msgout area for tracking what was the 252 * last message sent. 253 */ 254 255 #define OMSGSIZE 12 256 uchar_t e_cur_msgout[OMSGSIZE]; 257 uchar_t e_last_msgout; 258 uchar_t e_omsglen; 259 260 261 /* 262 * We expect, at, most, to receive a maximum of 7 bytes 263 * of an incoming extended message (MODIFY DATA POINTER), 264 * and thus reserve enough space for that. 265 */ 266 #define IMSGSIZE 8 267 uchar_t e_imsgarea[IMSGSIZE]; 268 269 /* 270 * These are used to index how far we've 271 * gone in receiving incoming messages. 272 */ 273 uchar_t e_imsglen; 274 uchar_t e_imsgindex; 275 276 /* 277 * Saved last msgin. 278 */ 279 uchar_t e_last_msgin; 280 281 /* 282 * Target information 283 * Synchronous SCSI Information, 284 * Disconnect/reconnect capabilities 285 * Noise Susceptibility 286 */ 287 uchar_t e_offset[NTARGETS]; /* synchronous offset */ 288 uchar_t e_period[NTARGETS]; /* synchronous periods */ 289 uchar_t e_neg_period[NTARGETS]; /* synchronous periods (negotiated) */ 290 uchar_t e_backoff[NTARGETS]; /* synchronous period compensation */ 291 /* 0: no backoff 1: do backoff now */ 292 /* 2: no backoff now but goto async */ 293 /* on next failure */ 294 uchar_t e_default_period[NTARGETS]; /* default sync period */ 295 uchar_t e_req_ack_delay; /* req ack delay in offset reg */ 296 uchar_t e_offset_last; /* save last offset value */ 297 uchar_t e_period_last; /* save last period value */ 298 299 /* 300 * This uchar_t is a bit map for targets 301 * whose SYNC capabilities are known. 302 */ 303 uchar_t e_sync_known; 304 305 /* 306 * This uchar_t is a bit map for targets 307 * for disabling sync on request from 308 * target driver setcap 309 */ 310 uchar_t e_force_async; 311 312 /* 313 * This uchar_t is a bit map for targets who 314 * don't appear to be able to disconnect. 315 */ 316 uchar_t e_nodisc; 317 318 /* 319 * This uchar_t is a bit map for targets 320 * who seem to be susceptible to noise. 321 */ 322 uchar_t e_weak; 323 324 /* 325 * This byte is a bit map for targets who don't appear 326 * to be able to support tagged commands. 327 */ 328 uchar_t e_notag; 329 330 /* 331 * scsi options, scsi_tag_age_limit per esp 332 */ 333 uchar_t e_target_scsi_options_defined; 334 335 uchar_t e_polled_intr; /* current interrupt was polled. */ 336 337 /* 338 * This ushort_t is a bit map for targets who need to have 339 * their properties update deferred. 340 */ 341 ushort_t e_props_update; 342 343 int e_scsi_options; 344 int e_target_scsi_options[NTARGETS]; 345 int e_scsi_tag_age_limit; 346 347 /* 348 * various chip and system idiosyncracies 349 */ 350 uint_t e_options; 351 352 /* 353 * scsi reset delay per esp 354 */ 355 uint_t e_scsi_reset_delay; 356 357 /* 358 * Scratch Buffer, allocated out of iopbmap for commands 359 * The same size as the ESP's fifo. 360 */ 361 volatile uchar_t *e_cmdarea; 362 363 /* 364 * shadow copy of dmaga_csr to avoid unnecessary I/O reads which are 365 * expensive 366 */ 367 uint32_t e_dmaga_csr; 368 369 /* 370 * Scratch Buffer DMA cookie 371 */ 372 ddi_dma_cookie_t e_dmacookie; 373 ddi_dma_handle_t e_dmahandle; 374 375 /* 376 * dma attrs for esp 377 */ 378 ddi_dma_attr_t *e_dma_attr; 379 380 /* 381 * Instrumentation 382 */ 383 short e_ncmds; /* number of commands stored here at present */ 384 short e_ndisc; /* number of disconnected cmds at present */ 385 386 /* 387 * Hardware pointers 388 * 389 * Pointer to mapped in ESP registers 390 */ 391 volatile struct espreg *e_reg; 392 393 /* 394 * Pointer to mapped in DMA Gate Array registers 395 */ 396 397 volatile struct dmaga *e_dma; 398 399 /* 400 * last and current state, queues 401 */ 402 uint32_t e_lastdma; /* last dma address */ 403 uint32_t e_lastcount; /* last dma count */ 404 uint32_t e_esc_read_count; /* read count for cmdarea */ 405 uchar_t e_dslot; /* delta to next slot */ 406 short e_last_slot; /* last active target/lun */ 407 short e_cur_slot; /* current active target/lun */ 408 short e_next_slot; /* round robin scheduling */ 409 410 struct esp_cmd *e_slots[N_SLOTS]; 411 412 struct esp_cmd *e_readyf[N_SLOTS]; 413 struct esp_cmd *e_readyb[N_SLOTS]; 414 415 struct t_slots *e_tagQ[N_SLOTS]; 416 417 /* 418 * if throttle >= 0 then 419 * continue submitting cmds 420 * if throttle == 0 then hold cmds 421 * if throttle < 0 then drain 422 */ 423 short e_throttle[N_SLOTS]; 424 short e_tcmds[N_SLOTS]; 425 426 /* 427 * if a device reset has been performed, a 428 * delay is required before accessing the target 429 * again; reset delays are in milli secs 430 * (assuming that reset watchdog runs every 431 * ESP_WATCH_RESET_DELAY_TICK milli secs; 432 * watchdog decrements the reset delay) 433 */ 434 int e_reset_delay[NTARGETS]; 435 436 struct esp_cmd *e_arq_pkt[N_SLOTS]; 437 struct scsi_extended_sense *e_rq_sense_data[N_SLOTS]; 438 struct esp_cmd *e_save_pkt[N_SLOTS]; 439 440 /* 441 * callback thread info for this esp; the thread may be shared 442 */ 443 uint_t e_callback_signal_needed; 444 struct callback_info *e_callback_info; 445 446 /* 447 * a queue for packets in case the esp mutex is locked 448 */ 449 kmutex_t e_startQ_mutex; 450 struct esp_cmd *e_startf; 451 struct esp_cmd *e_startb; 452 453 struct kmem_cache *e_kmem_cache; 454 455 /* 456 * list of reset notification requests 457 */ 458 struct scsi_reset_notify_entry *e_reset_notify_listf; 459 460 /* 461 * QFULL handling related timeouts and limits. 462 */ 463 timeout_id_t e_restart_cmd_timeid; 464 uchar_t e_qfull_retries[NTARGETS]; 465 ushort_t e_qfull_retry_interval[NTARGETS]; 466 467 /* 468 * data access handle for register mapping 469 */ 470 ddi_acc_handle_t e_regs_acc_handle; 471 /* 472 * data access handle for cmdarea 473 */ 474 ddi_acc_handle_t e_cmdarea_acc_handle; 475 476 /* 477 * state flags 478 */ 479 int e_flags; 480 /* 481 * Interrupt kstat 482 */ 483 struct kstat *e_intr_kstat; 484 485 #ifdef ESP_KSTATS 486 /* 487 * stats per slot 488 */ 489 struct kstat *e_slot_stats[N_SLOTS]; 490 491 /* 492 * scsi bus statistics 493 */ 494 struct kstat *e_scsi_bus_stats; 495 #endif 496 497 #define NPHASE 16 498 #ifdef ESPDEBUG 499 /* 500 * SCSI analyzer function data structures. 501 */ 502 int e_xfer; /* size of current transfer */ 503 short e_phase_index; /* next entry in table */ 504 struct scsi_phases { /* SCSI analyzer structure */ 505 short e_save_state; 506 short e_save_stat; 507 int e_val1, e_val2; 508 int e_reserved; 509 } e_phase[NPHASE]; 510 #endif /* ESPDEBUG */ 511 }; 512 513 _NOTE(MUTEX_PROTECTS_DATA(esp::e_mutex, esp)) 514 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", \ 515 esp::e_next esp::e_callback_info esp::e_state esp::e_nodisc)) 516 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", 517 esp::e_callback_signal_needed)) 518 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", 519 esp::e_dma esp::e_dma_attr esp::e_dma_rev)) 520 _NOTE(SCHEME_PROTECTS_DATA("stable data", 521 esp::e_target_scsi_options esp::e_scsi_options)) 522 _NOTE(SCHEME_PROTECTS_DATA("protected by kmem lock", esp::e_kmem_cache)) 523 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", 524 esp::e_notag esp::e_suspended esp::e_ndisc)) 525 _NOTE(SCHEME_PROTECTS_DATA("stable data", esp::e_dev esp::e_tran)) 526 _NOTE(MUTEX_PROTECTS_DATA(esp::e_startQ_mutex, esp::e_startf esp::e_startb)) 527 _NOTE(DATA_READABLE_WITHOUT_LOCK(esp::e_flags)) 528 529 /* 530 * e_req_ack_delay: 531 * the values for req/ack delay have been emperically determined; a value 532 * of 0x20 for 101 was found to be preferable but this caused "illegal 533 * cmd interrupt" when a xfer > 64K was broken up (we were still using 534 * the 16 bit counter) in data phase; after restarting the xfer, the esp 535 * immediately returned "illegal cmd" because it is not legal to give a 536 * cmd while ACK is left asserted; it is not known yet why ACK is left 537 * asserted if this delay is 0x20; anyway, emulex now recommends 0x50 538 * The sunergy macio chip has more problems than the c2 with the value 0x20. 539 */ 540 #define DEFAULT_REQ_ACK_DELAY_101 0x50 /* delay assert period by 1/2 cycle */ 541 #define DEFAULT_REQ_ACK_DELAY_236 0x10 /* delay assert period by 1/2 cycle */ 542 543 /* 544 * define for e_options 545 */ 546 #define ESP_OPT_SBUS_RERUNS 0x0001 /* ESC has rerun problem */ 547 #define ESP_OPT_FAS 0x0002 /* FAS type */ 548 #define ESP_OPT_DMA_OUT_TAG 0x0004 /* can dma out tags */ 549 #define ESP_OPT_MASK_OFF_STAT 0x0008 /* mask off status reserved bit */ 550 #define ESP_OPT_DIFFERENTIAL 0x0010 /* differential scsi */ 551 #define ESP_OPT_STACKED_CMDS 0x0020 /* use stacked cmd for MSG_ACPT */ 552 #define ESP_OPT_ACCEPT_STEP567 0x0040 /* step register may report 5,6,7 */ 553 /* instead of 4 */ 554 #define ESP_OPT_SLOW_FIFO_FLUSH 0x0080 /* wait for fifo empty after flush */ 555 556 /* 557 * define for e_flags 558 */ 559 #define ESP_FLG_NOTIMEOUTS 0x0001 /* disallow timeout rescheduling */ 560 561 #define ESP_CAN_SCHED ((esp->e_flags & ESP_FLG_NOTIMEOUTS) == 0) 562 563 #ifdef ESPDEBUG 564 /* 565 * Log state and phase history of activity 566 */ 567 #define LOG_STATE(esp, arg0, arg1, arg2, arg3) { \ 568 esp->e_phase[esp->e_phase_index].e_save_state = arg0; \ 569 esp->e_phase[esp->e_phase_index].e_save_stat = arg1; \ 570 esp->e_phase[esp->e_phase_index].e_val1 = arg2; \ 571 esp->e_phase[esp->e_phase_index].e_val2 = arg3; \ 572 esp->e_phase[esp->e_phase_index].e_reserved = 0xbadfeed; \ 573 esp->e_phase_index = (++esp->e_phase_index) & (NPHASE-1); \ 574 }; 575 #else /* ESPDEBUG */ 576 #define LOG_STATE(esp, arg0, arg1, arg2, arg3) {}; 577 #endif /* ESPDEBUG */ 578 579 /* 580 * Representations of Driver states (stored in tags e_state && e_laststate). 581 */ 582 583 /* 584 * Totally idle. There may or may not disconnected commands still 585 * running on targets. 586 */ 587 588 #define STATE_FREE 0x00 589 590 /* 591 * Selecting States. These states represent a selection attempt 592 * for a target. 593 */ 594 595 #define STATE_SELECT_NORMAL 0x0100 596 #define STATE_SELECT_N_STOP 0x0200 597 #define STATE_SELECT_N_SENDMSG 0x0400 598 #define STATE_SYNC_ASKING 0x0800 599 #define STATE_SELECT_N_TAG 0x1000 600 #define STATE_SELECTING 0xFF00 /* Select mask */ 601 602 603 /* 604 * When the driver is neither idle nor selecting, it is in one of 605 * the information transfer phases. These states are not unique 606 * bit patterns- they are simple numbers used to mark transitions. 607 * They must start at 1 and proceed sequentially upwards and 608 * match the indexing of function vectors declared in the function 609 * esp_phasemanage(). 610 */ 611 612 #define STATE_ITPHASES 0x00FF /* Phase mask */ 613 614 /* 615 * These states cover finishing sending a command out (if it wasn't 616 * sent as a side-effect of selecting), or the case of starting 617 * a command that was linked to the previous command (i.e., no 618 * selection phase for this particular command as the target 619 * remained connected when the previous command completed). 620 */ 621 622 #define ACTS_CMD_START 0x01 623 #define ACTS_CMD_DONE 0x02 624 625 /* 626 * These states are the begin and end of sending out a message. 627 * The message to be sent is stored in the field e_msgout (see above). 628 */ 629 630 #define ACTS_MSG_OUT 0x03 631 #define ACTS_MSG_OUT_DONE 0x04 632 633 /* 634 * These states are the beginning, middle, and end of incoming messages. 635 * 636 */ 637 638 #define ACTS_MSG_IN 0x05 639 #define ACTS_MSG_IN_MORE 0x06 640 #define ACTS_MSG_IN_DONE 0x07 641 642 643 /* 644 * This state is reached when the target may be getting 645 * ready to clear the bus (disconnect or command complete). 646 */ 647 648 #define ACTS_CLEARING 0x08 649 650 651 /* 652 * These states elide the begin and end of a DATA phase 653 */ 654 655 #define ACTS_DATA 0x09 656 #define ACTS_DATA_DONE 0x0A 657 658 /* 659 * This state indicates that we were in status phase. We handle status 660 * phase by issuing the ESP command 'CMD_COMP_SEQ' which causes the 661 * ESP to read the status byte, and then to read a message in (presumably 662 * one of COMMAND COMPLETE, LINKED COMMAND COMPLETE or LINKED COMMAND 663 * COMPLETE WITH FLAG). 664 * 665 * This state is what is expected to follow after the issuance of the 666 * ESP command 'CMD_COMP_SEQ'. 667 */ 668 669 #define ACTS_C_CMPLT 0x0B 670 671 /* 672 * This state is used by the driver to indicate that it 673 * is in the middle of processing a reselection attempt. 674 */ 675 676 #define ACTS_RESEL 0x0C 677 678 /* 679 * Hiwater mark of vectored states 680 */ 681 682 #define ACTS_ENDVEC 0x0C 683 684 /* 685 * This state is used by the driver to indicate that it doesn't know 686 * what the next state is, and that it should look at the ESP's status 687 * register to find out what SCSI bus phase we are in in order to select 688 * the next state to transition to. 689 */ 690 691 #define ACTS_UNKNOWN 0x1A 692 693 /* 694 * This state is used by the driver to indicate that a self-inititated 695 * Bus reset is in progress. 696 */ 697 698 #define ACTS_RESET 0x1C 699 700 701 /* 702 * This state is used by the driver to indicate to itself that it is 703 * in the middle of aborting things. 704 */ 705 706 #define ACTS_ABORTING 0x1D 707 708 /* 709 * This state is used by the driver to indicate to itself that it is 710 * in the middle of spanning a target driver completion call. 711 */ 712 713 #define ACTS_SPANNING 0x1E 714 715 /* 716 * This state is used by the driver to just hold the state of 717 * the softc structure while it is either aborting or resetting 718 * everything. 719 */ 720 721 #define ACTS_FROZEN 0x1F 722 723 724 /* 725 * These additional states are only used by the scsi bus analyzer. 726 */ 727 #define ACTS_PREEMPTED 0x21 728 #define ACTS_PROXY 0x22 729 #define ACTS_SYNCHOUT 0x23 730 #define ACTS_CMD_LOST 0x24 731 #define ACTS_DATAOUT 0x25 732 #define ACTS_DATAIN 0x26 733 #define ACTS_STATUS 0x27 734 #define ACTS_DISCONNECT 0x28 735 #define ACTS_NOP 0x29 736 #define ACTS_REJECT 0x2A 737 #define ACTS_RESTOREDP 0x2B 738 #define ACTS_SAVEDP 0x2C 739 #define ACTS_BAD_RESEL 0x2D 740 #define ACTS_LOG 0x0F 741 #define ACTS_SELECT 0x2E /* ACTS_FREE too */ 742 #define ACTS_TAG 0x2F 743 #define ACTS_CMD 0x30 744 745 #define ACTS_NEW_STATE 0x40 746 #define ACTS_ESP_CMD 0x41 747 748 /* 749 * Interrupt dispatch actions 750 */ 751 752 #define ACTION_RETURN -1 /* return from interrupt */ 753 #define ACTION_FINSEL 0 /* finish selection */ 754 #define ACTION_RESEL 1 /* handle reselection */ 755 #define ACTION_PHASEMANAGE 2 /* manage phases */ 756 #define ACTION_FINISH 3 /* this command done */ 757 #define ACTION_FINRST 4 /* finish reset recovery */ 758 #define ACTION_SEARCH 5 /* search for new command to start */ 759 #define ACTION_ABORT_CURCMD 6 /* abort current command */ 760 #define ACTION_ABORT_ALLCMDS 7 /* abort all commands */ 761 #define ACTION_RESET 8 /* reset bus */ 762 #define ACTION_SELECT 9 /* handle selection */ 763 764 /* 765 * Proxy command definitions. 766 * 767 * At certain times, we need to run a proxy command for a target 768 * (if only to select a target and send a message). 769 * 770 * We use the tail end of the cdb that is internal to the esp_cmd 771 * structure to store the proxy code, the proxy data (e.g., the 772 * message to send). 773 * 774 * We also store a boolean result code in this area so that the 775 * user of a proxy command knows whether it succeeded. 776 */ 777 778 /* 779 * Offsets into the cmd_db[] array for proxy data 780 */ 781 782 #define ESP_PROXY_TYPE CDB_GROUP0 783 #define ESP_PROXY_RESULT ESP_PROXY_TYPE+1 784 #define ESP_PROXY_DATA ESP_PROXY_RESULT+1 785 786 /* 787 * Currently supported proxy types 788 */ 789 790 #define ESP_PROXY_SNDMSG 1 791 792 /* 793 * Reset actions 794 */ 795 796 #define ESP_RESET_ESP 0x1 /* reset ESP chip */ 797 #define ESP_RESET_DMA 0x2 /* reset DMA gate array */ 798 #define ESP_RESET_BRESET 0x4 /* reset SCSI bus */ 799 #define ESP_RESET_SCSIBUS (ESP_RESET_BRESET) 800 #define ESP_RESET_SOFTC 0x10 /* reset SOFTC structure */ 801 802 #define ESP_RESET_HW (ESP_RESET_ESP|ESP_RESET_DMA|ESP_RESET_SCSIBUS) 803 #define ESP_RESET_ALL (ESP_RESET_HW|ESP_RESET_SOFTC) 804 805 #define ESP_RESET_MSG 0x20 806 807 /* 808 * Debugging macros and defines 809 */ 810 811 #ifdef ESPDEBUG 812 813 #define INFORMATIVE (espdebug) 814 #define DEBUGGING (espdebug > 1) 815 816 #define EPRINTF(str) if (espdebug > 1) eprintf(esp, str) 817 #define EPRINTF1(str, a) if (espdebug > 1) eprintf(esp, str, a) 818 #define EPRINTF2(str, a, b) if (espdebug > 1) eprintf(esp, str, a, b) 819 #define EPRINTF3(str, a, b, c) if (espdebug > 1) eprintf(esp, str, a, b, c) 820 #define EPRINTF4(str, a, b, c, d) \ 821 if (espdebug > 1) eprintf(esp, str, a, b, c, d) 822 #define EPRINTF5(str, a, b, c, d, e) \ 823 if (espdebug > 1) eprintf(esp, str, a, b, c, d, e) 824 #define EPRINTF6(str, a, b, c, d, e, f) \ 825 if (espdebug > 1) eprintf(esp, str, a, b, c, d, e, f) 826 827 #define IPRINTF(str) if (espdebug) eprintf(esp, str) 828 #define IPRINTF1(str, a) if (espdebug) eprintf(esp, str, a) 829 #define IPRINTF2(str, a, b) if (espdebug) eprintf(esp, str, a, b) 830 #define IPRINTF3(str, a, b, c) if (espdebug) eprintf(esp, str, a, b, c) 831 #define IPRINTF4(str, a, b, c, d) \ 832 if (espdebug) eprintf(esp, str, a, b, c, d) 833 #define IPRINTF5(str, a, b, c, d, e) \ 834 if (espdebug) eprintf(esp, str, a, b, c, d, e) 835 #define IPRINTF6(str, a, b, c, d, e, f) \ 836 if (espdebug) eprintf(esp, str, a, b, c, d, e, f) 837 838 #else /* ESPDEBUG */ 839 840 #define EPRINTF(str) 841 #define EPRINTF1(str, a) 842 #define EPRINTF2(str, a, b) 843 #define EPRINTF3(str, a, b, c) 844 #define EPRINTF4(str, a, b, c, d) 845 #define EPRINTF5(str, a, b, c, d, e) 846 #define EPRINTF6(str, a, b, c, d, e, f) 847 #define IPRINTF(str) 848 #define IPRINTF1(str, a) 849 #define IPRINTF2(str, a, b) 850 #define IPRINTF3(str, a, b, c) 851 #define IPRINTF4(str, a, b, c, d) 852 #define IPRINTF5(str, a, b, c, d, e) 853 #define IPRINTF6(str, a, b, c, d, e, f) 854 855 #endif /* ESPDEBUG */ 856 857 /* 858 * Shorthand macros and defines 859 */ 860 861 /* 862 * Short hand defines 863 */ 864 865 #define SAME_CMD 0 866 #define INT_CMD 1 867 #define NEW_CMD 2 868 869 870 #define CLEAR_THROTTLE 512 871 #define HOLD_THROTTLE 0 872 #define DRAIN_THROTTLE -1 873 #define QFULL_THROTTLE -2 874 875 #define PAD_LIMIT 1025 876 877 #define NODISC(tgt) (esp->e_nodisc & (1<<(tgt))) 878 #define NOTAG(tgt) (esp->e_notag & (1<<(tgt))) 879 #define TAGGED(tgt) ((esp->e_notag & (1<<(tgt))) == 0) 880 #define SYNC_KNOWN(tgt) (esp->e_sync_known & (1<<(tgt))) 881 #define CURRENT_CMD(esp) ((esp)->e_slots[(esp)->e_cur_slot]) 882 883 #define SLOT(sp) ((short)(Tgt((sp)) * NLUNS_PER_TARGET|\ 884 (Lun((sp))))) 885 #define NEXTSLOT(slot, d) ((slot)+(d)) & ((N_SLOTS)-1) 886 #define FIFO_CNT(ep) ((ep)->esp_fifo_flag & 0x1f) 887 #define MY_ID(esp) ((esp)->e_espconf & ESP_CONF_BUSID) 888 #define INTPENDING(esp) ((esp)->e_dma->dmaga_csr&DMAGA_INT_MASK) 889 890 #define Tgt(sp) ((sp)->cmd_pkt.pkt_address.a_target) 891 #define Lun(sp) ((sp)->cmd_pkt.pkt_address.a_lun) 892 893 #ifdef ESP_KSTATS 894 #define IOSP(slot) (KSTAT_IO_PTR(esp->e_slot_stats[slot])) 895 #define IOSP_SCSI_BUS (KSTAT_IO_PTR(esp->e_scsi_bus_stats)) 896 897 #define ESP_KSTAT_SCSI_BUS(esp) \ 898 if (esp_do_bus_kstats) { \ 899 if (esp->e_laststate == STATE_FREE && \ 900 esp->e_state != STATE_FREE) { \ 901 if (esp->e_scsi_bus_stats) { \ 902 kstat_runq_enter(IOSP_SCSI_BUS); \ 903 } \ 904 } else if (esp->e_laststate != STATE_FREE && \ 905 esp->e_state == STATE_FREE) { \ 906 if (esp->e_scsi_bus_stats) { \ 907 kstat_runq_exit(IOSP_SCSI_BUS); \ 908 } \ 909 } \ 910 } 911 912 #define New_state(esp, state)\ 913 (esp)->e_laststate = (esp)->e_state, (esp)->e_state = (state); \ 914 ESP_KSTAT_SCSI_BUS(esp) 915 #else 916 #define New_state(esp, state)\ 917 (esp)->e_laststate = (esp)->e_state, (esp)->e_state = (state) 918 #endif 919 920 #define ESP_KSTAT_INTR(esp) KSTAT_INTR_PTR(esp->e_intr_kstat)->\ 921 intrs[KSTAT_INTR_HARD]++ 922 923 #define Esp_cmd(esp, cmd)\ 924 (esp)->e_reg->esp_cmd = (cmd), (esp)->e_last_cmd = (cmd) 925 926 #define ESP_PREEMPT(esp) \ 927 New_state((esp), STATE_FREE); (esp)->e_last_slot = (esp)->e_cur_slot, \ 928 (esp)->e_cur_slot = UNDEFINED 929 930 #define CNUM (ddi_get_instance(esp->e_dev)) 931 #define TRUE 1 932 #define FALSE 0 933 #define UNDEFINED -1 934 #define INVALID_MSG 0x7f 935 936 937 #define ESP_DMAGA_REV(esp) (esp)->e_dma_rev 938 939 /* 940 * Some manifest miscellaneous constants 941 */ 942 943 #define MEG (1000 * 1000) 944 #define FIVE_MEG (5 * MEG) 945 #define TEN_MEG (10 * MEG) 946 #define TWENTY_MEG (20 * MEG) 947 #define TWENTYFIVE_MEG (25 * MEG) 948 #define FORTY_MEG (40 * MEG) 949 #define ESP_FREQ_SLOP (25000) 950 951 /* 952 * DMA macros; we use a shadow copy of the dmaga_csr to save unnecessary 953 * reads 954 */ 955 #define ESP_DMA_WRITE(esp, count, base) { \ 956 register volatile struct espreg *ep = esp->e_reg; \ 957 register volatile struct dmaga *dmar = esp->e_dma; \ 958 SET_ESP_COUNT(ep, count); \ 959 esp->e_dmaga_csr |= DMAGA_WRITE | DMAGA_ENDVMA; \ 960 dmar->dmaga_csr = esp->e_dmaga_csr; \ 961 if (ESP_DMAGA_REV(esp) == ESC1_REV1) { \ 962 SET_DMAESC_COUNT(dmar, count); \ 963 } \ 964 dmar->dmaga_addr = esp->e_lastdma = base; \ 965 } 966 967 #define ESP_DMA_READ(esp, count, base) { \ 968 register volatile struct espreg *ep = esp->e_reg; \ 969 register volatile struct dmaga *dmar = esp->e_dma; \ 970 SET_ESP_COUNT(ep, count); \ 971 esp->e_dmaga_csr |= \ 972 (esp->e_dmaga_csr & ~DMAGA_WRITE) | DMAGA_ENDVMA; \ 973 dmar->dmaga_csr = esp->e_dmaga_csr; \ 974 dmar->dmaga_addr = esp->e_lastdma = base; \ 975 } 976 977 #define ESP_SET_ESC_READ_COUNT(esp, count, base) { \ 978 if ((esp->e_options & ESP_OPT_SBUS_RERUNS) && \ 979 (((base + count) & (MMU_PAGESIZE-1)) != 0)) { \ 980 register uint_t addr1 = (uint_t)base; \ 981 register uint_t addr2 = (uint_t) \ 982 (base + count + MMU_PAGESIZE) & (~(MMU_PAGESIZE-1)); \ 983 register uint_t spec_count = (uint_t)(addr2 - addr1); \ 984 SET_DMAESC_COUNT(esp->e_dma, spec_count); \ 985 } else \ 986 SET_DMAESC_COUNT(esp->e_dma, count); \ 987 } 988 989 990 /* 991 * For DMA gate arrays, the PACKCNT field of the DMA 992 * CSR register indicates how many bytes are still 993 * latched up and need to be drained to memory. 994 * 995 * For the DMA+ CSR, the PACKCNT field will either 996 * be zero or non-zero, indicating a empty/non-empty 997 * D_CACHE. The DRAIN bit has no effect. 998 * 999 * DON'T flush the dma if there is a dma request pending; this could 1000 * cause an abandonned rerun read which would hang the xbox 1001 */ 1002 #define DMA_DRAIN_TIMEOUT (200*100) 1003 1004 #define ESP_FLUSH_DMA(esp) \ 1005 if (esp->e_dmaga_csr & DMAGA_REQPEND) { \ 1006 while (esp->e_dma->dmaga_csr & DMAGA_REQPEND); \ 1007 } \ 1008 esp->e_dmaga_csr |= DMAGA_FLUSH; \ 1009 esp->e_dmaga_csr &= \ 1010 ~(DMAGA_ENDVMA | DMAGA_WRITE | DMAGA_ENATC); \ 1011 esp->e_dma->dmaga_csr = esp->e_dmaga_csr; \ 1012 esp->e_dmaga_csr &= ~DMAGA_FLUSH; \ 1013 1014 #define ESP_DRAIN_DMA(esp) { \ 1015 int i = 0; \ 1016 register volatile struct dmaga *dmap = esp->e_dma; \ 1017 if (DMAGA_NPACKED(dmap)) { \ 1018 if ((ESP_DMAGA_REV(esp) != ESC1_REV1) && \ 1019 (ESP_DMAGA_REV(esp) != DMA_REV3)) { \ 1020 esp->e_dmaga_csr |= DMAGA_DRAIN; \ 1021 dmap->dmaga_csr = esp->e_dmaga_csr; \ 1022 esp->e_dmaga_csr &= ~DMAGA_DRAIN; \ 1023 } \ 1024 EPRINTF("draining dma\n"); \ 1025 for (i = 0; i < DMA_DRAIN_TIMEOUT; i++) { \ 1026 drv_usecwait(1); \ 1027 if (DMAGA_NPACKED(dmap) == 0) \ 1028 break; \ 1029 } \ 1030 } \ 1031 if ((i >= DMA_DRAIN_TIMEOUT) && (DMAGA_NPACKED(dmap))) { \ 1032 esplog(esp, CE_WARN, "dma did not drain\n"); \ 1033 return (ACTION_RESET); \ 1034 } \ 1035 ESP_FLUSH_DMA(esp); \ 1036 } 1037 1038 #define esp_chip_disconnect(esp, sp) \ 1039 { \ 1040 if (esp->e_ndisc) \ 1041 Esp_cmd(esp, CMD_EN_RESEL); \ 1042 if (esp->e_cur_slot != UNDEFINED && sp) { \ 1043 if ((sp->cmd_pkt.pkt_flags & FLAG_NOPARITY) && \ 1044 (esp->e_target_scsi_options[Tgt(sp)] & \ 1045 SCSI_OPTIONS_PARITY)) { \ 1046 esp->e_reg->esp_conf = esp->e_espconf; \ 1047 } \ 1048 } \ 1049 esp->e_sdtr = 0; \ 1050 } 1051 1052 /* 1053 * this macro is called without mutex held; there is a race but 1054 * it is on the safe side 1055 */ 1056 #define ESP_WAKEUP_CALLBACK_THREAD(esp) \ 1057 { \ 1058 register struct callback_info *cb_info = \ 1059 esp->e_callback_info; \ 1060 if (esp->e_callback_signal_needed) { \ 1061 esp->e_callback_signal_needed = 0; \ 1062 esp_wakeup_callback_thread(cb_info); \ 1063 } \ 1064 } 1065 1066 1067 #define ESP_CHECK_STARTQ_AND_ESP_MUTEX_EXIT(esp) \ 1068 mutex_enter(&esp->e_startQ_mutex); \ 1069 if (esp->e_startf) { \ 1070 esp_empty_startQ(esp); \ 1071 } \ 1072 mutex_exit(ESP_MUTEX); \ 1073 mutex_exit(&esp->e_startQ_mutex); 1074 1075 /* 1076 * flags for _esp_start 1077 */ 1078 #define NO_TRAN_BUSY 0 /* _esp_start should not bounce these pkts */ 1079 #define TRAN_BUSY_OK 1 /* _esp_start may bounce these pkts */ 1080 1081 /* 1082 * reset delay tick 1083 */ 1084 #define ESP_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */ 1085 1086 /* 1087 * 2 ms timeout on receiving tag on reconnect 1088 */ 1089 #define RECONNECT_TAG_RCV_TIMEOUT 2000 /* allow up to 2 ms */ 1090 1091 /* 1092 * Default is to have 10 retries on receiving QFULL status and 1093 * each retry to be after 100 ms. 1094 */ 1095 #define QFULL_RETRIES 10 1096 #define QFULL_RETRY_INTERVAL 100 1097 1098 /* 1099 * auto request sense 1100 */ 1101 #define RQ_MAKECOM_COMMON(pktp, flag, cmd) \ 1102 (pktp)->pkt_flags = (flag), \ 1103 ((union scsi_cdb *)(pktp)->pkt_cdbp)->scc_cmd = (cmd), \ 1104 ((union scsi_cdb *)(pktp)->pkt_cdbp)->scc_lun = \ 1105 (pktp)->pkt_address.a_lun 1106 1107 #define RQ_MAKECOM_G0(pktp, flag, cmd, addr, cnt) \ 1108 RQ_MAKECOM_COMMON((pktp), (flag), (cmd)), \ 1109 FORMG0ADDR(((union scsi_cdb *)(pktp)->pkt_cdbp), (addr)), \ 1110 FORMG0COUNT(((union scsi_cdb *)(pktp)->pkt_cdbp), (cnt)) 1111 1112 1113 /* 1114 * packet completion 1115 */ 1116 #define MARK_PKT(sp, reason, stat)\ 1117 if (sp->cmd_pkt.pkt_reason == CMD_CMPLT) {\ 1118 sp->cmd_pkt.pkt_reason = reason; \ 1119 } \ 1120 sp->cmd_pkt.pkt_statistics |= stat; 1121 1122 1123 #define COMPLETE_PKT(sp, reason, stat) \ 1124 MARK_PKT(sp, reason, stat); \ 1125 esp_call_pkt_comp(esp, sp) 1126 1127 #define NEW_TIMEOUT 1 1128 1129 #ifdef __cplusplus 1130 } 1131 #endif 1132 1133 #endif /* _SYS_SCSI_ADAPTERS_ESPVAR_H */ 1134
Indexes created Thu Nov 26 20:23:21 UTC 2009
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