1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 28 /* 29 * Source code for the bidirectional parallel port 30 * driver for the Zebra SBus card, and the parallel 31 * port in the DMA2P and MACHIO. 32 * 33 * For any questions/problems, contact deborah@eng. 34 */ 35 36 /* #includes below */ 37 #include <sys/types.h> 38 #include <sys/param.h> 39 #include <sys/errno.h> 40 #include <sys/conf.h> 41 #include <sys/uio.h> 42 #include <sys/debug.h> 43 #include <sys/modctl.h> 44 #include <sys/kmem.h> 45 #include <sys/cmn_err.h> 46 #include <sys/dmaga.h> 47 #include <sys/open.h> 48 #include <sys/stat.h> 49 #include <sys/ddi.h> 50 #include <sys/sunddi.h> 51 #include <sys/file.h> 52 #include <sys/kstat.h> 53 54 #include <sys/bpp_io.h> 55 #include <sys/bpp_reg.h> 56 #include <sys/bpp_var.h> 57 58 /* structure definitions below */ 59 60 static struct bpp_transfer_parms bpp_default_transfer_parms = { 61 BPP_ACK_BUSY_HS, /* read_handshake */ 62 1000, /* read_setup_time - 1 us */ 63 1000, /* read_strobe_width - 1 us */ 64 60, /* read_timeout - 1 minute */ 65 BPP_ACK_HS, /* write_handshake */ 66 1000, /* write_setup_time - 1 us */ 67 1000, /* write_strobe_width - 1 us */ 68 60, /* write_timeout - 1 minute */ 69 }; 70 71 static struct bpp_pins bpp_default_pins = { 72 0, /* output pins */ 73 0, /* input pins */ 74 }; 75 76 static struct bpp_error_status bpp_default_error_stat = { 77 0, /* no timeout */ 78 0, /* no bus error */ 79 0, /* no pin status set */ 80 }; 81 82 83 /* static variable declarations below */ 84 85 /* array of pointers to unit structs */ 86 static int sbus_clock = 0; /* sbus clock freq prop in MHz */ 87 static int sbus_cycle = 0; /* sbus clock prop period in nsec */ 88 static void *bpp_state_head; /* opaque handle top of state structs */ 89 90 91 static ddi_dma_attr_t bpp_dma_attr = { 92 DMA_ATTR_V0, /* version */ 93 0x00000000ull, /* dlim_addr_lo */ 94 0xffffffffull, /* dlim_addr_hi */ 95 ((1<<24)-1), /* inclusive upper bound of */ 96 /* bpp dma address counter */ 97 /* lower 24 bits are a counter, */ 98 /* upper 8 bits are registered */ 99 1, /* DMA address alignment */ 100 DEFAULT_BURSTSIZE, /* encoded burstsizes */ 101 0x1, /* min effective DMA size */ 102 0x7fffffff, /* max DMA xfer size */ 103 0x00ffffff, /* segment boundary */ 104 1, /* s/g list length */ 105 1, /* granularity of device */ 106 0 /* DMA flags */ 107 }; 108 109 static ddi_device_acc_attr_t bpp_acc_attr = { 110 DDI_DEVICE_ATTR_V0, 111 DDI_STRUCTURE_BE_ACC, 112 DDI_STRICTORDER_ACC 113 }; 114 115 #define KIOIP KSTAT_INTR_PTR(bpp_p->intrstats) 116 117 #define getsoftc(unit) \ 118 ((struct bpp_unit *)ddi_get_soft_state(bpp_state_head, (unit))) 119 120 #ifndef BPP_DEBUG 121 #define BPP_DEBUG 0 122 #endif /* BPP_DEBUG */ 123 124 125 #if BPP_DEBUG > 0 126 static int bpp_debug = BPP_DEBUG; 127 #define BPP_PRINT(level, args) _STMT(if (bpp_debug >= (level)) \ 128 cmn_err args; /* space */) 129 #else 130 #define BPP_PRINT(level, args) /* nothing */ 131 #endif /* BPP_DEBUG */ 132 133 /* private procedure declarations below */ 134 /* Autoconfig Declarations */ 135 static int bpp_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 136 void *arg, void **result); 137 static int bpp_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 138 139 /* Driver function Declarations */ 140 static int bpp_open(dev_t *dev, int openflags, int otyp, cred_t *credp); 141 static int bpp_close(dev_t dev, int openflags, int otyp, cred_t *credp); 142 static int bpp_read(dev_t dev, struct uio *uiop, cred_t *credp); 143 static int bpp_write(dev_t dev, struct uio *uiop, cred_t *credp); 144 static int bpp_ioctl(dev_t dev, int cmd, intptr_t arg, int flag, 145 cred_t *credp, int *rvalp); 146 static uint_t bpp_intr(); 147 static int bpp_strategy(register struct buf *bp); 148 static void bpp_minphys(struct buf *bp); 149 150 /* Utility Function Declarations */ 151 static int check_bpp_registers(int unit_no); 152 static void set_dss_dsw(int unit_no, int read_mode); 153 static ushort_t check_write_params(struct bpp_transfer_parms *parms_p, 154 int unit, int flags); 155 static ushort_t check_read_params(struct bpp_transfer_parms *parms_p, 156 uint_t unit, int flags); 157 static ushort_t check_read_pins(struct bpp_pins *pins_p, 158 int flags, uint_t unit, register enum handshake_t handshake); 159 static ushort_t check_write_pins(struct bpp_pins *pins_p, 160 int flags, uint_t unit, register enum handshake_t handshake); 161 static void read_outpins(int unit_no, int flags, 162 register enum handshake_t handshake); 163 static void check_for_active_pins(int unit_no); 164 static int bpp_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 165 static void bpp_transfer_timeout(void *unit_no_arg); 166 static void bpp_transfer_failed(int unit_no); 167 168 /* 169 * The bpp_cb_ops struct enables the kernel to find the 170 * rest of the driver entry points. 171 */ 172 static struct cb_ops bpp_cb_ops = { 173 bpp_open, /* driver open routine */ 174 bpp_close, /* driver close routine */ 175 nulldev, /* driver strategy routine - block devs only */ 176 nodev, /* driver print routine */ 177 nodev, /* driver dump routine */ 178 bpp_read, /* driver read routine */ 179 bpp_write, /* driver write routine */ 180 bpp_ioctl, /* driver ioctl routine */ 181 nodev, /* driver devmap routine */ 182 nulldev, /* driver mmap routine */ 183 nulldev, /* driver segmap routine */ 184 nochpoll, /* driver chpoll routine */ 185 ddi_prop_op, /* driver prop_op routine */ 186 0, /* driver cb_str - STREAMS only */ 187 D_NEW | D_MP /* driver compatibility flag */ 188 }; 189 190 /* 191 * The bpp_ops struct enables the kernel to find the 192 * bpp loadable module routines. 193 */ 194 static struct dev_ops bpp_ops = 195 { 196 DEVO_REV, /* revision number */ 197 0, /* device reference count */ 198 bpp_getinfo, /* driver get_dev_info routine */ 199 nulldev, /* confirm device ID */ 200 nulldev, /* device probe for non-self-id */ 201 bpp_attach, /* attach routine of driver */ 202 bpp_detach, /* device detach routine */ 203 nodev, /* device reset routine */ 204 &bpp_cb_ops, /* device operations struct */ 205 (struct bus_ops *)0, /* bus operations */ 206 NULL, /* power */ 207 ddi_quiesce_not_supported, /* devo_quiesce */ 208 }; 209 210 211 /* 212 * The bpp_drv structure provides the linkage between the vd driver 213 * (for loadable drivers) and the dev_ops structure for this driver 214 * (bpp_ops). 215 */ 216 static struct modldrv modldrv = { 217 &mod_driverops, /* type of module - driver */ 218 "pport driver: bpp", /* name of module */ 219 &bpp_ops /* *Drv_dev_ops */ 220 }; 221 222 static struct modlinkage modlinkage = { 223 MODREV_1, 224 &modldrv, 225 NULL 226 }; 227 228 /* Autoconfig Support Functions */ 229 230 /* 231 * bpp_attach() 232 * 233 * Allocate unit structures. 234 * Map the bpp device registers into kernel virtual memory. 235 * Add the bpp driver to the level 2 interrupt chain. 236 * Initialize the bpp portion of the zebra card. 237 * Turn on the interrupts. 238 */ 239 static int 240 bpp_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 241 { 242 int unit_no; /* attaching unit's number */ 243 int sbus_frequency; /* sbus clock frequency (in cycles) */ 244 int burst_sizes; /* sbus burst sizes, encoded */ 245 char name[16]; /* name to pass to minor node */ 246 247 register struct bpp_unit *bpp_p; /* will point to this */ 248 /* unit's state struct */ 249 volatile struct bpp_regs *bpp_regs_p; 250 251 252 unit_no = ddi_get_instance(dip); 253 BPP_PRINT(2, (CE_CONT, "Entering bpp_attach, unit %d\n", unit_no)); 254 255 switch (cmd) { 256 case DDI_ATTACH: 257 break; 258 259 case DDI_RESUME: 260 if ((bpp_p = ddi_get_driver_private(dip)) == NULL) 261 return (DDI_FAILURE); 262 mutex_enter(&bpp_p->bpp_mutex); 263 if (!(bpp_p->flags & BPP_SUSPENDED)) { 264 mutex_exit(&bpp_p->bpp_mutex); 265 return (DDI_FAILURE); 266 } 267 bpp_p->flags &= ~BPP_SUSPENDED; 268 mutex_exit(&bpp_p->bpp_mutex); 269 bpp_regs_p = bpp_p->bpp_regs_p; 270 goto initialise; 271 272 default: 273 return (DDI_FAILURE); 274 } 275 276 /* Make sure we're not in a slave-only slot */ 277 if (ddi_slaveonly(dip) == DDI_SUCCESS) { 278 cmn_err(CE_NOTE, 279 "bpp unit %d: NOT used - SBus slot is slave only.", 280 unit_no); 281 return (DDI_FAILURE); 282 } 283 284 285 /* 286 * Allocate a unit structure for this unit. 287 * Each bpp_unit struct is allocated as zeroed memory. 288 * Store away its address for future use. 289 */ 290 BPP_PRINT(5, (CE_CONT, "Allocating unit struct for unit %d.\n", 291 unit_no)); 292 if (ddi_soft_state_zalloc(bpp_state_head, unit_no) != 0) 293 return (DDI_FAILURE); 294 /* assign a pointer to this unit's state struct */ 295 bpp_p = getsoftc(unit_no); 296 ddi_set_driver_private(dip, bpp_p); 297 298 /* 299 * Initialize the unit structures. The unit structure for 300 * each unit is initialized when bpp_attach is called for that unit. 301 */ 302 303 /* 304 * For devices that issue interrupts, the driver must install 305 * itself on the interrupt chain for each level that the hardware 306 * can interrupt at. 307 * This must be done before expecting to receive any interrupts. 308 */ 309 if (ddi_add_intr(dip, 0, &bpp_p->bpp_block_cookie, 310 (ddi_idevice_cookie_t *)0, bpp_intr, 311 (caddr_t)(uintptr_t)unit_no) != DDI_SUCCESS) { 312 cmn_err(CE_NOTE, 313 "bpp_attach unit %d: cannot add interrupt!", unit_no); 314 ddi_soft_state_free(bpp_state_head, unit_no); 315 return (DDI_FAILURE); 316 } 317 BPP_PRINT(5, (CE_CONT, "Installed bpp_poll: unit %d\n", unit_no)); 318 319 cv_init(&bpp_p->wr_cv, NULL, CV_DRIVER, NULL); 320 321 /* 322 * Initialize the bpp mutex. 323 * This mutex is used for all operations outside of attach. 324 */ 325 mutex_init(&bpp_p->bpp_mutex, NULL, MUTEX_DRIVER, 326 (void *)bpp_p->bpp_block_cookie); 327 328 /* 329 * Save the devinfo pointer for this unit. 330 * Initialize the interupt cookie. 331 * Inhibit opens on this unit until initialization is successful. 332 */ 333 bpp_p->dip = dip; 334 335 /* 336 * Initialize the transfer parameters structure for this unit. 337 */ 338 bpp_p->transfer_parms = bpp_default_transfer_parms; 339 340 /* 341 * Initialize the control pins structure for this unit. 342 */ 343 bpp_p->pins = bpp_default_pins; 344 345 /* 346 * Initialize the error status structure for this unit. 347 * Initialize the timeout status byte for this unit. 348 * Initialize the timeout idents for this unit. 349 */ 350 bpp_p->error_stat = bpp_default_error_stat; 351 bpp_p->timeouts = NO_TIMEOUTS; 352 BPP_PRINT(5, (CE_CONT, "Timeout block is 0x%x.\n", bpp_p->timeouts)); 353 bpp_p->bpp_transfer_timeout_ident = 0; 354 bpp_p->bpp_fakeout_timeout_ident = 0; 355 356 /* 357 * Check that the clock-frequency property is in 358 * a sensible range. If it isn't, the math used when setting 359 * the transfer parameters strobe and width times will 360 * fail. Flag the future problem here rather than in the ioctl. 361 */ 362 363 sbus_frequency = ddi_getprop(DDI_DEV_T_ANY, dip, 0, 364 "clock-frequency", 1000000); 365 BPP_PRINT(5, (CE_CONT, 366 "clock-frequency prop is: %d\n", sbus_frequency)); 367 sbus_clock = sbus_frequency/1000000; 368 if (sbus_clock >= 10 && sbus_clock <= 25) { 369 BPP_PRINT(5, (CE_CONT, "SBus clock is %d MHz.\n", sbus_clock)); 370 /* calculate clock period (in nsec) */ 371 sbus_cycle = (1000 / sbus_clock); 372 bpp_p->sbus_clock_cycle = sbus_cycle; 373 } else { 374 cmn_err(CE_NOTE, "SBus clock frequency out of range."); 375 ddi_remove_intr(bpp_p->dip, 0, bpp_p->bpp_block_cookie); 376 ddi_soft_state_free(bpp_state_head, unit_no); 377 return (DDI_FAILURE); 378 } 379 BPP_PRINT(5, (CE_CONT, "SBus Clock period is %d nsec.\n", 380 bpp_p->sbus_clock_cycle)); 381 382 383 /* 384 * Map in any device registers. The zebra parallel section 385 * has only one register area. 386 */ 387 /* 388 * Map the structure into kernel virtual space. 389 */ 390 if (ddi_regs_map_setup(dip, 0, (caddr_t *)&(bpp_p->bpp_regs_p), 391 0, sizeof (struct bpp_regs), 392 &bpp_acc_attr, &bpp_p->bpp_acc_handle) != DDI_SUCCESS) { 393 cmn_err(CE_NOTE, 394 "bpp_attach unit %d: regs_map_setup failed!", unit_no); 395 cv_destroy(&bpp_p->wr_cv); 396 mutex_destroy(&bpp_p->bpp_mutex); 397 ddi_remove_intr(bpp_p->dip, 0, bpp_p->bpp_block_cookie); 398 ddi_soft_state_free(bpp_state_head, unit_no); 399 return (DDI_FAILURE); 400 } 401 bpp_regs_p = bpp_p->bpp_regs_p; 402 403 if (check_bpp_registers(unit_no)) { /* registers don't seem right */ 404 cmn_err(CE_NOTE, 405 "bpp_attach unit %d: register check failed!", unit_no); 406 ddi_regs_map_free(&bpp_p->bpp_acc_handle); 407 cv_destroy(&bpp_p->wr_cv); 408 mutex_destroy(&bpp_p->bpp_mutex); 409 ddi_remove_intr(bpp_p->dip, 0, bpp_p->bpp_block_cookie); 410 ddi_soft_state_free(bpp_state_head, unit_no); 411 return (DDI_FAILURE); 412 } 413 414 if (ddi_dma_alloc_handle(dip, &bpp_dma_attr, DDI_DMA_DONTWAIT, NULL, 415 &bpp_p->bpp_dma_handle) != DDI_SUCCESS) { 416 cmn_err(CE_NOTE, 417 "bpp_attach unit %d: dma_alloc_handle failed!", 418 unit_no); 419 ddi_regs_map_free(&bpp_p->bpp_acc_handle); 420 cv_destroy(&bpp_p->wr_cv); 421 mutex_destroy(&bpp_p->bpp_mutex); 422 ddi_remove_intr(bpp_p->dip, 0, bpp_p->bpp_block_cookie); 423 ddi_soft_state_free(bpp_state_head, unit_no); 424 return (DDI_FAILURE); 425 } 426 427 /* The driver is now commited - all sanity checks done */ 428 429 (void) sprintf(name, "bpp%d", unit_no); 430 if (ddi_create_minor_node(dip, name, S_IFCHR, 431 unit_no, DDI_NT_PRINTER, NULL) == DDI_FAILURE) { 432 ddi_remove_minor_node(dip, NULL); 433 cmn_err(CE_NOTE, "ddi_create_minor_node failed for unit %d", 434 unit_no); 435 ddi_dma_free_handle(&bpp_p->bpp_dma_handle); 436 ddi_regs_map_free(&bpp_p->bpp_acc_handle); 437 cv_destroy(&bpp_p->wr_cv); 438 mutex_destroy(&bpp_p->bpp_mutex); 439 ddi_remove_intr(bpp_p->dip, 0, bpp_p->bpp_block_cookie); 440 ddi_soft_state_free(bpp_state_head, unit_no); 441 return (DDI_FAILURE); 442 } 443 444 ddi_report_dev(dip); 445 446 (void) sprintf(name, "bppc%d", unit_no); 447 bpp_p->intrstats = kstat_create("bpp", unit_no, name, "controller", 448 KSTAT_TYPE_INTR, 1, KSTAT_FLAG_PERSISTENT); 449 if (bpp_p->intrstats) { 450 kstat_install(bpp_p->intrstats); 451 } 452 453 initialise: 454 /* 455 * The burst-sizes property encodes which SBus burst sizes this 456 * cpu will support. Each binary digit represents a power of 457 * two. Thus 0x37 would indicate 1,2,4,16, and 32-byte bursts 458 * are supported. 459 * Use this info to program the P_BURST_SIZE bits of the 460 * P_CSR. 461 */ 462 burst_sizes = ddi_getprop(DDI_DEV_T_ANY, dip, 0, "burst-sizes", -1); 463 BPP_PRINT(5, (CE_CONT, 464 "^burst-sizes prop is: 0x%x\n", burst_sizes)); 465 466 /* 467 * Starting with the DMA2P, the bpp lives with a DMA controller 468 * which can support different burst sizes. Determine the 469 * SBus burst size and program the register. 470 * Be sure to always look for largest-possible burst-size first. 471 * On an HIOD (zebra card) there is no active register at that 472 * location. 473 */ 474 475 #if BPP_DEBUG 476 if ((bpp_regs_p->dma_csr & BPP_DEVICE_ID_MASK) == BPP_HIOD_DEVID) { 477 /* 478 * HIOD DMA engine only supports 4-word (default) bursts, no 479 * programmable register. 480 */ 481 BPP_PRINT(5, (CE_CONT, 482 "bpp_attach: devid field indicates HIOD bpp DMA\n")); 483 /* no register, so do nothing here */ 484 } else 485 #endif /* BPP_DEBUG */ 486 if ((bpp_regs_p->dma_csr & BPP_DEVICE_ID_MASK) == BPP_DMA2P_DEVID) { 487 BPP_PRINT(5, (CE_CONT, 488 "bpp_attach: devid field indicates DMA2P bpp DMA\n")); 489 if ((burst_sizes == 0xff) || 490 (!((burst_sizes & BURST16) || 491 (burst_sizes & BURST32)))) { 492 BPP_PRINT(5, (CE_CONT, 493 "bad burst-sizes 0x%x, setting to %x\n", 494 burst_sizes, BPP_BURST_DEFAULT)); 495 bpp_regs_p->dma_csr |= BPP_BURST_DEFAULT; 496 } else if (burst_sizes & BURST32) { /* largest possible */ 497 BPP_PRINT(5, (CE_CONT, 498 "Setting P_BURST_SIZE for 8-word bursts\n")); 499 bpp_regs_p->dma_csr |= BPP_BURST_8WORD; 500 } else if (burst_sizes & BURST16) { 501 BPP_PRINT(5, (CE_CONT, 502 "Setting P_BURST_SIZE for 4-word bursts\n")); 503 bpp_regs_p->dma_csr |= BPP_BURST_4WORD; 504 } 505 } else if ((bpp_regs_p->dma_csr & BPP_DEVICE_ID_MASK) != 506 BPP_HIOD_DEVID) { 507 BPP_PRINT(5, (CE_CONT, 508 "bpp_attach: undefined bpp DMA")); 509 BPP_PRINT(5, (CE_CONT, 510 "using 0x%x for bursts.\n", BPP_BURST_DEFAULT)); 511 bpp_regs_p->dma_csr |= BPP_BURST_DEFAULT; 512 } 513 514 /* 515 * Perform device initialization. 516 */ 517 518 bpp_regs_p->dma_csr |= BPP_RESET_BPP; 519 bpp_regs_p->dma_csr &= ~BPP_RESET_BPP; 520 bpp_regs_p->dma_csr |= BPP_TC_INTR_DISABLE; 521 522 /* 523 * Set up the polarities for the ERR, SLCT PE, and BUSY interrupts. 524 * Changing the polarities could cause a stray interrupt, 525 * so clear them here. 526 * These polarities are handshake dependent. 527 * This setup corresponds to the default handshakes. 528 */ 529 BPP_PRINT(5, (CE_CONT, "Before setting polarities, int_cntl = 0x%x\n", 530 bpp_regs_p->int_cntl)); 531 bpp_regs_p->int_cntl |= BPP_ERR_IRP; /* ERR rising edge */ 532 bpp_regs_p->int_cntl |= BPP_SLCT_IRP; /* SLCT rising edge */ 533 /* SLCT+ means off-line */ 534 bpp_regs_p->int_cntl &= ~BPP_PE_IRP; /* PE falling edge */ 535 bpp_regs_p->int_cntl |= BPP_BUSY_IRP; /* BUSY rising edge */ 536 /* clear any stray interrupts */ 537 bpp_regs_p->int_cntl |= BPP_ALL_IRQS; 538 BPP_PRINT(5, (CE_CONT, "After setting polarities, int_cntl = 0x%x\n", 539 bpp_regs_p->int_cntl)); 540 541 /* Turn on interrupts */ 542 bpp_p->bpp_regs_p->dma_csr |= BPP_INT_EN; 543 544 if (bpp_p->bpp_regs_p->op_config 545 & BPP_VERSATEC_INTERLOCK) { /* versatec connector absent */ 546 /* block versatec handshake modes */ 547 bpp_p->flags &= ~BPP_VERSATEC; 548 BPP_PRINT(5, (CE_CONT, "Versatec connector absent.\n")); 549 } else { 550 /* allow versatec handshake modes */ 551 bpp_p->flags |= BPP_VERSATEC; 552 BPP_PRINT(5, (CE_CONT, "Versatec connector present.\n")); 553 } 554 555 BPP_PRINT(2, (CE_CONT, "Leaving bpp_attach: unit %d\n", unit_no)); 556 557 BPP_PRINT(2, (CE_CONT, "ATTACH SUCCEEDED.\n")); 558 return (DDI_SUCCESS); 559 } 560 561 /* 562 * xx_getinfo is called from the framework to determine the devinfo pointer 563 * or instance number corresponding to a given dev_info_t. 564 */ 565 /*ARGSUSED*/ 566 static int 567 bpp_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 568 { 569 register int error; 570 register struct bpp_unit *bpp_p; 571 572 BPP_PRINT(2, (CE_CONT, "Entering bpp_getinfo, cmd %x\n", infocmd)); 573 574 switch (infocmd) { 575 case DDI_INFO_DEVT2DEVINFO: 576 if ((bpp_p = getsoftc((dev_t)arg)) == NULL) { 577 *result = NULL; 578 error = DDI_FAILURE; 579 } else { 580 mutex_enter(&bpp_p->bpp_mutex); 581 *result = bpp_p->dip; 582 mutex_exit(&bpp_p->bpp_mutex); 583 error = DDI_SUCCESS; 584 } 585 break; 586 case DDI_INFO_DEVT2INSTANCE: 587 *result = (void *)(uintptr_t)getminor((dev_t)arg); 588 error = DDI_SUCCESS; 589 break; 590 default: 591 error = DDI_FAILURE; 592 } 593 594 BPP_PRINT(2, (CE_CONT, "Leaving bpp_getinfo, result %x\n", error)); 595 return (error); 596 } 597 598 599 /* 600 * _init is called by the autoloading code when the special file is 601 * first opened, or by modload(). 602 */ 603 int 604 _init(void) 605 { 606 register int error; 607 if ((error = ddi_soft_state_init(&bpp_state_head, 608 sizeof (struct bpp_unit), 1)) != 0) { 609 return (error); 610 } 611 if ((error = mod_install(&modlinkage)) != 0) 612 ddi_soft_state_fini(&bpp_state_head); 613 return (error); 614 } 615 616 /* 617 * _info is called by modinfo(). 618 */ 619 int 620 _info(struct modinfo *modinfop) 621 { 622 return (mod_info(&modlinkage, modinfop)); 623 } 624 625 /* 626 * _fini is called by 627 * modunload() just before the driver is unloaded from system memory. 628 */ 629 int 630 _fini(void) 631 { 632 int status; 633 634 if ((status = mod_remove(&modlinkage)) != 0) 635 return (status); 636 ddi_soft_state_fini(&bpp_state_head); 637 return (status); 638 } 639 640 641 /* 642 * Turn off interrupts, remove registration of all interrupt vectors, 643 * and release all memory. 644 * This routine does the reverse of the attach routine. 645 * 646 */ 647 static int 648 bpp_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 649 { 650 register struct bpp_unit *bpp_p; /* will point to this */ 651 /* unit's state struct */ 652 volatile struct bpp_regs *bpp_regs_p; 653 int unit_no; 654 655 unit_no = ddi_get_instance(dip); 656 BPP_PRINT(2, (CE_CONT, "Entering bpp_detach, unit %d\n", unit_no)); 657 658 switch (cmd) { 659 case DDI_DETACH: 660 break; 661 662 case DDI_SUSPEND: 663 if ((bpp_p = ddi_get_driver_private(dip)) == NULL) 664 return (DDI_FAILURE); 665 mutex_enter(&bpp_p->bpp_mutex); 666 if (bpp_p->flags & BPP_SUSPENDED) { 667 mutex_exit(&bpp_p->bpp_mutex); 668 return (DDI_FAILURE); 669 } 670 bpp_p->flags |= BPP_SUSPENDED; 671 mutex_exit(&bpp_p->bpp_mutex); 672 /* XXX - Need to Wait for pending ops to finish */ 673 while (bpp_p->timeouts) { 674 } /* Yuck! */ 675 return (DDI_SUCCESS); 676 677 default: 678 BPP_PRINT(3, (CE_CONT, 679 "Invalid detach cmd 0x%x in bpp_detach\n", cmd)); 680 goto detach_failed; 681 } 682 683 bpp_p = getsoftc(unit_no); 684 bpp_regs_p = bpp_p->bpp_regs_p; 685 686 /* Turn off interrupts for this unit. */ 687 if (bpp_regs_p->dma_csr & BPP_ENABLE_DMA) { 688 /* was transferring */ 689 cmn_err(CE_NOTE, 690 "ERROR: bpp unload of unit %d while DMA active!", 691 unit_no); 692 /* turn off DMA and byte count */ 693 bpp_regs_p->dma_csr &= ~BPP_ENABLE_DMA; 694 bpp_regs_p->dma_csr &= ~BPP_ENABLE_BCNT; 695 /* Reset PP state machine */ 696 bpp_regs_p->op_config |= BPP_SRST; 697 bpp_regs_p->op_config &= ~BPP_SRST; 698 /* flush the cache */ 699 bpp_regs_p->dma_csr |= BPP_FLUSH; 700 } 701 /* 702 * Disable the TC interrupts. 703 * Mask the error interrupts too. 704 * These shouldn't be on if we weren't transferring 705 * at the time, but it's safest to just turn 706 * them off anyway. 707 */ 708 bpp_regs_p->dma_csr |= BPP_TC_INTR_DISABLE; 709 bpp_regs_p->int_cntl &= 710 ~(BPP_ERR_IRQ_EN | BPP_SLCT_IRQ_EN | BPP_PE_IRQ_EN); 711 bpp_p->bpp_regs_p->dma_csr &= ~BPP_INT_EN; 712 /* 713 * XXX This comment no longer applies to 5.x 714 * 715 * To be safer, I really should free the buf which 716 * was being used to do the transfer, and wait on 717 * a semaphore that tells me that bpp_read or 718 * bpp_write have returned the partial error. 719 */ 720 721 /* Remove the minor node created in attach */ 722 ddi_remove_minor_node(dip, NULL); 723 724 /* Free DMA handle */ 725 ddi_dma_free_handle(&bpp_p->bpp_dma_handle); 726 727 /* 728 * Unmap register area from kernel memory. 729 */ 730 dip = bpp_p->dip; 731 ddi_regs_map_free(&bpp_p->bpp_acc_handle); 732 733 /* 734 * Remove interrupt registry 735 */ 736 BPP_PRINT(5, (CE_CONT, "Removing bpp from interrupt chains.\n")); 737 ddi_remove_intr(bpp_p->dip, 0, bpp_p->bpp_block_cookie); 738 739 if (bpp_p->intrstats) { 740 kstat_delete(bpp_p->intrstats); 741 } 742 bpp_p->intrstats = NULL; 743 744 /* Destroy the per-unit cv and mutex. */ 745 cv_destroy(&bpp_p->wr_cv); 746 mutex_destroy(&bpp_p->bpp_mutex); 747 748 /* Free the memory allocated for this unit's state struct */ 749 ddi_soft_state_free(bpp_state_head, unit_no); 750 751 BPP_PRINT(2, (CE_CONT, "Leaving bpp_detach.\n")); 752 return (DDI_SUCCESS); 753 754 detach_failed: 755 BPP_PRINT(2, (CE_CONT, "DETACH FAILED.\n")); 756 return (DDI_FAILURE); 757 } 758 759 /* Normal Device Driver routines */ 760 761 /* 762 * Open the device. 763 */ 764 /*ARGSUSED*/ 765 static int 766 bpp_open(dev_t *dev, int openflags, int otyp, cred_t *credp) 767 { 768 int unit_no; 769 ushort_t retval = 0; /* return value (errno) for system call */ 770 register struct bpp_unit *bpp_p; /* will point to this */ 771 /* unit's state struct */ 772 773 unit_no = BPP_UNIT(dev); 774 bpp_p = getsoftc(unit_no); 775 BPP_PRINT(2, (CE_CONT, 776 "bpp%d: Entering bpp_open, flags %d.\n", unit_no, openflags)); 777 /* 778 * Assure that the device is being opened as a character device. 779 */ 780 if (otyp != OTYP_CHR) { 781 cmn_err(CE_NOTE, 782 "bpp%d attempted open as non-character device!", 783 unit_no); 784 retval = EINVAL; 785 goto out; 786 } 787 788 789 /* 790 * Check for allocation of unit structures. 791 */ 792 if (bpp_p == NULL) { 793 cmn_err(CE_NOTE, 794 "bpp%d unit pointer is NULL!", unit_no); 795 retval = ENXIO; /* attach failed ?? */ 796 goto out; 797 } 798 799 mutex_enter(&bpp_p->bpp_mutex); 800 /* 801 * Only allow a single open. If this device has 802 * already been opened, return an error. 803 */ 804 if (bpp_p->flags & BPP_ISOPEN) { 805 BPP_PRINT(1, (CE_CONT, "bpp%d already opened.\n", unit_no)); 806 retval = EBUSY; 807 mutex_exit(&bpp_p->bpp_mutex); 808 goto out; 809 } 810 811 812 /* 813 * Mark the bpp as opened. 814 */ 815 bpp_p->flags |= BPP_ISOPEN; 816 817 /* 818 * Initialize the transfer parameters structure 819 * and initialize the control pins structure 820 * for this unit. 821 */ 822 bpp_p->transfer_parms = bpp_default_transfer_parms; 823 bpp_p->pins = bpp_default_pins; 824 bpp_p->openflags = openflags; /* record the open mode */ 825 mutex_exit(&bpp_p->bpp_mutex); 826 827 out: 828 BPP_PRINT(2, (CE_CONT, "Leaving bpp_open, unit %d: errno %d.\n", 829 unit_no, retval)); 830 return (retval); 831 } 832 833 /* 834 * Close the device. 835 */ 836 /*ARGSUSED*/ 837 static int 838 bpp_close(dev_t dev, int openflags, int otyp, cred_t *credp) 839 { 840 841 int unit_no; 842 register struct bpp_unit *bpp_p; /* will point to this */ 843 /* unit's state struct */ 844 timeout_id_t tid = 0; 845 846 unit_no = BPP_UNIT(&dev); 847 bpp_p = getsoftc(unit_no); 848 BPP_PRINT(2, (CE_CONT, 849 "Entering bpp_close, unit number %d.\n", unit_no)); 850 851 BPP_PRINT(5, (CE_CONT, "In bpp_close, Timeout block is 0x%x.\n", 852 bpp_p->timeouts)); 853 mutex_enter(&bpp_p->bpp_mutex); 854 if (bpp_p->timeouts) { /* any timeouts pending? */ 855 BPP_PRINT(5, (CE_CONT, "Some timeouts still pending.\n")); 856 if (bpp_p->timeouts & TRANSFER_TIMEOUT) { 857 BPP_PRINT(5, (CE_CONT, "Clearing transfer timeout.\n")); 858 tid = bpp_p->bpp_transfer_timeout_ident; 859 bpp_p->bpp_transfer_timeout_ident = 0; 860 } 861 if (bpp_p->timeouts & FAKEOUT_TIMEOUT) { 862 cmn_err(CE_CONT, "BOGUS fakeout timeout.\n"); 863 } 864 } 865 866 bpp_p->timeouts = NO_TIMEOUTS; 867 BPP_PRINT(5, (CE_CONT, "At end of bpp_close, Timeout block is 0x%x.\n", 868 bpp_p->timeouts)); 869 870 /* 871 * Mark unit closed. 872 */ 873 bpp_p->flags &= ~BPP_ISOPEN; 874 mutex_exit(&bpp_p->bpp_mutex); 875 876 if (tid) 877 (void) untimeout(tid); 878 879 BPP_PRINT(2, (CE_CONT, "Leaving bpp_close, unit %d:\n", unit_no)); 880 return (0); 881 } 882 883 /* 884 * Read system call. 885 */ 886 /*ARGSUSED*/ 887 static int 888 bpp_read(dev_t dev, struct uio *uiop, cred_t *credp) 889 { 890 int unit_no; 891 ushort_t retval = 0; /* return value (errno) for system call */ 892 volatile struct bpp_regs *bpp_regs_p; 893 struct bpp_transfer_parms *bpp_transfer_parms_p; 894 static int scan_turnaround = 1000; /* time to allow the scanner */ 895 /* to change from data sink */ 896 /* to source */ 897 register struct bpp_unit *bpp_p; /* will point to this */ 898 /* unit's state struct */ 899 900 unit_no = BPP_UNIT(&dev); 901 bpp_p = getsoftc(unit_no); 902 BPP_PRINT(2, (CE_CONT, "Entering bpp_read, unit number %d.\n", 903 unit_no)); 904 905 mutex_enter(&bpp_p->bpp_mutex); 906 907 while (bpp_p->flags & BPP_BUSY) 908 if (!cv_wait_sig(&bpp_p->wr_cv, &bpp_p->bpp_mutex)) { 909 mutex_exit(&bpp_p->bpp_mutex); 910 return (EINTR); 911 } 912 913 bpp_p->flags |= BPP_BUSY; 914 915 bpp_regs_p = bpp_p->bpp_regs_p; 916 bpp_transfer_parms_p = &bpp_p->transfer_parms; 917 918 /* 919 * delay to allow for scanning write/read turnaround 920 */ 921 922 if (bpp_p->last_trans == write_trans) { 923 mutex_exit(&bpp_p->bpp_mutex); 924 drv_usecwait(scan_turnaround); 925 mutex_enter(&bpp_p->bpp_mutex); 926 } 927 928 /* 929 * Set the handshake bits 930 */ 931 932 /* 933 * make sure the memory clear operation is turned off 934 */ 935 bpp_regs_p->op_config &= ~BPP_EN_MEM_CLR; 936 937 switch (bpp_transfer_parms_p->read_handshake) { 938 case BPP_NO_HS: 939 BPP_PRINT(5, (CE_CONT, "BPP_NO_HS case\n")); 940 bpp_regs_p->op_config &= ~(BPP_ACK_OP | BPP_BUSY_OP); 941 bpp_regs_p->op_config |= (BPP_DS_BIDIR | BPP_BUSY_BIDIR); 942 break; 943 case BPP_ACK_HS: 944 BPP_PRINT(5, (CE_CONT, "BPP_ACK_HS case\n")); 945 bpp_regs_p->op_config &= ~BPP_BUSY_OP; 946 bpp_regs_p->op_config |= BPP_ACK_OP; 947 bpp_regs_p->op_config |= 948 (BPP_DS_BIDIR | BPP_ACK_BIDIR | BPP_BUSY_BIDIR); 949 break; 950 case BPP_BUSY_HS: 951 case BPP_HSCAN_HS: 952 BPP_PRINT(5, (CE_CONT, "BPP_BUSY_HS case\n")); 953 bpp_regs_p->op_config |= BPP_BUSY_OP; 954 bpp_regs_p->op_config &= ~BPP_ACK_OP; 955 bpp_regs_p->op_config |= (BPP_DS_BIDIR | BPP_BUSY_BIDIR); 956 break; 957 case BPP_ACK_BUSY_HS: 958 BPP_PRINT(5, (CE_CONT, "BPP_ACK_BUSY_HS case\n")); 959 bpp_regs_p->op_config |= (BPP_BUSY_OP | BPP_ACK_OP); 960 bpp_regs_p->op_config |= 961 (BPP_DS_BIDIR | BPP_ACK_BIDIR | BPP_BUSY_BIDIR); 962 break; 963 case BPP_XSCAN_HS: 964 /* 965 * reads with the Xerox use ACK handshake 966 * and unidirectional operation 967 */ 968 BPP_PRINT(5, (CE_CONT, "BPP_XSCAN_HS case\n")); 969 bpp_regs_p->op_config &= ~BPP_BUSY_OP; 970 bpp_regs_p->op_config |= BPP_ACK_OP; 971 bpp_regs_p->op_config &= 972 ~(BPP_DS_BIDIR | BPP_BUSY_BIDIR | BPP_ACK_BIDIR); 973 break; 974 case BPP_CLEAR_MEM: 975 BPP_PRINT(5, (CE_CONT, "BPP_CLEAR_MEM case\n")); 976 bpp_regs_p->op_config &= ~BPP_DMA_DATA; 977 bpp_regs_p->op_config |= BPP_EN_MEM_CLR; 978 break; 979 case BPP_SET_MEM: 980 BPP_PRINT(5, (CE_CONT, "BPP_SET_MEM case\n")); 981 bpp_regs_p->op_config |= BPP_DMA_DATA; 982 bpp_regs_p->op_config |= BPP_EN_MEM_CLR; 983 break; 984 } 985 /* 986 * The direction should not be marked until after the handshake 987 * bits have been set. 988 */ 989 bpp_regs_p->trans_cntl |= BPP_DIRECTION; 990 991 /* set the dss and dsw values */ 992 set_dss_dsw(unit_no, 1); 993 994 /* 995 * If we're opened for read/write, 996 * toggle the scan/print line for scanning 997 */ 998 if ((bpp_p->openflags & FREAD) && 999 (bpp_p->openflags & FWRITE)) { 1000 if (bpp_transfer_parms_p->read_handshake == BPP_HSCAN_HS) { 1001 /* The HP Scanjet uses AFX */ 1002 bpp_regs_p->out_pins |= BPP_AFX_PIN; 1003 } else { 1004 bpp_regs_p->out_pins |= BPP_SLCTIN_PIN; 1005 } 1006 } 1007 bpp_p->last_trans = read_trans; 1008 mutex_exit(&bpp_p->bpp_mutex); 1009 BPP_PRINT(5, (CE_CONT, "bpp_read, calling physio\n")); 1010 retval = physio(bpp_strategy, (struct buf *)0, dev, 1011 B_READ, bpp_minphys, uiop); 1012 1013 mutex_enter(&bpp_p->bpp_mutex); 1014 bpp_p->flags &= ~BPP_BUSY; 1015 cv_signal(&bpp_p->wr_cv); 1016 mutex_exit(&bpp_p->bpp_mutex); 1017 1018 BPP_PRINT(2, (CE_CONT, 1019 "Leaving bpp_read, unit %d: errno %d.\n", 1020 unit_no, retval)); 1021 return (retval); 1022 } 1023 1024 /* 1025 * Write system call. 1026 */ 1027 /*ARGSUSED*/ 1028 static int 1029 bpp_write(dev_t dev, struct uio *uiop, cred_t *credp) 1030 { 1031 int unit_no; 1032 ushort_t retval = 0; /* return value (errno) for system call */ 1033 register volatile struct bpp_regs *bpp_regs_p; 1034 register struct bpp_transfer_parms *bpp_transfer_parms_p; 1035 1036 register struct bpp_error_status *bpp_errorstat_p; /* error stat */ 1037 register struct bpp_unit *bpp_p; /* will point to this */ 1038 /* unit's state struct */ 1039 1040 unit_no = BPP_UNIT(&dev); 1041 BPP_PRINT(2, (CE_CONT, 1042 "Entering bpp_write, unit number %d.\n", unit_no)); 1043 1044 bpp_p = getsoftc(unit_no); 1045 1046 mutex_enter(&bpp_p->bpp_mutex); 1047 1048 while (bpp_p->flags & BPP_BUSY) 1049 if (!cv_wait_sig(&bpp_p->wr_cv, &bpp_p->bpp_mutex)) { 1050 mutex_exit(&bpp_p->bpp_mutex); 1051 return (EINTR); 1052 } 1053 1054 bpp_p->flags |= BPP_BUSY; 1055 1056 bpp_regs_p = bpp_p->bpp_regs_p; 1057 bpp_transfer_parms_p = &bpp_p->transfer_parms; 1058 bpp_errorstat_p = &bpp_p->error_stat; 1059 1060 /* clear any old error status */ 1061 *bpp_errorstat_p = bpp_default_error_stat; 1062 1063 /* 1064 * Set up the polarities for the ERR, SLCT PE, and BUSY interrupts. 1065 * Changing the polarities could cause a stray interrupt, 1066 * so clear them here. 1067 * These polarities are handshake dependent. 1068 * This setup corresponds to the default handshakes. 1069 */ 1070 BPP_PRINT(5, (CE_CONT, "Before setting polarities, int_cntl = 0x%x\n", 1071 bpp_regs_p->int_cntl)); 1072 bpp_regs_p->int_cntl |= BPP_ERR_IRP; /* ERR rising edge */ 1073 bpp_regs_p->int_cntl |= BPP_SLCT_IRP; /* SLCT rising edge */ 1074 /* SLCT+ is off-line */ 1075 bpp_regs_p->int_cntl &= ~BPP_PE_IRP; /* PE falling edge */ 1076 1077 bpp_regs_p->int_cntl |= (BPP_ERR_IRQ | BPP_SLCT_IRQ | BPP_PE_IRQ); 1078 1079 BPP_PRINT(5, (CE_CONT, "After setting polarities, int_cntl = 0x%x\n", 1080 bpp_regs_p->int_cntl)); 1081 1082 check_for_active_pins(unit_no); 1083 1084 /* 1085 * if any active pins were found, don't attempt the transfer, 1086 * unless we're in scanner mode (read-write), scanners use the PE line 1087 * to get the host's attention. 1088 */ 1089 if ((bpp_p->openflags & (FREAD | FWRITE)) == (FREAD | FWRITE)) { 1090 /* 1091 * Toggle the scan/print line for scanning 1092 */ 1093 if (bpp_transfer_parms_p->read_handshake == BPP_HSCAN_HS) { 1094 /* The HP Scanjet uses AFX */ 1095 bpp_regs_p->out_pins &= ~BPP_AFX_PIN; 1096 } else { 1097 bpp_regs_p->out_pins &= ~BPP_SLCTIN_PIN; 1098 } 1099 } else { 1100 if ((bpp_errorstat_p->pin_status & 1101 (BPP_ERR_ERR | BPP_SLCT_ERR | BPP_PE_ERR))) { 1102 /* printer error - no transfer allowed */ 1103 BPP_PRINT(5, (CE_CONT, 1104 "In bpp_write, pending error pin condition\n")); 1105 retval = ENXIO; 1106 mutex_exit(&bpp_p->bpp_mutex); 1107 goto out; 1108 } 1109 } 1110 1111 /* mark the transfer direction in the hardware */ 1112 bpp_regs_p->trans_cntl &= ~BPP_DIRECTION; 1113 1114 /* 1115 * make sure the memory clear operation is turned off 1116 */ 1117 bpp_regs_p->op_config &= ~BPP_EN_MEM_CLR; 1118 1119 /* 1120 * Set the handshake bits 1121 */ 1122 if (bpp_transfer_parms_p->write_handshake == BPP_NO_HS) { 1123 BPP_PRINT(5, (CE_CONT, "BPP_NO_HS case\n")); 1124 bpp_regs_p->op_config &= ~(BPP_ACK_OP | BPP_BUSY_OP); 1125 } else if (bpp_transfer_parms_p->write_handshake == BPP_ACK_HS) { 1126 BPP_PRINT(5, (CE_CONT, "BPP_ACK_HS case\n")); 1127 bpp_regs_p->op_config &= ~BPP_BUSY_OP; 1128 bpp_regs_p->op_config |= BPP_ACK_OP; 1129 } else if (bpp_transfer_parms_p->write_handshake == BPP_BUSY_HS) { 1130 BPP_PRINT(5, (CE_CONT, "BPP_BUSY_HS case\n")); 1131 bpp_regs_p->op_config |= BPP_BUSY_OP; 1132 bpp_regs_p->op_config &= ~BPP_ACK_OP; 1133 } 1134 1135 /* Make sure that ACK and BUSY are unidirectional */ 1136 bpp_regs_p->op_config &= ~(BPP_ACK_BIDIR | BPP_BUSY_BIDIR); 1137 1138 /* set the dss and dsw values */ 1139 set_dss_dsw(unit_no, 0); 1140 1141 bpp_p->last_trans = write_trans; 1142 mutex_exit(&bpp_p->bpp_mutex); 1143 1144 BPP_PRINT(5, (CE_CONT, "bpp_write, calling physio\n")); 1145 retval = physio(bpp_strategy, (struct buf *)0, dev, 1146 B_WRITE, bpp_minphys, uiop); 1147 1148 out: 1149 mutex_enter(&bpp_p->bpp_mutex); 1150 bpp_p->flags &= ~BPP_BUSY; 1151 cv_signal(&bpp_p->wr_cv); 1152 mutex_exit(&bpp_p->bpp_mutex); 1153 1154 BPP_PRINT(2, (CE_CONT, 1155 "Leaving bpp_write, unit %d: errno %d.\n", unit_no, retval)); 1156 return (retval); 1157 } 1158 1159 /* 1160 * Limit transfer size to the smaller of 1161 * - system minphys size 1162 * - 16 MB limit in HIOD address register 1163 */ 1164 static void 1165 bpp_minphys(struct buf *bp) 1166 { 1167 minphys(bp); 1168 if (bp->b_bcount > BPP_MAX_DMA) 1169 bp->b_bcount = BPP_MAX_DMA; 1170 } 1171 1172 /* 1173 * Check to see if any of the control pins are active. 1174 */ 1175 static void 1176 check_for_active_pins(int unit_no) 1177 { 1178 register struct bpp_unit *bpp_p; /* will point to this */ 1179 /* unit's state struct */ 1180 register volatile struct bpp_regs *bpp_regs_p; 1181 register struct bpp_error_status *bpp_errorstat_p; /* error stat */ 1182 1183 bpp_p = getsoftc(unit_no); 1184 bpp_regs_p = bpp_p->bpp_regs_p; 1185 bpp_errorstat_p = &bpp_p->error_stat; 1186 1187 BPP_PRINT(2, (CE_CONT, 1188 "Entering check_for_active_pins, unit number %d.\n", unit_no)); 1189 ASSERT(MUTEX_HELD(&bpp_p->bpp_mutex)); 1190 /* 1191 * Check that there are no pending ERR, SLCT or PE error 1192 * conditions. If there are, do not attempt the transfer. 1193 */ 1194 BPP_PRINT(5, (CE_CONT, "check_active_pins: in_pins = 0x%x\n", 1195 bpp_regs_p->in_pins)); 1196 BPP_PRINT(5, (CE_CONT, "check_active_pins: int_cntl = 0x%x\n", 1197 bpp_regs_p->int_cntl)); 1198 1199 if (((bpp_regs_p->in_pins & BPP_ERR_PIN) && 1200 (bpp_regs_p->int_cntl & BPP_ERR_IRP)) || 1201 ((~bpp_regs_p->in_pins & BPP_ERR_PIN)&& 1202 (~bpp_regs_p->int_cntl & BPP_ERR_IRP))) { /* ERR active */ 1203 BPP_PRINT(5, (CE_CONT, 1204 "In ck_active_pins, pending ERR condition\n")); 1205 bpp_errorstat_p->pin_status |= BPP_ERR_ERR; 1206 } 1207 1208 if (((bpp_regs_p->in_pins & BPP_SLCT_PIN) && 1209 (bpp_regs_p->int_cntl & BPP_SLCT_IRP)) || 1210 ((~bpp_regs_p->in_pins & BPP_SLCT_PIN)&& 1211 (~bpp_regs_p->int_cntl & BPP_SLCT_IRP))) { /* SLCT active */ 1212 BPP_PRINT(5, (CE_CONT, 1213 "In ck_active_pins, pending SLCT condition\n")); 1214 bpp_errorstat_p->pin_status |= BPP_SLCT_ERR; 1215 } 1216 1217 if (((bpp_regs_p->in_pins & BPP_PE_PIN) && 1218 (bpp_regs_p->int_cntl & BPP_PE_IRP)) || 1219 ((~bpp_regs_p->in_pins & BPP_PE_PIN)&& 1220 (~bpp_regs_p->int_cntl & BPP_PE_IRP))) { /* PE active */ 1221 BPP_PRINT(5, (CE_CONT, 1222 "In check_active_pins, pending PE condition\n")); 1223 bpp_errorstat_p->pin_status |= BPP_PE_ERR; 1224 } 1225 BPP_PRINT(2, (CE_CONT, 1226 "Leaving check_for_active_pins, unit number %d.\n", unit_no)); 1227 } 1228 1229 /* 1230 * Setup and start a transfer on the device. 1231 */ 1232 /*ARGSUSED*/ 1233 static int 1234 bpp_strategy(register struct buf *bp) 1235 { 1236 register struct bpp_unit *bpp_p; /* will point to this */ 1237 /* unit's state struct */ 1238 int unit_no; 1239 int timeout_value; /* read or write timeout in secs */ 1240 uint_t start_address; /* kernel virt. DVMA start address */ 1241 size_t size; /* size of DVMA transfer */ 1242 register struct bpp_transfer_parms *bpp_transfer_parms_p; 1243 register volatile struct bpp_regs *bpp_regs_p; 1244 int flags; /* flags to use for DMA mapping */ 1245 ddi_dma_cookie_t dma_cookie; 1246 uint_t dma_cookie_cnt; 1247 1248 1249 unit_no = BPP_UNIT(&(bp->b_edev)); 1250 BPP_PRINT(2, (CE_CONT, 1251 "bpp%d:Entering bpp_strategy: length 0x%x.\n", 1252 unit_no, bp->b_bcount)); 1253 1254 /* 1255 * Use the unit number to locate our data structures. 1256 */ 1257 bpp_p = getsoftc(unit_no); 1258 bpp_regs_p = bpp_p->bpp_regs_p; 1259 bpp_transfer_parms_p = &bpp_p->transfer_parms; 1260 1261 mutex_enter(&bpp_p->bpp_mutex); 1262 if (bpp_p->flags & BPP_SUSPENDED) { 1263 mutex_exit(&bpp_p->bpp_mutex); 1264 (void) ddi_dev_is_needed(bpp_p->dip, 0, 1); 1265 mutex_enter(&bpp_p->bpp_mutex); 1266 } 1267 bpp_p->bpp_buffer = bp; /* bpp_intr needs this */ 1268 1269 /* Clear the unit error status struct */ 1270 bpp_p->error_stat = bpp_default_error_stat; 1271 1272 /* Set DMA request flags based on struct buf flags */ 1273 if (bp->b_flags & B_READ) 1274 flags = DDI_DMA_READ; 1275 else if (bp->b_flags & B_WRITE) 1276 flags = DDI_DMA_WRITE; 1277 1278 BPP_PRINT(5, (CE_CONT, 1279 "Before dma_buf_bind, b_addr = 0x%p, b_bcount = 0x%x\n", 1280 (void *)bp->b_un.b_addr, bp->b_bcount)); 1281 /* 1282 * Get dvma bus resource, sleeping if necessary. 1283 */ 1284 if (ddi_dma_buf_bind_handle(bpp_p->bpp_dma_handle, bp, 1285 flags | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 0, 1286 &dma_cookie, &dma_cookie_cnt) != DDI_DMA_MAPPED) { 1287 cmn_err(CE_NOTE, 1288 "ERROR: bpp%d: dma_buf_bind failed mapping", 1289 unit_no); 1290 bioerror(bp, ENOMEM); 1291 bp->b_resid = bp->b_bcount; 1292 biodone(bp); 1293 return (0); 1294 } 1295 ASSERT(dma_cookie_cnt == 1); 1296 1297 BPP_PRINT(5, (CE_CONT, 1298 "After dma_buf_bind, b_addr = 0x%p, b_bcount = 0x%x\n", 1299 (void *)bp->b_un.b_addr, bp->b_bcount)); 1300 1301 start_address = dma_cookie.dmac_address; 1302 BPP_PRINT(5, (CE_CONT, 1303 "start_address = 0x%x\n", start_address)); 1304 1305 size = bp->b_bcount; 1306 1307 /* 1308 * Write the dma start address to the hardware. 1309 * Write the transfer byte count to the hardware. 1310 */ 1311 BPP_PRINT(5, (CE_CONT, "writing start_address 0x%x, size %d to regs\n", 1312 start_address, size)); 1313 1314 bpp_regs_p->dma_addr = start_address; 1315 bpp_regs_p->dma_bcnt = (uint_t)size; 1316 1317 BPP_PRINT(5, (CE_CONT, 1318 "bpp_strategy: Transfer %d bytes starting at 0x%x.\n", 1319 bpp_regs_p->dma_bcnt, bpp_regs_p->dma_addr)); 1320 BPP_PRINT(5, (CE_CONT, 1321 "before enabling interrupts, dma csr=0x%x, int_cntl=0x%x.\n", 1322 bpp_regs_p->dma_csr, bpp_regs_p->int_cntl)); 1323 1324 /* 1325 * Enable byte-counter during DVMA. 1326 * Enable TC interrupts so we will know when the DVMA is done. 1327 * Start the DVMA. 1328 * Enable the peripheral error interrupts. 1329 */ 1330 /* 1331 * Do not close critical section until timeouts have been 1332 * enabled, otherwise we might get an untimeout before 1333 * the timeout has been set! 1334 */ 1335 bpp_regs_p->dma_csr |= BPP_ENABLE_BCNT; 1336 bpp_regs_p->dma_csr &= ~BPP_TC_INTR_DISABLE; 1337 bpp_regs_p->dma_csr |= BPP_ENABLE_DMA; 1338 1339 if (bp->b_flags & B_READ) { 1340 BPP_PRINT(5, (CE_CONT, 1341 "bp->b_flags indicates READ mode\n")); 1342 timeout_value = bpp_transfer_parms_p->read_timeout; 1343 } else { 1344 BPP_PRINT(5, (CE_CONT, 1345 "bp->b_flags indicates WRITE mode\n")); 1346 if (!(bpp_p->openflags & FREAD && 1347 bpp_p->openflags & FWRITE)) { 1348 bpp_regs_p->int_cntl |= (BPP_ERR_IRQ_EN | 1349 BPP_SLCT_IRQ_EN | BPP_PE_IRQ_EN); 1350 } 1351 BPP_PRINT(5, (CE_CONT, 1352 "after enable error int. int cntl contains 0x%x.\n", 1353 bpp_regs_p->int_cntl)); 1354 timeout_value = bpp_transfer_parms_p->write_timeout; 1355 } 1356 1357 BPP_PRINT(5, (CE_CONT, 1358 "after enabling interrupts, dma csr = 0x%x, int_cntl = 0x%x.\n", 1359 bpp_regs_p->dma_csr, bpp_regs_p->int_cntl)); 1360 BPP_PRINT(5, (CE_CONT, 1361 "Setting timeout to call bpp_transfer_timeout in %d sec\n", 1362 timeout_value)); 1363 bpp_p->bpp_transfer_timeout_ident = 1364 timeout(bpp_transfer_timeout, (void *)(uintptr_t)unit_no, 1365 drv_usectohz(timeout_value * 1000000)); 1366 bpp_p->timeouts |= TRANSFER_TIMEOUT; 1367 BPP_PRINT(5, (CE_CONT, "In bpp_strategy, Timeout block is 0x%x.\n", 1368 bpp_p->timeouts)); 1369 mutex_exit(&bpp_p->bpp_mutex); 1370 1371 BPP_PRINT(2, (CE_CONT, "Leaving bpp_strategy.\n")); 1372 return (0); 1373 } 1374 1375 /* 1376 * Handle special control requests 1377 */ 1378 /*ARGSUSED*/ 1379 static int 1380 bpp_ioctl(dev_t dev, int cmd, intptr_t arg, int flag, 1381 cred_t *credp, int *rvalp) 1382 { 1383 int unit_no; 1384 ushort_t retval = 0; /* return value (errno) for system call */ 1385 ushort_t read_retval = 0; 1386 ushort_t write_retval = 0; 1387 struct bpp_unit *bpp_p; /* will point to this */ 1388 /* unit's state struct */ 1389 volatile struct bpp_regs *bpp_regs_p; 1390 struct bpp_transfer_parms *bpp_transfer_parms_p; 1391 struct bpp_transfer_parms temp_parms; 1392 struct bpp_error_status *bpp_errorstat_p; /* error stat */ 1393 struct bpp_pins *bpp_pins_p; /* error stat */ 1394 struct bpp_pins temp_pins; 1395 1396 register enum handshake_t write_handshake; 1397 register enum handshake_t read_handshake; 1398 1399 unit_no = BPP_UNIT(&dev); 1400 bpp_p = getsoftc(unit_no); 1401 bpp_regs_p = bpp_p->bpp_regs_p; 1402 bpp_transfer_parms_p = &bpp_p->transfer_parms; 1403 bpp_errorstat_p = &bpp_p->error_stat; 1404 bpp_pins_p = &bpp_p->pins; 1405 1406 write_handshake = bpp_transfer_parms_p->write_handshake; 1407 read_handshake = bpp_transfer_parms_p->read_handshake; 1408 1409 BPP_PRINT(2, (CE_CONT, 1410 "Entering bpp_ioctl, unit number %d.\n", unit_no)); 1411 mutex_enter(&bpp_p->bpp_mutex); 1412 if (bpp_p->flags & BPP_SUSPENDED) { 1413 mutex_exit(&bpp_p->bpp_mutex); 1414 (void) ddi_dev_is_needed(bpp_p->dip, 0, 1); 1415 mutex_enter(&bpp_p->bpp_mutex); 1416 } 1417 1418 switch (cmd) { 1419 case BPPIOC_SETPARMS: /* set transfer parameters */ 1420 BPP_PRINT(5, (CE_CONT, "BPPIOC_SETPARMS case.\n")); 1421 /* copy passed parms to temporary storage */ 1422 (void) copyin((caddr_t)arg, &temp_parms, sizeof (temp_parms)); 1423 bpp_transfer_parms_p = &temp_parms; 1424 if (flag & FREAD) { 1425 BPP_PRINT(5, (CE_CONT, 1426 "Checking read parameters.\n")); 1427 read_retval = check_read_params(bpp_transfer_parms_p, 1428 unit_no, flag); 1429 } 1430 if (flag & FWRITE) { 1431 BPP_PRINT(5, (CE_CONT, 1432 "Checking write parameters.\n")); 1433 write_retval = check_write_params(bpp_transfer_parms_p, 1434 unit_no, flag); 1435 } 1436 if (read_retval || write_retval) { 1437 retval = EINVAL; 1438 } else { /* valid parameters */ 1439 bpp_p->transfer_parms = temp_parms; 1440 } 1441 break; 1442 case BPPIOC_GETPARMS: /* get transfer parameters */ 1443 BPP_PRINT(5, (CE_CONT, "BPPIOC_GETPARMS case.\n")); 1444 (void) copyout(&bpp_p->transfer_parms, 1445 (caddr_t)arg, sizeof (struct bpp_transfer_parms)); 1446 retval = 0; 1447 break; 1448 case BPPIOC_SETOUTPINS: /* set output pins */ 1449 BPP_PRINT(5, (CE_CONT, "BPPIOC_SETOUTPINS case.\n")); 1450 /* copy passed parms to temporary storage */ 1451 (void) copyin((caddr_t)arg, &temp_pins, 1452 sizeof (struct bpp_pins)); 1453 bpp_pins_p = &temp_pins; 1454 if (flag & FREAD) { 1455 BPP_PRINT(5, (CE_CONT, 1456 "Checking read pins.\n")); 1457 read_retval = check_read_pins(bpp_pins_p, 1458 flag, unit_no, read_handshake); 1459 if (read_retval == 0) { /* valid pins */ 1460 bpp_p->pins = temp_pins; 1461 } 1462 } 1463 if (flag & FWRITE) { 1464 BPP_PRINT(5, (CE_CONT, 1465 "Checking write pins.\n")); 1466 write_retval = check_write_pins(bpp_pins_p, 1467 flag, unit_no, write_handshake); 1468 if (write_retval == 0) { /* valid pins */ 1469 bpp_p->pins = temp_pins; 1470 } 1471 } 1472 if (read_retval || write_retval) { 1473 retval = EINVAL; 1474 } else { /* All is well, write the registers */ 1475 bpp_regs_p->out_pins = 1476 bpp_p->pins.output_reg_pins; 1477 /* the previous line will not cstyle */ 1478 bpp_regs_p->in_pins = 1479 bpp_p->pins.input_reg_pins; 1480 } 1481 break; 1482 case BPPIOC_GETOUTPINS: /* get output pins */ 1483 BPP_PRINT(5, (CE_CONT, "BPPIOC_GETOUTPINS case.\n")); 1484 (void) copyout(&bpp_p->pins, 1485 (caddr_t)arg, sizeof (struct bpp_pins)); 1486 /* read the current pin state into the struct */ 1487 read_outpins(unit_no, flag, write_handshake); 1488 retval = 0; 1489 break; 1490 case BPPIOC_GETERR: /* get error block status */ 1491 BPP_PRINT(5, (CE_CONT, "BPPIOC_GETERR case.\n")); 1492 (void) copyout(&bpp_p->error_stat, 1493 (caddr_t)arg, sizeof (struct bpp_error_status)); 1494 retval = 0; 1495 break; 1496 case BPPIOC_TESTIO: /* test transfer readiness */ 1497 BPP_PRINT(5, (CE_CONT, "BPPIOC_TESTIO case.\n")); 1498 bpp_errorstat_p = &bpp_p->error_stat; 1499 retval = 0; 1500 /* clear any old error status */ 1501 *bpp_errorstat_p = bpp_default_error_stat; 1502 check_for_active_pins(unit_no); 1503 /* if any active pins were found, return -1 */ 1504 if (bpp_errorstat_p->pin_status & 1505 (BPP_ERR_ERR | BPP_SLCT_ERR | BPP_PE_ERR)) { 1506 BPP_PRINT(5, (CE_CONT, 1507 "In TESTIO, found error pin condition\n")); 1508 retval = EIO; 1509 } else 1510 retval = 0; 1511 break; 1512 /* TEST - request partial fake transfer */ 1513 case BPPIOC_SETBC: 1514 BPP_PRINT(5, (CE_CONT, "BPPIOC_SETBC case.\n")); 1515 retval = ENOTTY; 1516 break; 1517 /* TEST - get DMA_BCNT from last data transfer */ 1518 case BPPIOC_GETBC: 1519 BPP_PRINT(5, (CE_CONT, "BPPIOC_GETBC case.\n")); 1520 retval = ENOTTY; 1521 break; 1522 /* TEST - get contents of device registers */ 1523 case BPPIOC_GETREGS: 1524 BPP_PRINT(5, (CE_CONT, "BPPIOC_GETREGS case.\n")); 1525 retval = ENOTTY; 1526 break; 1527 /* TEST - set special fakeout error code to simulate errs */ 1528 case BPPIOC_SETERRCODE: 1529 BPP_PRINT(5, (CE_CONT, "BPPIOC_SETERRCODE case.\n")); 1530 retval = ENOTTY; 1531 break; 1532 /* TEST - get pointer to fakeout transferred data */ 1533 case BPPIOC_GETFAKEBUF: 1534 BPP_PRINT(5, (CE_CONT, "BPPIOC_GETFAKEBUF case.\n")); 1535 retval = ENOTTY; 1536 break; 1537 default: 1538 BPP_PRINT(1, (CE_CONT, "Error in bpp_ioctl switch!\n")); 1539 retval = ENOTTY; 1540 break; 1541 } 1542 1543 mutex_exit(&bpp_p->bpp_mutex); 1544 1545 BPP_PRINT(2, (CE_CONT, "Leaving bpp_ioctl, unit %d: errno %d.\n", 1546 unit_no, retval)); 1547 return (retval); 1548 } 1549 1550 1551 /* 1552 * Handle an interrupt or interrupts that may or may not be from 1553 * one or more of the bpp units. 1554 */ 1555 static uint_t 1556 bpp_intr(caddr_t unit_no) 1557 { 1558 int bpp_unit_no; 1559 timeout_id_t tid; 1560 uint_t int_serviced = DDI_INTR_UNCLAIMED; 1561 register struct buf *bp; 1562 register volatile struct bpp_regs *bpp_regs_p; 1563 register struct bpp_unit *bpp_p; /* will point to this */ 1564 /* unit's state struct */ 1565 register struct bpp_error_status *bpp_errorstat_p; /* error stat */ 1566 1567 BPP_PRINT(2, (CE_CONT, "Entering bpp_intr, unit number %d\n", unit_no)); 1568 bpp_unit_no = (int)(uintptr_t)unit_no; 1569 1570 /* 1571 * Check that this unit is indeed interrupting. 1572 */ 1573 bpp_p = getsoftc(bpp_unit_no); 1574 bpp_regs_p = bpp_p->bpp_regs_p; 1575 bpp_errorstat_p = &bpp_p->error_stat; 1576 mutex_enter(&bpp_p->bpp_mutex); 1577 if ((bpp_regs_p->dma_csr & BPP_INT_PEND) || 1578 (bpp_regs_p->dma_csr & BPP_ERR_PEND)) { 1579 BPP_PRINT(5, (CE_CONT, "Interrupt found, unit #%d.\n", 1580 bpp_unit_no)); 1581 /* 1582 * Mark that we found an interrupting device. 1583 * Call the interrupt service routine. 1584 */ 1585 int_serviced = DDI_INTR_CLAIMED; 1586 if (bpp_p->intrstats) { 1587 KIOIP->intrs[KSTAT_INTR_HARD]++; 1588 } 1589 1590 /* 1591 * The bpp hardware can interrupt for errors, or 1592 * for several transfer conditions. These can happen 1593 * at the same time. 1594 * I process any errors first, checking to see 1595 * if a transfer was in process. 1596 * In the future, I may want to count how many times I've 1597 * tried to flush the cache, and eventually give up and 1598 * reset the hardware. 1599 * Then I process "normal" conditions. 1600 */ 1601 1602 bp = bpp_p->bpp_buffer; /* saved in bpp_strategy */ 1603 /* 1604 * Check for an error, recover if possible. 1605 */ 1606 if (bpp_regs_p->dma_csr & BPP_ERR_PEND) { 1607 #if BPP_DEBUG 1608 BPP_PRINT(5, (CE_CONT, "Error interrupt detected\n")); 1609 if (bpp_regs_p->dma_csr & BPP_SLAVE_ERR) { 1610 BPP_PRINT(5, 1611 (CE_CONT, "Slave error detected\n")); 1612 } 1613 #endif /* BPP_DEBUG */ 1614 if (bpp_regs_p->dma_csr & BPP_ENABLE_DMA) { 1615 /* was transferring */ 1616 /* 1617 * The transfer has failed. Notify the 1618 * application how many bytes got out, 1619 * and that there was an IO error, 1620 * and turn off the transfer. 1621 */ 1622 bpp_transfer_failed(bpp_unit_no); 1623 mutex_exit(&bpp_p->bpp_mutex); 1624 return (DDI_INTR_CLAIMED); 1625 } else { 1626 /* will make return value -1 */ 1627 bp->b_flags |= B_ERROR; 1628 bp->b_resid = bp->b_bcount; 1629 } 1630 /* 1631 * capture the error status in the error_stat struct 1632 * so the application can get it with the GETERR 1633 * ioctl later. 1634 */ 1635 bpp_errorstat_p->bus_error = 1; 1636 1637 /* Mark the error. */ 1638 bp->b_error = EIO; 1639 1640 /* clear the error interrupt */ 1641 while (bp->b_flags & B_READ) 1642 ; 1643 /* wait here */ 1644 /* cannot assert FLUSH till cache drains */ 1645 /* spin on draining bit */ 1646 bpp_regs_p->dma_csr |= BPP_FLUSH; 1647 } 1648 if (bpp_regs_p->dma_csr & BPP_INT_PEND) { 1649 BPP_PRINT(5, (CE_CONT, "Interrupt pending found.\n")); 1650 BPP_PRINT(5, (CE_CONT, "dma csr contains 0x%x.\n", 1651 bpp_regs_p->dma_csr)); 1652 BPP_PRINT(5, (CE_CONT, "int cntl contains 0x%x.\n", 1653 bpp_regs_p->int_cntl)); 1654 /* TC case - terminal count */ 1655 if (bpp_regs_p->dma_csr & BPP_TERMINAL_CNT && 1656 ((bpp_regs_p->dma_csr & BPP_TC_INTR_DISABLE) == 1657 0)) { 1658 BPP_PRINT(5, (CE_CONT, 1659 "Terminal count interrupt found.\n")); 1660 /* mask this interrupt */ 1661 bpp_regs_p->dma_csr |= BPP_TC_INTR_DISABLE; 1662 bpp_regs_p->dma_csr &= ~BPP_ENABLE_BCNT; 1663 /* and clear the interrupting condition */ 1664 bpp_regs_p->dma_csr |= BPP_TERMINAL_CNT; 1665 bpp_regs_p->dma_csr &= ~BPP_ENABLE_DMA; 1666 bp->b_resid = bpp_p->transfer_remainder; 1667 /* Mask the error interrupt conditions */ 1668 bpp_regs_p->int_cntl &= 1669 ~(BPP_ERR_IRQ_EN | BPP_SLCT_IRQ_EN | 1670 BPP_PE_IRQ_EN); 1671 BPP_PRINT(5, (CE_CONT, "dma csr 0x%x.\n", 1672 bpp_regs_p->dma_csr)); 1673 BPP_PRINT(5, (CE_CONT, "int cntl 0x%x.\n", 1674 bpp_regs_p->int_cntl)); 1675 } 1676 /* ERR_IRQ case - error pin interrupt */ 1677 if ((bpp_regs_p->int_cntl & BPP_ERR_IRQ) && 1678 (bpp_regs_p->int_cntl & BPP_ERR_IRQ_EN)) { 1679 BPP_PRINT(5, (CE_CONT, 1680 "Error pin interrupt found.\n")); 1681 bpp_errorstat_p->pin_status |= BPP_ERR_ERR; 1682 if (bpp_regs_p->dma_csr & BPP_ENABLE_DMA) { 1683 /* was transferring */ 1684 bpp_transfer_failed(bpp_unit_no); 1685 } 1686 /* clear interrupting condition */ 1687 bpp_regs_p->int_cntl |= BPP_ERR_IRQ; 1688 } 1689 /* SLCT_IRQ case - select pin interrupt */ 1690 if ((bpp_regs_p->int_cntl & BPP_SLCT_IRQ) && 1691 (bpp_regs_p->int_cntl & BPP_SLCT_IRQ_EN)) { 1692 BPP_PRINT(5, (CE_CONT, 1693 "Select pin interrupt found.\n")); 1694 bpp_errorstat_p->pin_status |= BPP_SLCT_ERR; 1695 if (bpp_regs_p->dma_csr & BPP_ENABLE_DMA) { 1696 /* was transferring */ 1697 bpp_transfer_failed(bpp_unit_no); 1698 } 1699 /* clear interrupting condition */ 1700 bpp_regs_p->int_cntl |= BPP_SLCT_IRQ; 1701 } 1702 /* PE_IRQ case - paper error pin interrupt */ 1703 if ((bpp_regs_p->int_cntl & BPP_PE_IRQ) && 1704 (bpp_regs_p->int_cntl & BPP_PE_IRQ_EN)) { 1705 BPP_PRINT(5, (CE_CONT, 1706 "Paper error pin interrupt found.\n")); 1707 bpp_errorstat_p->pin_status |= BPP_PE_ERR; 1708 if (bpp_regs_p->dma_csr & BPP_ENABLE_DMA) { 1709 /* was transferring */ 1710 bpp_transfer_failed(bpp_unit_no); 1711 } 1712 /* clear interrupting condition */ 1713 bpp_regs_p->int_cntl |= BPP_PE_IRQ; 1714 } 1715 /* 1716 * The interrupts below (BUSY, ACK, and DS) 1717 * are available in the hardware, but are not 1718 * being used for anything now. 1719 */ 1720 /* BUSY_IRQ case - busy pin interrupt */ 1721 if ((bpp_regs_p->int_cntl & BPP_BUSY_IRQ) && 1722 (bpp_regs_p->int_cntl & BPP_BUSY_IRQ_EN)) { 1723 BPP_PRINT(5, (CE_CONT, 1724 "Busy pin interrupt found.\n")); 1725 /* for pio only */ 1726 /* clear interrupting condition */ 1727 bpp_regs_p->int_cntl |= BPP_BUSY_IRQ; 1728 } 1729 /* ACK_IRQ case - acknowledge pin interrupt */ 1730 if ((bpp_regs_p->int_cntl & BPP_ACK_IRQ) && 1731 (bpp_regs_p->int_cntl & BPP_ACK_IRQ_EN)) { 1732 BPP_PRINT(5, (CE_CONT, 1733 "Acknowledge pin interrupt found.\n")); 1734 /* for pio only */ 1735 /* clear interrupting condition */ 1736 bpp_regs_p->int_cntl |= BPP_ACK_IRQ; 1737 } 1738 /* DS_IRQ case - data strobe pin interrupt */ 1739 if ((bpp_regs_p->int_cntl & BPP_DS_IRQ) && 1740 (bpp_regs_p->int_cntl & BPP_DS_IRQ_EN)) { 1741 BPP_PRINT(5, (CE_CONT, 1742 "Data strobe pin interrupt found.\n")); 1743 /* for pio only */ 1744 /* clear interrupting condition */ 1745 bpp_regs_p->int_cntl |= BPP_DS_IRQ; 1746 } 1747 } /* end of INT_PEND check */ 1748 1749 BPP_PRINT(5, (CE_CONT, 1750 "dma csr 0x%x.\n", bpp_regs_p->dma_csr)); 1751 BPP_PRINT(5, (CE_CONT, 1752 "int cntl 0x%x.\n", bpp_regs_p->int_cntl)); 1753 1754 /* Clear the transfer timeout */ 1755 BPP_PRINT(5, (CE_CONT, 1756 "In bpp_intr, Clearing transfer timeout.\n")); 1757 tid = bpp_p->bpp_transfer_timeout_ident; 1758 bpp_p->bpp_transfer_timeout_ident = 0; 1759 bpp_p->timeouts &= ~TRANSFER_TIMEOUT; 1760 BPP_PRINT(5, (CE_CONT, "In bpp_intr, Timeout block is 0x%x.\n", 1761 bpp_p->timeouts)); 1762 /* 1763 * Release the dvma bus resource. 1764 */ 1765 1766 (void) ddi_dma_unbind_handle(bpp_p->bpp_dma_handle); 1767 1768 BPP_PRINT(5, (CE_CONT, 1769 "bpp_intr, unit %d, Calling biodone.\n", unit_no)); 1770 /* 1771 * Mark the io on the buf as finished, with the side effect 1772 * of waking up others who want to use the buf. 1773 */ 1774 mutex_exit(&bpp_p->bpp_mutex); 1775 if (tid) 1776 (void) untimeout(tid); 1777 (void) biodone(bp); 1778 } else { 1779 if (bpp_p->intrstats) { 1780 KIOIP->intrs[KSTAT_INTR_SPURIOUS]++; 1781 } 1782 mutex_exit(&bpp_p->bpp_mutex); 1783 } 1784 BPP_PRINT(2, (CE_CONT, "Leaving bpp_intr, int_serviced = 0x%x.\n", 1785 int_serviced)); 1786 return (int_serviced); 1787 } 1788 1789 1790 /* 1791 * A transfer has failed for some reason. 1792 * Mark the bp struct to indicate how much happened, 1793 * and turn off the transfer and its interrupts. 1794 */ 1795 static void 1796 bpp_transfer_failed(int unit_no) 1797 { 1798 struct buf *bp; 1799 register volatile struct bpp_regs *bpp_regs_p; 1800 register struct bpp_unit *bpp_p; /* will point to this */ 1801 /* unit's state struct */ 1802 1803 bpp_p = getsoftc(unit_no); 1804 bp = bpp_p->bpp_buffer; /* saved in bpp_strategy */ 1805 bpp_regs_p = bpp_p->bpp_regs_p; 1806 1807 BPP_PRINT(2, (CE_CONT, "Entering bpp_transfer_failed.\n")); 1808 BPP_PRINT(1, (CE_CONT, "ERROR: bpp%d transfer failed!\n", unit_no)); 1809 1810 ASSERT(MUTEX_HELD(&bpp_p->bpp_mutex)); 1811 /* 1812 * The transfer has failed. Notify the application 1813 * how many bytes got out, and turn off the transfer. 1814 * NOTE: don't set B_ERROR in b_flags else the return from 1815 * write() will be -1. See syscall(). 1816 * NOTE: the kernel ignores the the b_error field 1817 * in the short-write case - errno is always set to zero. 1818 */ 1819 /* Disable the DMA first for safety */ 1820 bpp_regs_p->dma_csr &= ~BPP_ENABLE_DMA; 1821 1822 1823 /* If the DMA state machines are not idle, reset them. */ 1824 if (!(bpp_regs_p->op_config & BPP_IDLE)) { 1825 BPP_PRINT(1, (CE_CONT, "Warning: DMA is not IDLE!\n")); 1826 bpp_regs_p->dma_csr &= ~BPP_ENABLE_BCNT; 1827 BPP_PRINT(1, (CE_CONT, 1828 "In bpp_strategy, resetting PP state machine\n")); 1829 bpp_regs_p->op_config |= BPP_SRST; 1830 bpp_regs_p->op_config &= ~BPP_SRST; 1831 1832 /* 1833 * we have not received the acknowledge for the last 1834 * byte transferred, so the byte counter was never 1835 * decremented for it. 1836 */ 1837 bp->b_resid = ((bpp_regs_p->dma_bcnt - 1) + 1838 bpp_p->transfer_remainder); 1839 } else { 1840 bpp_regs_p->dma_csr &= ~BPP_ENABLE_BCNT; 1841 bp->b_resid = (bpp_regs_p->dma_bcnt + 1842 bpp_p->transfer_remainder); 1843 } 1844 /* flush the local cache */ 1845 bpp_regs_p->dma_csr |= BPP_FLUSH; 1846 1847 BPP_PRINT(5, (CE_CONT, 1848 "In bpp_transfer_failed, Residual is %d.\n", bp->b_resid)); 1849 1850 /* make sure the DMA doesn't start again. */ 1851 bpp_regs_p->dma_bcnt = 0; 1852 /* 1853 * Disable the TC interrupts. 1854 * Mask the error interrupts too. 1855 */ 1856 bpp_regs_p->dma_csr |= BPP_TC_INTR_DISABLE; 1857 bpp_regs_p->int_cntl &= 1858 ~(BPP_ERR_IRQ_EN | BPP_SLCT_IRQ_EN | BPP_PE_IRQ_EN); 1859 1860 /* Check for any of the input pins active */ 1861 check_for_active_pins(unit_no); 1862 BPP_PRINT(2, (CE_CONT, "Leaving bpp_transfer_failed.\n")); 1863 } 1864 1865 1866 /* 1867 * This routine is called when the DVMA does not complete 1868 * and generate a TC interrupt. 1869 * I mark the bp struct to indicate that the transfer failed, 1870 * and turn off the transfer. I then call biodone to wake up strategy. 1871 */ 1872 static void 1873 bpp_transfer_timeout(void *unit_no_arg) 1874 { 1875 int unit_no = (int)(uintptr_t)unit_no_arg; 1876 register struct bpp_unit *bpp_p; /* will point to this */ 1877 /* unit's state struct */ 1878 register struct buf *bp; 1879 register volatile struct bpp_regs *bpp_regs_p; 1880 1881 BPP_PRINT(2, (CE_CONT, "Entering bpp_transfer_timeout, unit #%d.\n", 1882 unit_no)); 1883 1884 bpp_p = getsoftc(unit_no); 1885 BPP_PRINT(5, (CE_CONT, 1886 "In bpp_transfer_timeout, Timeout block is 0x%x.\n", 1887 bpp_p->timeouts)); 1888 mutex_enter(&bpp_p->bpp_mutex); 1889 if (bpp_p->bpp_transfer_timeout_ident == 0) { 1890 mutex_exit(&bpp_p->bpp_mutex); 1891 return; 1892 } 1893 1894 ASSERT(bpp_p->timeouts != 0); 1895 1896 /* 1897 * Use the unit number to locate our data structures. 1898 */ 1899 bp = bpp_p->bpp_buffer; /* saved in bpp_strategy */ 1900 bpp_regs_p = bpp_p->bpp_regs_p; 1901 1902 /* 1903 * If we're talking to the 1904 * Ricoh scanner, handle it's special "hold busy" 1905 * protocol -- Toggle the print/scan (PR/SC) bit and 1906 * reset the parallel port 1907 */ 1908 BPP_PRINT(5, (CE_CONT, "byte count is %d.\n", bpp_regs_p->dma_bcnt)); 1909 BPP_PRINT(5, (CE_CONT, "write_timeout is %d.\n", 1910 bpp_p->transfer_parms.write_timeout)); 1911 if (bpp_regs_p->trans_cntl & BPP_DIRECTION) { 1912 /* read mode - partial reads will time out */ 1913 BPP_PRINT(5, (CE_CONT, "read timeout, clearing registers.\n")); 1914 bp->b_resid = (bpp_regs_p->dma_bcnt + 1915 bpp_p->transfer_remainder); 1916 /* make sure the DMA doesn't start again. */ 1917 bpp_regs_p->dma_bcnt = 0; 1918 /* 1919 * Disable the byte counting, and the TC interrupts. 1920 * Mask the error interrupts too. 1921 */ 1922 bpp_regs_p->dma_csr |= BPP_TC_INTR_DISABLE; 1923 bpp_regs_p->dma_csr &= ~BPP_ENABLE_BCNT; 1924 bpp_regs_p->dma_csr &= ~BPP_ENABLE_DMA; 1925 bpp_regs_p->int_cntl &= ~(BPP_ERR_IRQ_EN | BPP_SLCT_IRQ_EN 1926 | BPP_PE_IRQ_EN); 1927 } else if ((bpp_regs_p->trans_cntl & BPP_DIRECTION) == 0) { 1928 /* other write cases (read can time out w/no error) */ 1929 bpp_transfer_failed(unit_no); 1930 /* Mark the error. */ 1931 /* 1932 * bp->b_resid will be set to indicate the number 1933 * of bytes actually transferred by bpp_transfer_failed(). 1934 * If no bytes were transferred, set B_ERROR 1935 * so that -1 is returned, and set the b_error value. 1936 */ 1937 if (!(bp->b_resid)) { /* not a partial transfer */ 1938 bp->b_flags |= B_ERROR; 1939 bp->b_error = EIO; 1940 } 1941 } 1942 1943 /* mark this timeout as no longer pending */ 1944 bpp_p->bpp_transfer_timeout_ident = 0; 1945 bpp_p->timeouts &= ~TRANSFER_TIMEOUT; 1946 /* mark the error status structure */ 1947 bpp_p->error_stat.timeout_occurred = 1; 1948 BPP_PRINT(5, (CE_CONT, 1949 "In bpp_transfer_timeout, Timeout blk is 0x%x.\n", 1950 bpp_p->timeouts)); 1951 1952 /* 1953 * Release the dvma bus resource. 1954 */ 1955 (void) ddi_dma_unbind_handle(bpp_p->bpp_dma_handle); 1956 1957 BPP_PRINT(5, (CE_CONT, 1958 "bpp_transfer_timeout, unit %d, Calling biodone.\n", unit_no)); 1959 mutex_exit(&bpp_p->bpp_mutex); 1960 (void) biodone(bp); 1961 BPP_PRINT(2, (CE_CONT, "Leaving bpp_transfer_timeout, unit #%d.\n", 1962 unit_no)); 1963 } 1964 1965 1966 /* Utility Functions */ 1967 1968 1969 /* 1970 * The values of read_setup_time and read_strobe_width 1971 * have already been bounds-checked. Convert the requested times 1972 * (in nanoseconds) to SBus clock cycles for the dss and dsw registers. 1973 * Always round the requested setup time up to the next clock 1974 * cycle boundary. 1975 */ 1976 static void 1977 set_dss_dsw(int unit_no, int read_mode) 1978 { 1979 int dss_temp; /* tentative dss value */ 1980 int dsw_temp; /* tentative dsw value */ 1981 register struct bpp_unit *bpp_p; /* will point to this */ 1982 /* unit's state struct */ 1983 register struct bpp_transfer_parms *bpp_transfer_parms_p; 1984 1985 BPP_PRINT(2, (CE_CONT, 1986 "Entering set_dss_dsw, unit:%d, read_mode = %x.\n", 1987 unit_no, read_mode)); 1988 bpp_p = getsoftc(unit_no); 1989 ASSERT(MUTEX_HELD(&bpp_p->bpp_mutex)); 1990 1991 bpp_transfer_parms_p = &bpp_p->transfer_parms; 1992 1993 if (read_mode) { 1994 dss_temp = 1995 bpp_transfer_parms_p->read_setup_time / 1996 bpp_p->sbus_clock_cycle; 1997 if (bpp_transfer_parms_p->read_setup_time % 1998 bpp_p->sbus_clock_cycle) 1999 dss_temp ++; /* round up */ 2000 dsw_temp = 2001 bpp_transfer_parms_p->read_strobe_width / 2002 bpp_p->sbus_clock_cycle; 2003 if (bpp_transfer_parms_p->read_strobe_width % 2004 bpp_p->sbus_clock_cycle) 2005 dsw_temp ++; /* round up */ 2006 } else { 2007 dss_temp = 2008 bpp_transfer_parms_p->write_setup_time / 2009 bpp_p->sbus_clock_cycle; 2010 if (bpp_transfer_parms_p->write_setup_time % 2011 bpp_p->sbus_clock_cycle) 2012 dss_temp ++; /* round up */ 2013 dsw_temp = 2014 bpp_transfer_parms_p->write_strobe_width / 2015 bpp_p->sbus_clock_cycle; 2016 if (bpp_transfer_parms_p->write_strobe_width % 2017 bpp_p->sbus_clock_cycle) 2018 dsw_temp ++; /* round up */ 2019 } 2020 2021 BPP_PRINT(5, (CE_CONT, "dss = 0x%x, dsw = 0x%x\n", dss_temp, dsw_temp)); 2022 bpp_p->bpp_regs_p->hw_config = 2023 ((((uchar_t)dsw_temp) << 8) | ((uchar_t)dss_temp)); 2024 BPP_PRINT(2, (CE_CONT, 2025 "Leaving set_dss_dsw, unit:%d.\n", unit_no)); 2026 } 2027 /* 2028 * Check the values of the write parameters in the passed bpp_transfer_parms 2029 * structure. If all the parameters are in range, 0 is returned. 2030 * If there is an out-of-range parameter, EINVAL is returned. 2031 */ 2032 /*ARGSUSED*/ 2033 static ushort_t 2034 check_write_params(struct bpp_transfer_parms *parms_p, int unit, int flags) 2035 { 2036 ushort_t retval = 0; /* return value (errno) for system call */ 2037 static int max_setup = 0; /* maximum setup time allowed (ns) */ 2038 static int max_width = 0; /* maximum width time allowed (ns) */ 2039 register struct bpp_unit *bpp_p; /* will point to this */ 2040 /* unit's state struct */ 2041 2042 bpp_p = getsoftc(unit); 2043 ASSERT(MUTEX_HELD(&bpp_p->bpp_mutex)); 2044 retval = 0; 2045 BPP_PRINT(2, (CE_CONT, 2046 "Entering check_write_params, parms_p = %x.\n", parms_p)); 2047 BPP_PRINT(5, (CE_CONT, "write_hs %d, write_time %d, \n", 2048 parms_p->write_handshake, parms_p->write_setup_time)); 2049 BPP_PRINT(5, (CE_CONT, "write_width %d, timeout %d.\n", 2050 parms_p->write_strobe_width, parms_p->write_timeout)); 2051 #ifndef lint 2052 /* better rangechecking will be added later */ 2053 /* check for legal range */ 2054 if ((parms_p->write_handshake < BPP_NO_HS) || 2055 (parms_p->write_handshake > BPP_VPLOT_HS)) { 2056 BPP_PRINT(1, (CE_CONT, "Handshake out of legal range!\n")); 2057 retval = EINVAL; 2058 goto out; 2059 } 2060 /* the handshake values overlap. Check for read handshakes */ 2061 if ((parms_p->write_handshake > BPP_BUSY_HS) && 2062 (parms_p->write_handshake < BPP_VPRINT_HS)) { 2063 BPP_PRINT(1, (CE_CONT, 2064 "Handshake out of legal write range!\n")); 2065 retval = EINVAL; 2066 goto out; 2067 } 2068 /* versatec handshakes illegal in read-write mode */ 2069 if ((flags & FREAD) && (parms_p->write_handshake > BPP_BUSY_HS)) { 2070 BPP_PRINT(1, (CE_CONT, "No versatec handshakes in read md!\n")); 2071 retval = EINVAL; 2072 goto out; 2073 } 2074 /* 2075 * Originally there was a plan to support a versatec mode. 2076 * The decision was made not to support it in software. 2077 * However, the hooks are still there in the hardware. 2078 * I leave the versatec fragments in case the decision is ever 2079 * reversed. 2080 */ 2081 /* versatec handshakes not implemented in current code */ 2082 if ((parms_p->write_handshake > BPP_BUSY_HS)) { 2083 BPP_PRINT(1, (CE_CONT, 2084 "No versatec handshakes allowed yet!\n")); 2085 retval = EINVAL; 2086 goto out; 2087 } 2088 #endif /* lint */ 2089 /* check range of setup time and strobe width here */ 2090 max_setup = BPP_DSS_SIZE * bpp_p->sbus_clock_cycle; 2091 max_width = BPP_DSW_SIZE * bpp_p->sbus_clock_cycle; 2092 2093 if ((parms_p->write_setup_time < 0) || 2094 (parms_p->write_setup_time > max_setup)) { 2095 BPP_PRINT(1, (CE_CONT, 2096 "Write setup time out of legal range!\n")); 2097 retval = EINVAL; 2098 goto out; 2099 } 2100 if ((parms_p->write_strobe_width < 0) || 2101 (parms_p->write_strobe_width > max_width)) { 2102 BPP_PRINT(1, (CE_CONT, 2103 "Write strobe width out of legal range!\n")); 2104 retval = EINVAL; 2105 goto out; 2106 } 2107 2108 /* check range of write timeout */ 2109 if ((parms_p->write_timeout < 0) || 2110 (parms_p->write_timeout > MAX_TIMEOUT)) { 2111 BPP_PRINT(1, (CE_CONT, 2112 "Write timeout out of legal range!\n")); 2113 retval = EINVAL; 2114 goto out; 2115 } 2116 2117 out: 2118 BPP_PRINT(2, (CE_CONT, 2119 "Leaving check_write_params, retval = %d.\n", retval)); 2120 return (retval); 2121 } 2122 2123 /* 2124 * Check the values of the read parameters in the passed bpp_transfer_parms 2125 * structure. If all the parameters are in range, 0 is returned. 2126 * If there is an out-of-range parameter, EINVAL is returned. 2127 */ 2128 /*ARGSUSED*/ 2129 static ushort_t 2130 check_read_params(struct bpp_transfer_parms *parms_p, uint_t unit, int flags) 2131 { 2132 ushort_t retval = 0; /* return value (errno) for system call */ 2133 static int max_setup = 0; /* maximum setup time allowed (ns) */ 2134 static int max_width = 0; /* maximum width time allowed (ns) */ 2135 register struct bpp_unit *bpp_p; /* will point to this */ 2136 /* unit's state struct */ 2137 2138 bpp_p = getsoftc(unit); 2139 ASSERT(MUTEX_HELD(&bpp_p->bpp_mutex)); 2140 retval = 0; 2141 BPP_PRINT(2, (CE_CONT, 2142 "Entering check_read_params, parms_p = %x.\n", parms_p)); 2143 BPP_PRINT(5, (CE_CONT, 2144 "read_hs %d, read_time %d, read_width %d, timeout %d.\n", 2145 parms_p->read_handshake, parms_p->read_setup_time, 2146 parms_p->read_strobe_width, parms_p->read_timeout)); 2147 #ifndef lint 2148 /* check for legal range */ 2149 if ((parms_p->read_handshake < BPP_NO_HS) || 2150 (parms_p->read_handshake > BPP_SET_MEM)) { 2151 BPP_PRINT(1, (CE_CONT, "Handshake out of legal range!\n")); 2152 retval = EINVAL; 2153 goto out; 2154 } 2155 #endif /* lint */ 2156 /* check range of setup time and strobe width here */ 2157 max_setup = BPP_DSS_SIZE * bpp_p->sbus_clock_cycle; 2158 max_width = BPP_DSW_SIZE * bpp_p->sbus_clock_cycle; 2159 2160 if ((parms_p->read_setup_time < 0) || 2161 (parms_p->read_setup_time > max_setup)) { 2162 BPP_PRINT(1, (CE_CONT, 2163 "Read setup time out of legal range!\n")); 2164 retval = EINVAL; 2165 goto out; 2166 } 2167 if ((parms_p->read_strobe_width < 0) || 2168 (parms_p->read_strobe_width > max_width)) { 2169 BPP_PRINT(1, (CE_CONT, 2170 "Read strobe width out of legal range!\n")); 2171 retval = EINVAL; 2172 goto out; 2173 } 2174 2175 /* check range of read timeout */ 2176 if ((parms_p->read_timeout < 0) || 2177 (parms_p->read_timeout > MAX_TIMEOUT)) { 2178 BPP_PRINT(1, (CE_CONT, 2179 "Read timeout out of legal range!\n")); 2180 retval = EINVAL; 2181 goto out; 2182 } 2183 2184 out: 2185 BPP_PRINT(2, (CE_CONT, 2186 "Leaving check_read_params, retval = %d.\n", retval)); 2187 return (retval); 2188 } 2189 2190 /*ARGSUSED*/ 2191 static ushort_t 2192 check_read_pins(struct bpp_pins *pins_p, int flags, uint_t unit, 2193 register enum handshake_t handshake) 2194 { 2195 ushort_t retval = 0; /* return value (errno) for system call */ 2196 register struct bpp_unit *bpp_p; /* will point to this */ 2197 /* unit's state struct */ 2198 2199 bpp_p = getsoftc(unit); 2200 ASSERT(MUTEX_HELD(&bpp_p->bpp_mutex)); 2201 BPP_PRINT(2, (CE_CONT, 2202 "Entering check_read_pins, pins_p = 0x%x \n", pins_p)); 2203 BPP_PRINT(5, (CE_CONT, 2204 "outpins = 0x%x, inpins = 0x%x.\n", pins_p->output_reg_pins, 2205 pins_p->input_reg_pins)); 2206 /* check for bogus bits turned on */ 2207 if ((pins_p->output_reg_pins & ~BPP_ALL_OUT_PINS) || 2208 (pins_p->input_reg_pins & ~BPP_ALL_IN_PINS)) { 2209 BPP_PRINT(1, (CE_CONT, 2210 "Check pins : Bogus bit in bpp pins structure!\n")); 2211 retval = EINVAL; 2212 goto out; 2213 } 2214 out: 2215 BPP_PRINT(2, (CE_CONT, 2216 "Leaving check_read_pins, retval = %d.\n", retval)); 2217 return (retval); 2218 } 2219 2220 /*ARGSUSED*/ 2221 static ushort_t 2222 check_write_pins(struct bpp_pins *pins_p, int flags, uint_t unit, 2223 register enum handshake_t handshake) 2224 { 2225 ushort_t retval = 0; /* return value (errno) for system call */ 2226 register struct bpp_unit *bpp_p; /* will point to this */ 2227 /* unit's state struct */ 2228 2229 bpp_p = getsoftc(unit); 2230 ASSERT(MUTEX_HELD(&bpp_p->bpp_mutex)); 2231 BPP_PRINT(2, (CE_CONT, 2232 "Entering check_write_pins, pins_p = 0x%x, \n", pins_p)); 2233 BPP_PRINT(5, (CE_CONT, "outpins = 0x%x, inpins = 0x%x.\n", 2234 pins_p->output_reg_pins, pins_p->input_reg_pins)); 2235 /* check for bogus bits turned on */ 2236 if ((pins_p->output_reg_pins & ~BPP_ALL_OUT_PINS) || 2237 (pins_p->input_reg_pins & ~BPP_ALL_IN_PINS)) { 2238 BPP_PRINT(1, (CE_CONT, 2239 "Check pins : Bogus bit in bpp pins structure!\n")); 2240 retval = EINVAL; 2241 goto out; 2242 } 2243 /* 2244 * Originally there was a plan to support a versatec mode. 2245 * The decision was made not to support it in software. 2246 * However, the hooks are still there in the hardware. 2247 * I leave the versatec fragments in case the decision is ever 2248 * reversed. 2249 */ 2250 #ifndef lint 2251 /* versatec handshakes not implemented in current code */ 2252 if ((handshake > BPP_BUSY_HS)) { 2253 BPP_PRINT(1, (CE_CONT, 2254 "No versatec handshakes allowed yet!\n")); 2255 /* 2256 * really, need to check for one bit only of remote 2257 * pins set. 2258 */ 2259 retval = EINVAL; 2260 goto out; 2261 } 2262 #endif /* lint */ 2263 out: 2264 BPP_PRINT(2, (CE_CONT, 2265 "Leaving check_write_pins, retval = %d.\n", retval)); 2266 return (retval); 2267 } 2268 2269 /* ARGSUSED */ 2270 static void 2271 read_outpins(int unit_no, int flags, register enum handshake_t handshake) 2272 { 2273 register struct bpp_unit *bpp_p; /* will point to this */ 2274 /* unit's state struct */ 2275 uchar_t temppins; 2276 BPP_PRINT(2, (CE_CONT, 2277 "Entering read_outpins, unit = %d, flags = 0x%x, \n", 2278 unit_no, flags)); 2279 bpp_p = getsoftc(unit_no); 2280 ASSERT(MUTEX_HELD(&bpp_p->bpp_mutex)); 2281 2282 BPP_PRINT(5, (CE_CONT, "handshake = %d.\n", handshake)); 2283 if (flags & FWRITE) { 2284 2285 #if BPP_DEBUG > 0 2286 if (handshake > BPP_BUSY_HS) { 2287 BPP_PRINT(1, (CE_CONT, 2288 "No versatec handshakes allowed yet!\n")); 2289 } 2290 #endif /* BPP_DEBUG */ 2291 2292 temppins = bpp_p->bpp_regs_p->out_pins & 2293 (BPP_SLCTIN_PIN | BPP_AFX_PIN | BPP_INIT_PIN); 2294 bpp_p->pins.output_reg_pins |= temppins; 2295 } 2296 2297 BPP_PRINT(2, (CE_CONT, "Leaving read_outpins.\n")); 2298 } 2299 2300 /* 2301 * Peek at the bpp registers to make sure that they really 2302 * exist. Also check initial conditions. If any of this 2303 * fails, return a non-zero value. 2304 */ 2305 static int 2306 check_bpp_registers(int unit_no) 2307 { 2308 volatile uint32_t *l_reg_addr; /* address of a 32-bit reg */ 2309 volatile uint32_t l_reg_contents; /* contents of a 32-bit reg */ 2310 volatile ushort_t *s_reg_addr; /* address of a 16-bit reg */ 2311 volatile ushort_t s_reg_contents; /* contents of a 16-bit reg */ 2312 volatile uchar_t *c_reg_addr; /* address of a 8-bit reg */ 2313 volatile uchar_t c_reg_contents; /* contents of a 8-bit reg */ 2314 register struct bpp_unit *bpp_p; /* will point to this */ 2315 /* unit's state struct */ 2316 2317 BPP_PRINT(2, (CE_CONT, "Entering check_bpp_registers, unit %d.\n", 2318 unit_no)); 2319 bpp_p = getsoftc(unit_no); 2320 /* check the 32-bit dma registers */ 2321 /* dma csr */ 2322 l_reg_addr = &(bpp_p->bpp_regs_p->dma_csr); 2323 if (ddi_peek32(bpp_p->dip, 2324 (int32_t *)l_reg_addr, (int32_t *)&l_reg_contents) != DDI_SUCCESS) { 2325 BPP_PRINT(1, (CE_CONT, 2326 "ck_bpp_registers: peek failed dma csr, address %x\n", 2327 l_reg_addr)); 2328 return (1); 2329 } 2330 BPP_PRINT(5, (CE_CONT, "dma_csr contains %x\n", l_reg_contents)); 2331 2332 /* dma addr */ 2333 l_reg_addr = &(bpp_p->bpp_regs_p->dma_addr); 2334 if (ddi_peek32(bpp_p->dip, 2335 (int32_t *)l_reg_addr, (int32_t *)&l_reg_contents) != DDI_SUCCESS) { 2336 BPP_PRINT(1, (CE_CONT, 2337 "ck_bpp_registers: peek failed dma addr, address %x\n", 2338 l_reg_addr)); 2339 return (1); 2340 } 2341 BPP_PRINT(5, (CE_CONT, "dma_addr contains %x\n", l_reg_contents)); 2342 2343 /* dma bcnt */ 2344 l_reg_addr = &(bpp_p->bpp_regs_p->dma_bcnt); 2345 if (ddi_peek32(bpp_p->dip, 2346 (int32_t *)l_reg_addr, (int32_t *)&l_reg_contents) != DDI_SUCCESS) { 2347 BPP_PRINT(1, (CE_CONT, 2348 "ck_bpp_registers: peek failed dma bcnt, address %x\n", 2349 l_reg_addr)); 2350 return (1); 2351 } 2352 BPP_PRINT(5, (CE_CONT, "dma_bcnt contains %x\n", l_reg_contents)); 2353 2354 /* short hardware registers */ 2355 /* hw_config */ 2356 s_reg_addr = &(bpp_p->bpp_regs_p->hw_config); 2357 if (ddi_peek16(bpp_p->dip, 2358 (int16_t *)s_reg_addr, (int16_t *)&s_reg_contents) != DDI_SUCCESS) { 2359 BPP_PRINT(1, (CE_CONT, 2360 "ck_bpp_registers: peek failed hw_config, address %x\n", 2361 s_reg_addr)); 2362 return (1); 2363 } 2364 if (ddi_poke16(bpp_p->dip, 2365 (short *)s_reg_addr, s_reg_contents) != DDI_SUCCESS) { 2366 BPP_PRINT(1, (CE_CONT, 2367 "ck_bpp_registers: poke failed hw_config, address %x\n", 2368 s_reg_addr)); 2369 return (1); 2370 } 2371 BPP_PRINT(5, (CE_CONT, "hw_config contains %x\n", s_reg_contents)); 2372 2373 /* op_config */ 2374 s_reg_addr = &(bpp_p->bpp_regs_p->op_config); 2375 if (ddi_peek16(bpp_p->dip, 2376 (short *)s_reg_addr, (short *)&s_reg_contents) != DDI_SUCCESS) { 2377 BPP_PRINT(1, (CE_CONT, 2378 "ck_bpp_registers: peek failed op_config, address %x\n", 2379 s_reg_addr)); 2380 return (1); 2381 } 2382 BPP_PRINT(5, (CE_CONT, "op_config contains %x\n", s_reg_contents)); 2383 2384 /* int_cntl */ 2385 s_reg_addr = &(bpp_p->bpp_regs_p->int_cntl); 2386 if (ddi_peek16(bpp_p->dip, 2387 (short *)s_reg_addr, (short *)&s_reg_contents) != DDI_SUCCESS) { 2388 BPP_PRINT(1, (CE_CONT, 2389 "ck_bpp_registers: peek failed int_cntl, address %x\n", 2390 s_reg_addr)); 2391 return (1); 2392 } 2393 BPP_PRINT(5, (CE_CONT, "int_cntl contains %x\n", s_reg_contents)); 2394 2395 /* char hardware registers */ 2396 /* data */ 2397 c_reg_addr = &(bpp_p->bpp_regs_p->data); 2398 if (ddi_peek8(bpp_p->dip, 2399 (char *)c_reg_addr, (char *)&c_reg_contents) != DDI_SUCCESS) { 2400 BPP_PRINT(1, (CE_CONT, 2401 "ck_bpp_registers: peek failed data, address %x\n", 2402 c_reg_addr)); 2403 return (1); 2404 } 2405 BPP_PRINT(5, (CE_CONT, "data contains %x\n", c_reg_contents)); 2406 2407 /* trans_cntl */ 2408 c_reg_addr = &(bpp_p->bpp_regs_p->trans_cntl); 2409 if (ddi_peek8(bpp_p->dip, 2410 (char *)c_reg_addr, (char *)&c_reg_contents) != DDI_SUCCESS) { 2411 BPP_PRINT(1, (CE_CONT, 2412 "ck_bpp_registers:peek failed trans_cntl, address %x\n", 2413 c_reg_addr)); 2414 return (1); 2415 } 2416 BPP_PRINT(5, (CE_CONT, "trans_cntl contains %x\n", c_reg_contents)); 2417 2418 /* out_pins */ 2419 c_reg_addr = &(bpp_p->bpp_regs_p->out_pins); 2420 if (ddi_peek8(bpp_p->dip, 2421 (char *)c_reg_addr, (char *)&c_reg_contents) != DDI_SUCCESS) { 2422 BPP_PRINT(1, (CE_CONT, 2423 "ck_bpp_registers: peek failed out_pins, address %x\n", 2424 c_reg_addr)); 2425 return (1); 2426 } 2427 BPP_PRINT(5, (CE_CONT, "out_pins contains %x\n", c_reg_contents)); 2428 2429 /* in_pins */ 2430 c_reg_addr = &(bpp_p->bpp_regs_p->in_pins); 2431 if (ddi_peek8(bpp_p->dip, 2432 (char *)c_reg_addr, (char *)&c_reg_contents) != DDI_SUCCESS) { 2433 BPP_PRINT(1, (CE_CONT, 2434 "ck_bpp_registers: peek failed in_pins, address %x\n", 2435 c_reg_addr)); 2436 return (1); 2437 } 2438 BPP_PRINT(5, (CE_CONT, "in_pins contains %x\n", c_reg_contents)); 2439 BPP_PRINT(5, (CE_CONT, 2440 "Leaving check_bpp_registers, unit %d.\n", unit_no)); 2441 return (0); 2442 } 2443
Indexes created Fri Nov 27 17:59:51 UTC 2009
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