1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * PCI to PCI bus bridge nexus driver 28 */ 29 30 #include <sys/conf.h> 31 #include <sys/kmem.h> 32 #include <sys/debug.h> 33 #include <sys/modctl.h> 34 #include <sys/autoconf.h> 35 #include <sys/ddi_impldefs.h> 36 #include <sys/pci.h> 37 #include <sys/pci_impl.h> 38 #include <sys/pcie_impl.h> 39 #include <sys/ddi.h> 40 #include <sys/sunddi.h> 41 #include <sys/sunndi.h> 42 #include <sys/ddifm.h> 43 #include <sys/ndifm.h> 44 #include <sys/fm/protocol.h> 45 #include <sys/hotplug/pci/pcie_hp.h> 46 #include <sys/hotplug/pci/pcihp.h> 47 #include <sys/pci_intr_lib.h> 48 #include <sys/psm.h> 49 #include <sys/pci_cap.h> 50 51 /* 52 * The variable controls the default setting of the command register 53 * for pci devices. See ppb_initchild() for details. 54 */ 55 static ushort_t ppb_command_default = PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 56 57 58 static int ppb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *, 59 off_t, off_t, caddr_t *); 60 static int ppb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t, 61 void *, void *); 62 static int ppb_fm_init(dev_info_t *, dev_info_t *, int, 63 ddi_iblock_cookie_t *); 64 static int ppb_fm_callback(dev_info_t *, ddi_fm_error_t *, const void *); 65 static int ppb_intr_ops(dev_info_t *, dev_info_t *, ddi_intr_op_t, 66 ddi_intr_handle_impl_t *, void *); 67 68 /* 69 * ppb_support_msi: Flag that controls MSI support across P2P Bridges. 70 * By default, MSI is not supported except for special cases like HT 71 * bridges/tunnels that have HT MSI mapping enabled. 72 * 73 * However, MSI support behavior can be patched on a system by changing 74 * the value of this flag as shown below:- 75 * 0 = default value, MSI is allowed by this driver for special cases 76 * 1 = MSI supported without any checks for this driver 77 * -1 = MSI not supported at all 78 */ 79 int ppb_support_msi = 0; 80 81 /* 82 * Controls the usage of the Hypertransport MSI mapping capability 83 * 0 = default value, leave hardware function as it is 84 * 1 = always enable HT MSI mapping 85 * -1 = always disable HT MSI mapping 86 */ 87 int ppb_support_ht_msimap = 0; 88 89 struct bus_ops ppb_bus_ops = { 90 BUSO_REV, 91 ppb_bus_map, 92 0, 93 0, 94 0, 95 i_ddi_map_fault, 96 ddi_dma_map, 97 ddi_dma_allochdl, 98 ddi_dma_freehdl, 99 ddi_dma_bindhdl, 100 ddi_dma_unbindhdl, 101 ddi_dma_flush, 102 ddi_dma_win, 103 ddi_dma_mctl, 104 ppb_ctlops, 105 ddi_bus_prop_op, 106 0, /* (*bus_get_eventcookie)(); */ 107 0, /* (*bus_add_eventcall)(); */ 108 0, /* (*bus_remove_eventcall)(); */ 109 0, /* (*bus_post_event)(); */ 110 0, /* (*bus_intr_ctl)(); */ 111 0, /* (*bus_config)(); */ 112 0, /* (*bus_unconfig)(); */ 113 ppb_fm_init, /* (*bus_fm_init)(); */ 114 NULL, /* (*bus_fm_fini)(); */ 115 NULL, /* (*bus_fm_access_enter)(); */ 116 NULL, /* (*bus_fm_access_exit)(); */ 117 NULL, /* (*bus_power)(); */ 118 ppb_intr_ops, /* (*bus_intr_op)(); */ 119 pcie_hp_common_ops /* (*bus_hp_op)(); */ 120 }; 121 122 /* 123 * The goal here is to leverage off of the pcihp.c source without making 124 * changes to it. Call into it's cb_ops directly if needed. 125 */ 126 static int ppb_open(dev_t *, int, int, cred_t *); 127 static int ppb_close(dev_t, int, int, cred_t *); 128 static int ppb_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 129 static int ppb_prop_op(dev_t, dev_info_t *, ddi_prop_op_t, int, char *, 130 caddr_t, int *); 131 static int ppb_info(dev_info_t *, ddi_info_cmd_t, void *, void **); 132 static void ppb_peekpoke_cb(dev_info_t *, ddi_fm_error_t *); 133 134 struct cb_ops ppb_cb_ops = { 135 ppb_open, /* open */ 136 ppb_close, /* close */ 137 nodev, /* strategy */ 138 nodev, /* print */ 139 nodev, /* dump */ 140 nodev, /* read */ 141 nodev, /* write */ 142 ppb_ioctl, /* ioctl */ 143 nodev, /* devmap */ 144 nodev, /* mmap */ 145 nodev, /* segmap */ 146 nochpoll, /* poll */ 147 ppb_prop_op, /* cb_prop_op */ 148 NULL, /* streamtab */ 149 D_NEW | D_MP | D_HOTPLUG, /* Driver compatibility flag */ 150 CB_REV, /* rev */ 151 nodev, /* int (*cb_aread)() */ 152 nodev /* int (*cb_awrite)() */ 153 }; 154 155 156 static int ppb_probe(dev_info_t *); 157 static int ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd); 158 static int ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 159 160 struct dev_ops ppb_ops = { 161 DEVO_REV, /* devo_rev */ 162 0, /* refcnt */ 163 ppb_info, /* info */ 164 nulldev, /* identify */ 165 ppb_probe, /* probe */ 166 ppb_attach, /* attach */ 167 ppb_detach, /* detach */ 168 nulldev, /* reset */ 169 &ppb_cb_ops, /* driver operations */ 170 &ppb_bus_ops, /* bus operations */ 171 NULL, /* power */ 172 ddi_quiesce_not_needed, /* quiesce */ 173 }; 174 175 /* 176 * Module linkage information for the kernel. 177 */ 178 179 static struct modldrv modldrv = { 180 &mod_driverops, /* Type of module */ 181 "Standard PCI to PCI bridge nexus driver", 182 &ppb_ops, /* driver ops */ 183 }; 184 185 static struct modlinkage modlinkage = { 186 MODREV_1, 187 (void *)&modldrv, 188 NULL 189 }; 190 191 /* 192 * soft state pointer and structure template: 193 */ 194 static void *ppb_state; 195 196 typedef struct { 197 dev_info_t *dip; 198 int ppb_fmcap; 199 ddi_iblock_cookie_t ppb_fm_ibc; 200 kmutex_t ppb_mutex; 201 kmutex_t ppb_peek_poke_mutex; 202 kmutex_t ppb_err_mutex; 203 204 /* 205 * cpr support: 206 */ 207 uint_t config_state_index; 208 struct { 209 dev_info_t *dip; 210 ushort_t command; 211 uchar_t cache_line_size; 212 uchar_t latency_timer; 213 uchar_t header_type; 214 uchar_t sec_latency_timer; 215 ushort_t bridge_control; 216 } config_state[PCI_MAX_CHILDREN]; 217 218 uint16_t parent_bus; 219 } ppb_devstate_t; 220 221 222 /* 223 * forward function declarations: 224 */ 225 static void ppb_removechild(dev_info_t *); 226 static int ppb_initchild(dev_info_t *child); 227 static void ppb_save_config_regs(ppb_devstate_t *ppb_p); 228 static void ppb_restore_config_regs(ppb_devstate_t *ppb_p); 229 static boolean_t ppb_ht_msimap_check(ddi_acc_handle_t cfg_hdl); 230 static int ppb_ht_msimap_set(ddi_acc_handle_t cfg_hdl, int cmd); 231 232 /* 233 * for <cmd> in ppb_ht_msimap_set 234 */ 235 #define HT_MSIMAP_ENABLE 1 236 #define HT_MSIMAP_DISABLE 0 237 238 239 int 240 _init(void) 241 { 242 int e; 243 244 if ((e = ddi_soft_state_init(&ppb_state, sizeof (ppb_devstate_t), 245 1)) == 0 && (e = mod_install(&modlinkage)) != 0) 246 ddi_soft_state_fini(&ppb_state); 247 return (e); 248 } 249 250 int 251 _fini(void) 252 { 253 int e; 254 255 if ((e = mod_remove(&modlinkage)) == 0) 256 ddi_soft_state_fini(&ppb_state); 257 return (e); 258 } 259 260 int 261 _info(struct modinfo *modinfop) 262 { 263 return (mod_info(&modlinkage, modinfop)); 264 } 265 266 /*ARGSUSED*/ 267 static int 268 ppb_probe(dev_info_t *devi) 269 { 270 return (DDI_PROBE_SUCCESS); 271 } 272 273 /*ARGSUSED*/ 274 static int 275 ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd) 276 { 277 dev_info_t *root = ddi_root_node(); 278 int instance; 279 ppb_devstate_t *ppb; 280 dev_info_t *pdip; 281 ddi_acc_handle_t config_handle; 282 char *bus; 283 int ret; 284 285 switch (cmd) { 286 case DDI_ATTACH: 287 288 /* 289 * Make sure the "device_type" property exists. 290 */ 291 (void) ddi_prop_update_string(DDI_DEV_T_NONE, devi, 292 "device_type", "pci"); 293 294 /* 295 * Allocate and get soft state structure. 296 */ 297 instance = ddi_get_instance(devi); 298 if (ddi_soft_state_zalloc(ppb_state, instance) != DDI_SUCCESS) 299 return (DDI_FAILURE); 300 ppb = ddi_get_soft_state(ppb_state, instance); 301 ppb->dip = devi; 302 303 /* 304 * don't enable ereports if immediate child of npe 305 */ 306 if (strcmp(ddi_driver_name(ddi_get_parent(devi)), "npe") == 0) 307 ppb->ppb_fmcap = DDI_FM_ERRCB_CAPABLE | 308 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE; 309 else 310 ppb->ppb_fmcap = DDI_FM_EREPORT_CAPABLE | 311 DDI_FM_ERRCB_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 312 DDI_FM_DMACHK_CAPABLE; 313 314 ddi_fm_init(devi, &ppb->ppb_fmcap, &ppb->ppb_fm_ibc); 315 mutex_init(&ppb->ppb_mutex, NULL, MUTEX_DRIVER, NULL); 316 mutex_init(&ppb->ppb_err_mutex, NULL, MUTEX_DRIVER, 317 (void *)ppb->ppb_fm_ibc); 318 mutex_init(&ppb->ppb_peek_poke_mutex, NULL, MUTEX_DRIVER, 319 (void *)ppb->ppb_fm_ibc); 320 321 if (ppb->ppb_fmcap & (DDI_FM_ERRCB_CAPABLE | 322 DDI_FM_EREPORT_CAPABLE)) 323 pci_ereport_setup(devi); 324 if (ppb->ppb_fmcap & DDI_FM_ERRCB_CAPABLE) 325 ddi_fm_handler_register(devi, ppb_fm_callback, NULL); 326 327 if (pci_config_setup(devi, &config_handle) != DDI_SUCCESS) { 328 if (ppb->ppb_fmcap & DDI_FM_ERRCB_CAPABLE) 329 ddi_fm_handler_unregister(devi); 330 if (ppb->ppb_fmcap & (DDI_FM_ERRCB_CAPABLE | 331 DDI_FM_EREPORT_CAPABLE)) 332 pci_ereport_teardown(devi); 333 ddi_fm_fini(devi); 334 ddi_soft_state_free(ppb_state, instance); 335 return (DDI_FAILURE); 336 } 337 338 ppb->parent_bus = PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO; 339 for (pdip = ddi_get_parent(devi); pdip && (pdip != root) && 340 (ppb->parent_bus != PCIE_PCIECAP_DEV_TYPE_PCIE_DEV); 341 pdip = ddi_get_parent(pdip)) { 342 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip, 343 DDI_PROP_DONTPASS, "device_type", &bus) != 344 DDI_PROP_SUCCESS) 345 break; 346 347 if (strcmp(bus, "pciex") == 0) 348 ppb->parent_bus = 349 PCIE_PCIECAP_DEV_TYPE_PCIE_DEV; 350 351 ddi_prop_free(bus); 352 } 353 354 if (ppb_support_ht_msimap == 1) 355 (void) ppb_ht_msimap_set(config_handle, 356 HT_MSIMAP_ENABLE); 357 else if (ppb_support_ht_msimap == -1) 358 (void) ppb_ht_msimap_set(config_handle, 359 HT_MSIMAP_DISABLE); 360 361 pci_config_teardown(&config_handle); 362 363 /* 364 * Initialize hotplug support on this bus. 365 */ 366 if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) 367 ret = pcie_init(devi, NULL); 368 else 369 ret = pcihp_init(devi); 370 371 if (ret != DDI_SUCCESS) { 372 cmn_err(CE_WARN, 373 "pci: Failed to setup hotplug framework"); 374 (void) ppb_detach(devi, DDI_DETACH); 375 return (ret); 376 } 377 378 ddi_report_dev(devi); 379 return (DDI_SUCCESS); 380 381 case DDI_RESUME: 382 383 /* 384 * Get the soft state structure for the bridge. 385 */ 386 ppb = ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 387 ppb_restore_config_regs(ppb); 388 return (DDI_SUCCESS); 389 390 default: 391 break; 392 } 393 return (DDI_FAILURE); 394 } 395 396 /*ARGSUSED*/ 397 static int 398 ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 399 { 400 ppb_devstate_t *ppb; 401 int ret; 402 403 switch (cmd) { 404 case DDI_DETACH: 405 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type"); 406 407 ppb = ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 408 if (ppb->ppb_fmcap & DDI_FM_ERRCB_CAPABLE) 409 ddi_fm_handler_unregister(devi); 410 if (ppb->ppb_fmcap & (DDI_FM_ERRCB_CAPABLE | 411 DDI_FM_EREPORT_CAPABLE)) 412 pci_ereport_teardown(devi); 413 414 /* 415 * Uninitialize hotplug support on this bus. 416 */ 417 ret = (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) ? 418 pcie_uninit(devi) : pcihp_uninit(devi); 419 if (ret != DDI_SUCCESS) 420 return (DDI_FAILURE); 421 422 mutex_destroy(&ppb->ppb_peek_poke_mutex); 423 mutex_destroy(&ppb->ppb_err_mutex); 424 mutex_destroy(&ppb->ppb_mutex); 425 ddi_fm_fini(devi); 426 427 /* 428 * And finally free the per-pci soft state. 429 */ 430 ddi_soft_state_free(ppb_state, ddi_get_instance(devi)); 431 432 return (DDI_SUCCESS); 433 434 case DDI_SUSPEND: 435 ppb = ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 436 ppb_save_config_regs(ppb); 437 return (DDI_SUCCESS); 438 439 default: 440 break; 441 } 442 return (DDI_FAILURE); 443 } 444 445 /*ARGSUSED*/ 446 static int 447 ppb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 448 off_t offset, off_t len, caddr_t *vaddrp) 449 { 450 dev_info_t *pdip; 451 452 pdip = (dev_info_t *)DEVI(dip)->devi_parent; 453 return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)(pdip, 454 rdip, mp, offset, len, vaddrp)); 455 } 456 457 /*ARGSUSED*/ 458 static int 459 ppb_ctlops(dev_info_t *dip, dev_info_t *rdip, 460 ddi_ctl_enum_t ctlop, void *arg, void *result) 461 { 462 pci_regspec_t *drv_regp; 463 int reglen; 464 int rn; 465 int totreg; 466 ppb_devstate_t *ppb = ddi_get_soft_state(ppb_state, 467 ddi_get_instance(dip)); 468 struct detachspec *dsp; 469 struct attachspec *asp; 470 471 switch (ctlop) { 472 case DDI_CTLOPS_REPORTDEV: 473 if (rdip == (dev_info_t *)0) 474 return (DDI_FAILURE); 475 cmn_err(CE_CONT, "?PCI-device: %s@%s, %s%d\n", 476 ddi_node_name(rdip), ddi_get_name_addr(rdip), 477 ddi_driver_name(rdip), 478 ddi_get_instance(rdip)); 479 return (DDI_SUCCESS); 480 481 case DDI_CTLOPS_INITCHILD: 482 return (ppb_initchild((dev_info_t *)arg)); 483 484 case DDI_CTLOPS_UNINITCHILD: 485 ppb_removechild((dev_info_t *)arg); 486 return (DDI_SUCCESS); 487 488 case DDI_CTLOPS_SIDDEV: 489 return (DDI_SUCCESS); 490 491 case DDI_CTLOPS_REGSIZE: 492 case DDI_CTLOPS_NREGS: 493 if (rdip == (dev_info_t *)0) 494 return (DDI_FAILURE); 495 break; 496 497 /* X86 systems support PME wakeup from suspend */ 498 case DDI_CTLOPS_ATTACH: 499 if (!pcie_is_child(dip, rdip)) 500 return (DDI_SUCCESS); 501 502 asp = (struct attachspec *)arg; 503 if ((ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) && 504 (asp->when == DDI_POST) && (asp->result == DDI_SUCCESS)) 505 pf_init(rdip, (void *)ppb->ppb_fm_ibc, asp->cmd); 506 507 if (asp->cmd == DDI_RESUME && asp->when == DDI_PRE) 508 if (pci_pre_resume(rdip) != DDI_SUCCESS) 509 return (DDI_FAILURE); 510 511 return (DDI_SUCCESS); 512 513 case DDI_CTLOPS_DETACH: 514 if (!pcie_is_child(dip, rdip)) 515 return (DDI_SUCCESS); 516 517 dsp = (struct detachspec *)arg; 518 if ((ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) && 519 (dsp->when == DDI_PRE)) 520 pf_fini(rdip, dsp->cmd); 521 522 if (dsp->cmd == DDI_SUSPEND && dsp->when == DDI_POST) 523 if (pci_post_suspend(rdip) != DDI_SUCCESS) 524 return (DDI_FAILURE); 525 526 return (DDI_SUCCESS); 527 528 case DDI_CTLOPS_PEEK: 529 case DDI_CTLOPS_POKE: 530 if (strcmp(ddi_driver_name(ddi_get_parent(dip)), "npe") != 0) 531 return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 532 return (pci_peekpoke_check(dip, rdip, ctlop, arg, result, 533 ddi_ctlops, &ppb->ppb_err_mutex, 534 &ppb->ppb_peek_poke_mutex, ppb_peekpoke_cb)); 535 536 default: 537 return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 538 } 539 540 *(int *)result = 0; 541 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, 542 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg", 543 (caddr_t)&drv_regp, ®len) != DDI_SUCCESS) 544 return (DDI_FAILURE); 545 546 totreg = reglen / sizeof (pci_regspec_t); 547 if (ctlop == DDI_CTLOPS_NREGS) 548 *(int *)result = totreg; 549 else if (ctlop == DDI_CTLOPS_REGSIZE) { 550 rn = *(int *)arg; 551 if (rn >= totreg) { 552 kmem_free(drv_regp, reglen); 553 return (DDI_FAILURE); 554 } 555 *(off_t *)result = drv_regp[rn].pci_size_low; 556 } 557 558 kmem_free(drv_regp, reglen); 559 return (DDI_SUCCESS); 560 } 561 562 static int 563 ppb_name_child(dev_info_t *child, char *name, int namelen) 564 { 565 pci_regspec_t *pci_rp; 566 uint_t slot, func; 567 char **unit_addr; 568 uint_t n; 569 570 /* 571 * For .conf nodes, use unit-address property as name 572 */ 573 if (ndi_dev_is_persistent_node(child) == 0) { 574 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child, 575 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) != 576 DDI_PROP_SUCCESS) { 577 cmn_err(CE_WARN, 578 "cannot find unit-address in %s.conf", 579 ddi_driver_name(child)); 580 return (DDI_FAILURE); 581 } 582 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) { 583 cmn_err(CE_WARN, "unit-address property in %s.conf" 584 " not well-formed", ddi_driver_name(child)); 585 ddi_prop_free(unit_addr); 586 return (DDI_SUCCESS); 587 } 588 (void) snprintf(name, namelen, "%s", *unit_addr); 589 ddi_prop_free(unit_addr); 590 return (DDI_SUCCESS); 591 } 592 593 /* get child "reg" property */ 594 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, 595 DDI_PROP_DONTPASS, "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) { 596 return (DDI_FAILURE); 597 } 598 599 /* copy the device identifications */ 600 slot = PCI_REG_DEV_G(pci_rp->pci_phys_hi); 601 func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); 602 603 if (func != 0) 604 (void) snprintf(name, namelen, "%x,%x", slot, func); 605 else 606 (void) snprintf(name, namelen, "%x", slot); 607 608 ddi_prop_free(pci_rp); 609 return (DDI_SUCCESS); 610 } 611 612 static int 613 ppb_initchild(dev_info_t *child) 614 { 615 struct ddi_parent_private_data *pdptr; 616 ppb_devstate_t *ppb; 617 char name[MAXNAMELEN]; 618 ddi_acc_handle_t config_handle; 619 ushort_t command_preserve, command; 620 621 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 622 ddi_get_instance(ddi_get_parent(child))); 623 624 if (ppb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS) 625 return (DDI_FAILURE); 626 ddi_set_name_addr(child, name); 627 628 /* 629 * Pseudo nodes indicate a prototype node with per-instance 630 * properties to be merged into the real h/w device node. 631 * The interpretation of the unit-address is DD[,F] 632 * where DD is the device id and F is the function. 633 */ 634 if (ndi_dev_is_persistent_node(child) == 0) { 635 extern int pci_allow_pseudo_children; 636 637 ddi_set_parent_data(child, NULL); 638 639 /* 640 * Try to merge the properties from this prototype 641 * node into real h/w nodes. 642 */ 643 if (ndi_merge_node(child, ppb_name_child) == DDI_SUCCESS) { 644 /* 645 * Merged ok - return failure to remove the node. 646 */ 647 ddi_set_name_addr(child, NULL); 648 return (DDI_FAILURE); 649 } 650 651 /* workaround for ddivs to run under PCI */ 652 if (pci_allow_pseudo_children) 653 return (DDI_SUCCESS); 654 655 /* 656 * The child was not merged into a h/w node, 657 * but there's not much we can do with it other 658 * than return failure to cause the node to be removed. 659 */ 660 cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged", 661 ddi_driver_name(child), ddi_get_name_addr(child), 662 ddi_driver_name(child)); 663 ddi_set_name_addr(child, NULL); 664 return (DDI_NOT_WELL_FORMED); 665 } 666 667 ddi_set_parent_data(child, NULL); 668 669 /* 670 * PCIe FMA specific 671 * 672 * Note: parent_data for parent is created only if this is PCI-E 673 * platform, for which, SG take a different route to handle device 674 * errors. 675 */ 676 if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) { 677 if (pcie_init_bus(child) == NULL) 678 return (DDI_FAILURE); 679 } 680 681 /* transfer select properties from PROM to kernel */ 682 if (ddi_getprop(DDI_DEV_T_NONE, child, DDI_PROP_DONTPASS, 683 "interrupts", -1) != -1) { 684 pdptr = kmem_zalloc((sizeof (struct ddi_parent_private_data) + 685 sizeof (struct intrspec)), KM_SLEEP); 686 pdptr->par_intr = (struct intrspec *)(pdptr + 1); 687 pdptr->par_nintr = 1; 688 ddi_set_parent_data(child, pdptr); 689 } else 690 ddi_set_parent_data(child, NULL); 691 692 if (pci_config_setup(child, &config_handle) != DDI_SUCCESS) 693 return (DDI_FAILURE); 694 695 /* 696 * Support for the "command-preserve" property. 697 */ 698 command_preserve = ddi_prop_get_int(DDI_DEV_T_ANY, child, 699 DDI_PROP_DONTPASS, "command-preserve", 0); 700 command = pci_config_get16(config_handle, PCI_CONF_COMM); 701 command &= (command_preserve | PCI_COMM_BACK2BACK_ENAB); 702 command |= (ppb_command_default & ~command_preserve); 703 pci_config_put16(config_handle, PCI_CONF_COMM, command); 704 705 pci_config_teardown(&config_handle); 706 return (DDI_SUCCESS); 707 } 708 709 static void 710 ppb_removechild(dev_info_t *dip) 711 { 712 struct ddi_parent_private_data *pdptr; 713 ppb_devstate_t *ppb; 714 715 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 716 ddi_get_instance(ddi_get_parent(dip))); 717 718 if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) 719 pcie_fini_bus(dip); 720 else if ((pdptr = ddi_get_parent_data(dip)) != NULL) { 721 kmem_free(pdptr, (sizeof (*pdptr) + sizeof (struct intrspec))); 722 ddi_set_parent_data(dip, NULL); 723 } 724 ddi_set_name_addr(dip, NULL); 725 726 /* 727 * Strip the node to properly convert it back to prototype form 728 */ 729 ddi_remove_minor_node(dip, NULL); 730 731 impl_rem_dev_props(dip); 732 } 733 734 /* 735 * ppb_save_config_regs 736 * 737 * This routine saves the state of the configuration registers of all 738 * the child nodes of each PBM. 739 * 740 * used by: ppb_detach() on suspends 741 * 742 * return value: none 743 */ 744 static void 745 ppb_save_config_regs(ppb_devstate_t *ppb_p) 746 { 747 int i; 748 dev_info_t *dip; 749 ddi_acc_handle_t config_handle; 750 751 for (i = 0, dip = ddi_get_child(ppb_p->dip); dip != NULL; 752 i++, dip = ddi_get_next_sibling(dip)) { 753 754 if (pci_config_setup(dip, &config_handle) != DDI_SUCCESS) { 755 cmn_err(CE_WARN, "%s%d: can't config space for %s%d\n", 756 ddi_driver_name(ppb_p->dip), 757 ddi_get_instance(ppb_p->dip), 758 ddi_driver_name(dip), 759 ddi_get_instance(dip)); 760 continue; 761 } 762 763 ppb_p->config_state[i].dip = dip; 764 ppb_p->config_state[i].command = 765 pci_config_get16(config_handle, PCI_CONF_COMM); 766 pci_config_teardown(&config_handle); 767 } 768 ppb_p->config_state_index = i; 769 } 770 771 772 /* 773 * ppb_restore_config_regs 774 * 775 * This routine restores the state of the configuration registers of all 776 * the child nodes of each PBM. 777 * 778 * used by: ppb_attach() on resume 779 * 780 * return value: none 781 */ 782 static void 783 ppb_restore_config_regs(ppb_devstate_t *ppb_p) 784 { 785 int i; 786 dev_info_t *dip; 787 ddi_acc_handle_t config_handle; 788 789 for (i = 0; i < ppb_p->config_state_index; i++) { 790 dip = ppb_p->config_state[i].dip; 791 if (pci_config_setup(dip, &config_handle) != DDI_SUCCESS) { 792 cmn_err(CE_WARN, "%s%d: can't config space for %s%d\n", 793 ddi_driver_name(ppb_p->dip), 794 ddi_get_instance(ppb_p->dip), 795 ddi_driver_name(dip), 796 ddi_get_instance(dip)); 797 continue; 798 } 799 pci_config_put16(config_handle, PCI_CONF_COMM, 800 ppb_p->config_state[i].command); 801 pci_config_teardown(&config_handle); 802 } 803 } 804 805 806 static boolean_t 807 ppb_ht_msimap_check(ddi_acc_handle_t cfg_hdl) 808 { 809 uint16_t ptr; 810 811 if (pci_htcap_locate(cfg_hdl, 812 PCI_HTCAP_TYPE_MASK | PCI_HTCAP_MSIMAP_ENABLE_MASK, 813 PCI_HTCAP_MSIMAP_TYPE | PCI_HTCAP_MSIMAP_ENABLE, &ptr) != 814 DDI_SUCCESS) 815 return (B_FALSE); 816 817 return (B_TRUE); 818 } 819 820 821 static int 822 ppb_ht_msimap_set(ddi_acc_handle_t cfg_hdl, int cmd) 823 { 824 uint16_t ptr; 825 uint16_t reg; 826 827 if (pci_htcap_locate(cfg_hdl, PCI_HTCAP_TYPE_MASK, 828 PCI_HTCAP_MSIMAP_TYPE, &ptr) != DDI_SUCCESS) 829 return (0); 830 831 reg = pci_config_get16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF); 832 switch (cmd) { 833 case HT_MSIMAP_ENABLE: 834 reg |= PCI_HTCAP_MSIMAP_ENABLE; 835 break; 836 case HT_MSIMAP_DISABLE: 837 default: 838 reg &= ~(uint16_t)PCI_HTCAP_MSIMAP_ENABLE; 839 } 840 841 pci_config_put16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF, reg); 842 return (1); 843 } 844 845 846 /* 847 * intercept certain interrupt services to handle special cases 848 */ 849 static int 850 ppb_intr_ops(dev_info_t *pdip, dev_info_t *rdip, ddi_intr_op_t intr_op, 851 ddi_intr_handle_impl_t *hdlp, void *result) 852 { 853 ddi_acc_handle_t cfg_hdl; 854 int rv = DDI_SUCCESS; 855 856 if (intr_op != DDI_INTROP_SUPPORTED_TYPES) 857 return (i_ddi_intr_ops(pdip, rdip, intr_op, hdlp, result)); 858 859 DDI_INTR_NEXDBG((CE_CONT, 860 "ppb_intr_ops: pdip 0x%p, rdip 0x%p, op %x handle 0x%p\n", 861 (void *)pdip, (void *)rdip, intr_op, (void *)hdlp)); 862 863 /* Fixed interrupt is supported by default */ 864 *(int *)result = DDI_INTR_TYPE_FIXED; 865 866 if (ppb_support_msi == -1) { 867 DDI_INTR_NEXDBG((CE_CONT, 868 "ppb_intr_ops: MSI is not allowed\n")); 869 goto OUT; 870 } 871 872 if (ppb_support_msi == 1) { 873 DDI_INTR_NEXDBG((CE_CONT, 874 "ppb_intr_ops: MSI is always allowed\n")); 875 rv = i_ddi_intr_ops(pdip, rdip, intr_op, hdlp, result); 876 goto OUT; 877 } 878 879 if (pci_config_setup(pdip, &cfg_hdl) != DDI_SUCCESS) { 880 DDI_INTR_NEXDBG((CE_CONT, 881 "ppb_intr_ops: pci_config_setup() failed\n")); 882 goto OUT; 883 } 884 885 /* 886 * check for hypertransport msi mapping capability 887 */ 888 if (ppb_ht_msimap_check(cfg_hdl)) { 889 DDI_INTR_NEXDBG((CE_CONT, 890 "ppb_intr_ops: HT MSI mapping enabled\n")); 891 rv = i_ddi_intr_ops(pdip, rdip, intr_op, hdlp, result); 892 } 893 894 /* 895 * if we add failure conditions after pci_config_setup, move this to 896 * OUT and use an extra flag to indicate the need to teardown cfg_hdl 897 */ 898 pci_config_teardown(&cfg_hdl); 899 900 OUT: 901 DDI_INTR_NEXDBG((CE_CONT, 902 "ppb_intr_ops: rdip 0x%p, returns supported types: 0x%x\n", 903 (void *)rdip, *(int *)result)); 904 return (rv); 905 } 906 907 /* ARGSUSED */ 908 static int 909 ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp) 910 { 911 int instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(*devp)); 912 ppb_devstate_t *ppb_p = ddi_get_soft_state(ppb_state, instance); 913 int rv; 914 915 if (ppb_p == NULL) 916 return (ENXIO); 917 918 /* 919 * Ioctls will be handled by PCI Express framework for all 920 * PCIe platforms 921 */ 922 if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) { 923 mutex_enter(&ppb_p->ppb_mutex); 924 rv = pcie_open(ppb_p->dip, devp, flags, otyp, credp); 925 mutex_exit(&ppb_p->ppb_mutex); 926 return (rv); 927 } 928 929 return ((pcihp_get_cb_ops())->cb_open(devp, flags, otyp, credp)); 930 } 931 932 /* ARGSUSED */ 933 static int 934 ppb_close(dev_t dev, int flags, int otyp, cred_t *credp) 935 { 936 int instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev)); 937 ppb_devstate_t *ppb_p = ddi_get_soft_state(ppb_state, instance); 938 int rv; 939 940 if (ppb_p == NULL) 941 return (ENXIO); 942 943 mutex_enter(&ppb_p->ppb_mutex); 944 /* 945 * Ioctls will be handled by PCI Express framework for all 946 * PCIe platforms 947 */ 948 if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) { 949 rv = pcie_close(ppb_p->dip, dev, flags, otyp, credp); 950 mutex_exit(&ppb_p->ppb_mutex); 951 return (rv); 952 } 953 954 mutex_exit(&ppb_p->ppb_mutex); 955 return ((pcihp_get_cb_ops())->cb_close(dev, flags, otyp, credp)); 956 } 957 958 /* 959 * ppb_ioctl: devctl hotplug controls 960 */ 961 /* ARGSUSED */ 962 static int 963 ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 964 int *rvalp) 965 { 966 int instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev)); 967 ppb_devstate_t *ppb_p = ddi_get_soft_state(ppb_state, instance); 968 969 if (ppb_p == NULL) 970 return (ENXIO); 971 972 /* 973 * Ioctls will be handled by PCI Express framework for all 974 * PCIe platforms 975 */ 976 if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) 977 return (pcie_ioctl(ppb_p->dip, dev, cmd, arg, mode, credp, 978 rvalp)); 979 980 return ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd, arg, mode, credp, 981 rvalp)); 982 } 983 984 static int 985 ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, int flags, 986 char *name, caddr_t valuep, int *lengthp) 987 { 988 int instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev)); 989 ppb_devstate_t *ppb_p = ddi_get_soft_state(ppb_state, instance); 990 991 if (ppb_p == NULL) 992 return (ENXIO); 993 994 if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) 995 return (pcie_prop_op(dev, dip, prop_op, flags, name, 996 valuep, lengthp)); 997 998 return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op, flags, 999 name, valuep, lengthp)); 1000 } 1001 1002 static int 1003 ppb_info(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result) 1004 { 1005 minor_t minor = getminor((dev_t)arg); 1006 int instance = PCI_MINOR_NUM_TO_INSTANCE(minor); 1007 ppb_devstate_t *ppb_p = ddi_get_soft_state(ppb_state, instance); 1008 1009 if (ppb_p == NULL) 1010 return (DDI_FAILURE); 1011 1012 if (ppb_p->parent_bus != PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) 1013 return (pcihp_info(dip, cmd, arg, result)); 1014 1015 switch (cmd) { 1016 default: 1017 return (DDI_FAILURE); 1018 1019 case DDI_INFO_DEVT2INSTANCE: 1020 *result = (void *)(uintptr_t)instance; 1021 return (DDI_SUCCESS); 1022 1023 case DDI_INFO_DEVT2DEVINFO: 1024 if (ppb_p == NULL) 1025 return (DDI_FAILURE); 1026 *result = (void *)ppb_p->dip; 1027 return (DDI_SUCCESS); 1028 } 1029 } 1030 1031 void ppb_peekpoke_cb(dev_info_t *dip, ddi_fm_error_t *derr) { 1032 (void) pci_ereport_post(dip, derr, NULL); 1033 } 1034 1035 /*ARGSUSED*/ 1036 static int 1037 ppb_fm_init(dev_info_t *dip, dev_info_t *tdip, int cap, 1038 ddi_iblock_cookie_t *ibc) 1039 { 1040 ppb_devstate_t *ppb = ddi_get_soft_state(ppb_state, 1041 ddi_get_instance(dip)); 1042 1043 ASSERT(ibc != NULL); 1044 *ibc = ppb->ppb_fm_ibc; 1045 1046 return (ppb->ppb_fmcap); 1047 } 1048 1049 /*ARGSUSED*/ 1050 static int 1051 ppb_fm_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *no_used) 1052 { 1053 ppb_devstate_t *ppb = ddi_get_soft_state(ppb_state, 1054 ddi_get_instance(dip)); 1055 1056 mutex_enter(&ppb->ppb_err_mutex); 1057 pci_ereport_post(dip, derr, NULL); 1058 mutex_exit(&ppb->ppb_err_mutex); 1059 return (derr->fme_status); 1060 } 1061
Indexes created Sun Nov 22 02:52:53 UTC 2009
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