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      1 /*
      2  * CDDL HEADER START
      3  *
      4  * The contents of this file are subject to the terms of the
      5  * Common Development and Distribution License (the "License").
      6  * You may not use this file except in compliance with the License.
      7  *
      8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
      9  * or http://www.opensolaris.org/os/licensing.
     10  * See the License for the specific language governing permissions
     11  * and limitations under the License.
     12  *
     13  * When distributing Covered Code, include this CDDL HEADER in each
     14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
     15  * If applicable, add the following below this CDDL HEADER, with the
     16  * fields enclosed by brackets "[]" replaced with your own identifying
     17  * information: Portions Copyright [yyyy] [name of copyright owner]
     18  *
     19  * CDDL HEADER END
     20  */
     21 
     22 /*
     23  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
     24  * Use is subject to license terms.
     25  */
     26 
     27 #ifndef _INTEL_NHM_H
     28 #define	_INTEL_NHM_H
     29 
     30 #ifdef __cplusplus
     31 extern "C" {
     32 #endif
     33 
     34 #define	NHM_EP_CPU	0x2c408086
     35 #define	NHM_WS_CPU	0x2c418086
     36 #define	NHM_CPU_RAS	0x2c1a8086
     37 #define	NHM_JF_CPU	0x2c588086
     38 #define	NHM_JF_CPU_RAS	0x2cda8086
     39 #define	NHM_WM_CPU	0x2c708086
     40 #define	NHM_WM_CPU_RAS	0x2d9a8086
     41 
     42 #define	NHM_INTERCONNECT	"Intel QuickPath"
     43 
     44 #define	MAX_CPU_NODES	2
     45 #define	CPU_PCI_DEVS	6
     46 #define	CPU_PCI_FUNCS	6
     47 
     48 #define	MAX_BUS_NUMBER	max_bus_number
     49 
     50 #define	SOCKET_BUS(cpu) (MAX_BUS_NUMBER - (cpu))
     51 #define	CPU_ID_RD(cpu)  nhm_pci_getl(SOCKET_BUS(cpu), 0, 0, 0, 0)
     52 #define	MC_CONTROL_RD(cpu) \
     53     nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x48, 0)
     54 #define	MC_STATUS_RD(cpu) \
     55     nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x4c, 0)
     56 #define	MC_SMI_SPARE_DIMM_ERROR_STATUS_RD(cpu) \
     57     nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x50, 0)
     58 #define	MC_CPU_RAS_RD(cpu) \
     59     nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0, 0)
     60 #define	MC_SCRUB_CONTROL_RD(cpu) \
     61     nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x4c, 0)
     62 #define	MC_SCRUB_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, \
     63     0x4c, reg);
     64 #define	MC_SSR_CONTROL_RD(cpu)	nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x48, 0)
     65 #define	MC_SSR_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, 0x48, \
     66     reg);
     67 #define	MC_SSR_SCRUB_CONTROL_RD(cpu)	nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, \
     68     0x4c, 0)
     69 #define	MC_RAS_ENABLES_RD(cpu)	nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x50, 0)
     70 #define	MC_RAS_STATUS_RD(cpu)	nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x54, 0)
     71 #define	MC_SSR_STATUS_RD(cpu)	nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x60, 0)
     72 #define	MC_CHANNEL_MAPPER_RD(cpu)	nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, \
     73     0x60, 0)
     74 #define	MC_COR_ECC_CNT_RD(cpu, select) \
     75     nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x80 + ((select) * 4), 0)
     76 #define	MC_CHANNEL_RANK_PRESENT_RD(cpu, channel) \
     77     nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x7c, 0)
     78 #define	MC_DOD_RD(cpu, channel, select) \
     79     nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x48 + ((select) * 4), 0)
     80 #define	MC_SAG_RD(cpu, channel, select) \
     81     nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x80 + ((select) * 4), 0)
     82 #define	MC_RIR_LIMIT_RD(cpu, channel, select) \
     83     nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x40 + ((select) * 4), 0)
     84 #define	MC_RIR_WAY_RD(cpu, channel, select) \
     85     nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x80 + ((select) * 4), 0)
     86 #define	MC_CHANNEL_DIMM_INIT_PARAMS_RD(cpu, channel) \
     87     nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x58, 0)
     88 #define	SAD_DRAM_RULE_RD(cpu, rule) \
     89     nhm_pci_getl(SOCKET_BUS(cpu), 0, 1, 0x80 + (4 * (rule)), 0)
     90 #define	SAD_INTERLEAVE_LIST_RD(cpu, rule) \
     91     nhm_pci_getl(SOCKET_BUS(cpu), 0, 1, 0xc0 + (4 * (rule)), 0)
     92 #define	TAD_DRAM_RULE_RD(cpu, rule) \
     93     nhm_pci_getl(SOCKET_BUS(cpu), 3, 1, 0x80 + (4 * (rule)), 0)
     94 #define	TAD_INTERLEAVE_LIST_RD(cpu, rule) \
     95     nhm_pci_getl(SOCKET_BUS(cpu), 3, 1, 0xc0 + (4 * (rule)), 0)
     96 #define	MC_DIMM_CLK_RATIO_STATUS(cpu) \
     97     nhm_pci_getl(SOCKET_BUS(cpu), 3, 4, 0x50, 0)
     98 
     99 /*
    100  * MC_CONTROL
    101  */
    102 #define	MC_CONTROL_CHANNEL_ACTIVE(reg, channel) \
    103 	((reg) & (1 << (8 + (channel))) != 0)
    104 #define	MC_CONTROL_ECCEN(reg) (((reg) >> 1) & 1)
    105 #define	MC_CONTROL_CLOSED_PAGE(reg) ((reg) & 1)
    106 #define	MC_CONTROL_DIVBY3(reg) ((reg >> 6) &1)
    107 
    108 #define	NUM_CACHELINE_BITS	6	/* Cachelines are 64B */
    109 
    110 /*
    111  * MC_STATUS
    112  */
    113 #define	CHANNEL_DISABLED(reg, channel) ((reg) & (1 << (channel)))
    114 #define	WS_ECC_ENABLED	0x10
    115 /*
    116  * MC_CHANNEL_DIMM_INIT_PARAMS
    117  */
    118 #define	THREE_DIMMS_PRESENT		(1 << 24) /* not quad rank */
    119 #define	SINGLE_QUAD_RANK_PRESENT	(1 << 23)
    120 #define	QUAD_RANK_PRESENT		(1 << 22) /* 1 or 2 quad rank dimms */
    121 #define	REGISTERED_DIMM			(1 << 15)
    122 
    123 /*
    124  * MC_DOD_CH
    125  */
    126 #define	RANKOFFSET(reg)	(((reg) >> 10) & 7)
    127 #define	DIMMPRESENT(reg) (((reg) & (1 << 9)) != 0)
    128 #define	NUMBANK(reg) (((reg) & (3 << 7)) == 0 ? 4 : (((reg) >> 7) & 3) * 8)
    129 #define	NUMRANK(reg) (((reg) & (3 << 5)) == 0 ? 1 : (((reg) >> 5) & 3) * 2)
    130 #define	NUMROW(reg) ((((reg) >> 2) & 7) + 12)
    131 #define	NUMCOL(reg) (((reg) & 3) + 10)
    132 #define	DIMMWIDTH	8
    133 #define	DIMMSIZE(reg) ((1ULL << (NUMCOL(reg) + NUMROW(reg))) * NUMRANK(reg) \
    134 	* NUMBANK(reg) * DIMMWIDTH)
    135 
    136 /*
    137  * MC_SAG_CH
    138  */
    139 #define	DIVBY3(reg)	(((reg) >> 27) & 1)	/* 3 or 6 way interleave */
    140 #define	REMOVE_6(reg)	(((reg) >> 24) & 1)
    141 #define	REMOVE_7(reg)	(((reg) >> 25) & 1)
    142 #define	REMOVE_8(reg)	(((reg) >> 26) & 1)
    143 #define	CH_ADDRESS_OFFSET(reg) \
    144 	(int64_t)((uint64_t)(reg) & 0x00ffffff)
    145 #define	CH_ADDRESS_SOFFSET(reg) \
    146 	((int64_t)(((uint64_t)(reg) & 0x00ffffff) << 40) >>40)
    147 /* SAG offset covers SA[39:16] so granularity is 2^16 = 64KB */
    148 #define	SAG_OFFSET_GRANULARITY	16
    149 /* 24-bit mask for TTMAD_CR_SAG_CH*.OFFSET */
    150 #define	SAG_OFFSET_SIZE_MASK	0xffffffULL
    151 /* 16-bit mask for lower bits not covered by CREG value (SA[15:0]) */
    152 #define	SAG_OFFSET_ADDR_MASK	0xffffULL
    153 #define	CACHELINE_ADDR_MASK	0x3fULL	/* 6-bit mask */
    154 
    155 /*
    156  * MC_RIR_LIMIT_CH
    157  */
    158 #define	RIR_LIMIT(reg)	((((uint64_t)(reg) & 0x000003ff) + 1) << 28)
    159 /*
    160  * MC_RIR_WAY_CH
    161  */
    162 #define	RIR_OFFSET(reg)	(int64_t)((uint64_t)(reg >> 4)& 0x3ff)
    163 #define	RIR_SOFFSET(reg)	((int64_t)(((uint64_t)(reg) & 0x3ff0) << 50) \
    164 				    >> 54)
    165 #define	RIR_DIMM_RANK(reg)	((reg) & 0xf)
    166 #define	RIR_RANK(reg)	((reg) & 0x3)
    167 #define	RIR_DIMM(reg)	((reg)>>2 & 0x03)
    168 #define	RIR_OFFSET_SIZE_MASK	0x3ff
    169 
    170 #define	MAX_RIR_WAY 4
    171 
    172 #define	RIR_LIMIT_GRANULARITY	28
    173 #define	RIR_OFFSET_ADDR_MASK	0xfffffffULL	/* 28-bit mask */
    174 #define	RIR_INTLV_PGOPEN_BIT	12	/* Rank interleaving */
    175 #define	RIR_INTLV_PGOPEN_MASK	0xfffULL	/* 12-bit mask */
    176 #define	RIR_INTLV_PGCLS_BIT	6	/* Rank interleaving */
    177 #define	RIR_INTLV_PGCLS_MASK	0x3fULL	/* 6-bit mask */
    178 #define	RIR_INTLV_SIZE_MASK	0x3ULL
    179 /*
    180  * MC_RAS_ENABLES
    181  */
    182 #define	RAS_LOCKSTEP_ENABLE(reg) (((reg) & 2) != 0)
    183 #define	RAS_MIRROR_MEM_ENABLE(reg) (((reg) & 1) != 0)
    184 /*
    185  * MC_RAS_STATUS
    186  */
    187 #define	REDUNDANCY_LOSS(reg) (((reg) & 1) != 0)
    188 /*
    189  * MC_SSRSTATUS
    190  */
    191 #define	SPAREING_IN_PROGRESS(reg) (((reg) & 2) != 0)
    192 #define	SPAREING_COMPLETE(reg) (((reg) & 1) != 0)
    193 
    194 /*
    195  * MC_SSR_CONTROL
    196  */
    197 #define	SSR_MODE(reg) ((reg) & 3)
    198 #define	SSR_IDLE	0
    199 #define	SSR_SCRUB	1
    200 #define	SSR_SPARE	2
    201 #define	DEMAND_SCRUB_ENABLE	(1 << 6)
    202 /*
    203  * MC_SCRUB_CONTROL
    204  */
    205 #define	STARTSCRUB	(1 << 24)
    206 /*
    207  * MC_DIMM_CLK_RATIO_STATUS
    208  */
    209 #define	MAX_DIMM_CLK_RATIO(reg) (((reg) >> 24) & 0x1f)
    210 /*
    211  * MC_SMI_SPARE_DIMM_ERROR_STATUS_RD
    212  */
    213 #define	REDUNDANCY_LOSS_FAILING_DIMM(status) (((status) >> 12) & 3)
    214 #define	DIMM_ERROR_OVERFLOW_STATUS(status) ((status) & 0xfff)
    215 
    216 #define	MAX_MEMORY_CONTROLLERS	MAX_CPU_NODES
    217 #define	CHANNELS_PER_MEMORY_CONTROLLER	3
    218 #define	MAX_DIMMS_PER_CHANNEL	3
    219 
    220 /*
    221  * SAD_DRAM_RULE
    222  */
    223 #define	SAD_DRAM_LIMIT(sad) ((((uint64_t)(sad) & 0x000fffc0ULL) + 0x40) << 20)
    224 #define	SAD_DRAM_MODE(sad) (((sad) >> 1) & 3)
    225 #define	SAD_DRAM_RULE_ENABLE(sad) ((sad) & 1)
    226 
    227 /*
    228  * from SAD_DRAM_RULE*.MODE
    229  */
    230 #define	DIRECT	0
    231 #define	XOR	1
    232 #define	MOD3	2
    233 #define	SAD_INTERLEAVE(list, num)	(((list) >> ((num) * 4)) & 0x3)
    234 #define	INTERLEAVE_NWAY	8
    235 #define	MAX_SAD_DRAM_RULE	8
    236 
    237 #define	SAD_LIMIT_GRANULARITY	26
    238 #define	SAD_LIMIT_ADDR_MASK	0x3ffffffULL
    239 #define	SAD_INTLV_DIRECT_BIT	6
    240 #define	SAD_INTLV_XOR_BIT	16
    241 #define	SAD_INTLV_SIZE_MASK	0x7ULL
    242 #define	SAD_INTLV_ADDR_MASK	0x3fULL
    243 
    244 /*
    245  * TAD_DRAM_RULE
    246  */
    247 #define	TAD_DRAM_LIMIT(tad) ((((uint64_t)(tad) & 0x000fffc0ULL) + 0x40) << 20)
    248 #define	TAD_DRAM_MODE(tad) (((tad) >> 1) & 3)
    249 #define	TAD_DRAM_RULE_ENABLE(tad) ((tad) & 1)
    250 
    251 #define	TAD_INTERLEAVE(list, channel) (((list) >> ((channel) * 4)) & 3)
    252 
    253 #define	MAX_TAD_DRAM_RULE 8
    254 
    255 #define	VRANK_SZ 0x10000000
    256 
    257 typedef struct sad {
    258 	uint64_t limit;
    259 	uint32_t node_list;
    260 	uint32_t node_tgt[INTERLEAVE_NWAY];
    261 	char mode;
    262 	char enable;
    263 	char interleave;
    264 } sad_t;
    265 
    266 typedef struct tad {
    267 	uint64_t limit;
    268 	uint32_t pkg_list;
    269 	uint32_t pkg_tgt[INTERLEAVE_NWAY];
    270 	char mode;
    271 	char enable;
    272 	char interleave;
    273 } tad_t;
    274 
    275 typedef struct sag_ch {
    276 	uint32_t offset;
    277 	int32_t soffset;
    278 	char divby3;
    279 	char remove6;
    280 	char remove7;
    281 	char remove8;
    282 } sag_ch_t;
    283 
    284 typedef struct rir_way {
    285 	uint16_t offset;
    286 	int16_t soffset;
    287 	uint8_t	rank;
    288 	uint8_t dimm;
    289 	uint8_t dimm_rank;
    290 	uint64_t rlimit;
    291 } way_t;
    292 
    293 typedef struct rir {
    294 	uint64_t limit;
    295 	way_t way[MAX_RIR_WAY];
    296 	char interleave;
    297 } rir_t;
    298 
    299 typedef struct dod_type {
    300 	int NUMCol;
    301 	int NUMRow;
    302 	int NUMRank;
    303 	int NUMBank;
    304 	int DIMMPresent;
    305 	int RankOffset;
    306 } dod_t;
    307 
    308 /*
    309  * MC_CHANNEL_MAPPER
    310  */
    311 #define	CHANNEL_MAP(reg, channel, write) (((reg) >> ((channel) * 6 + \
    312 	((write) ? 0 : 3))) & 7)
    313 
    314 extern int max_bus_number;
    315 
    316 #ifdef __cplusplus
    317 }
    318 #endif
    319 
    320 #endif /* _INTEL_NHM_H */
    321