1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _ATA_COMMON_H 28 #define _ATA_COMMON_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/varargs.h> 35 36 #include <sys/scsi/scsi.h> 37 #include <sys/dktp/dadkio.h> 38 #include <sys/dktp/dadev.h> 39 #include <sys/dkio.h> 40 #include <sys/dktp/tgdk.h> 41 42 #include <sys/ddi.h> 43 #include <sys/sunddi.h> 44 45 #include "ghd.h" 46 47 #include "pciide.h" 48 #include "ata_cmd.h" 49 #include "ata_fsm.h" 50 #include "ata_debug.h" 51 52 53 /* 54 * device types 55 */ 56 #define ATA_DEV_NONE 0 57 #define ATA_DEV_DISK 1 58 #define ATA_DEV_ATAPI 2 59 60 /* 61 * Largest sector allowed in 28 bit mode 62 */ 63 #define MAX_28BIT_CAPACITY 0xfffffff 64 65 /* 66 * Largest sector count allowed for device firmware file in one command. 67 */ 68 #define MAX_FWFILE_SIZE_ONECMD 0xffff 69 70 /* 71 * ata-options property configuration bits 72 */ 73 74 #define ATA_OPTIONS_DMA 0x01 75 76 #define ATAPRT(fmt) ghd_err fmt 77 78 /* ad_flags (per-drive) */ 79 80 #define AD_ATAPI 0x01 /* is an ATAPI drive */ 81 #define AD_DISK 0x02 82 #define AD_MUTEX_INIT 0x04 83 #define AD_NO_CDB_INTR 0x20 84 #define AD_1SECTOR 0x40 85 #define AD_INT13LBA 0x80 /* supports LBA at Int13 interface */ 86 #define AD_NORVRT 0x100 /* block revert-to-defaults */ 87 #define AD_EXT48 0x200 /* 48 bit (extended) LBA */ 88 #define AD_BLLBA48 0x400 89 #define ATAPIDRV(X) ((X)->ad_flags & AD_ATAPI) 90 91 92 /* max targets and luns */ 93 94 #define ATA_MAXTARG 2 95 #define ATA_MAXLUN 16 96 97 /* 98 * PCI-IDE Bus Mastering Scatter/Gather list size 99 */ 100 #define ATA_DMA_NSEGS 17 /* enough for at least 64K */ 101 102 /* 103 * Controller port address defaults 104 */ 105 #define ATA_BASE0 0x1f0 106 #define ATA_BASE1 0x170 107 108 /* 109 * port offsets from base address ioaddr1 110 */ 111 #define AT_DATA 0x00 /* data register */ 112 #define AT_ERROR 0x01 /* error register (read) */ 113 #define AT_FEATURE 0x01 /* features (write) */ 114 #define AT_COUNT 0x02 /* sector count */ 115 #define AT_SECT 0x03 /* sector number */ 116 #define AT_LCYL 0x04 /* cylinder low byte */ 117 #define AT_HCYL 0x05 /* cylinder high byte */ 118 #define AT_DRVHD 0x06 /* drive/head register */ 119 #define AT_STATUS 0x07 /* status/command register */ 120 #define AT_CMD 0x07 /* status/command register */ 121 122 /* 123 * port offsets from base address ioaddr2 124 */ 125 #define AT_ALTSTATUS 0x00 /* alternate status (read) */ 126 #define AT_DEVCTL 0x00 /* device control (write) */ 127 128 /* Device control register */ 129 #define ATDC_NIEN 0x02 /* disable interrupts */ 130 #define ATDC_SRST 0x04 /* controller reset */ 131 #define ATDC_D3 0x08 /* Mysterious bit, must be set */ 132 /* 133 * ATA-6 spec 134 * In 48-bit addressing, reading the LBA location and count 135 * registers when the high-order bit is set reads the "previous 136 * content" (LBA bits 47:24, count bits 15:8) instead of the 137 * "most recent" values (LBA bits 23:0, count bits 7:0). 138 */ 139 #define ATDC_HOB 0x80 /* High order bit */ 140 141 /* 142 * Status bits from AT_STATUS register 143 */ 144 #define ATS_BSY 0x80 /* controller busy */ 145 #define ATS_DRDY 0x40 /* drive ready */ 146 #define ATS_DF 0x20 /* device fault */ 147 #define ATS_DSC 0x10 /* seek operation complete */ 148 #define ATS_DRQ 0x08 /* data request */ 149 #define ATS_CORR 0x04 /* ECC correction applied */ 150 #define ATS_IDX 0x02 /* disk revolution index */ 151 #define ATS_ERR 0x01 /* error flag */ 152 153 /* 154 * Status bits from AT_ERROR register 155 */ 156 #define ATE_BBK_ICRC 0x80 /* bad block detected in ATA-1 */ 157 /* ICRC error in ATA-4 and newer */ 158 #define ATE_UNC 0x40 /* uncorrectable data error */ 159 #define ATE_MC 0x20 /* Media change */ 160 #define ATE_IDNF 0x10 /* ID not found */ 161 #define ATE_MCR 0x08 /* media change request */ 162 #define ATE_ABORT 0x04 /* aborted command */ 163 #define ATE_TKONF 0x02 /* track 0 not found */ 164 #define ATE_AMNF 0x01 /* address mark not found */ 165 166 #define ATE_NM 0x02 /* no media */ 167 168 /* 169 * Drive selectors for AT_DRVHD register 170 */ 171 #define ATDH_LBA 0x40 /* addressing in LBA mode not chs */ 172 #define ATDH_DRIVE0 0xa0 /* or into AT_DRVHD to select drive 0 */ 173 #define ATDH_DRIVE1 0xb0 /* or into AT_DRVHD to select drive 1 */ 174 175 /* 176 * Feature register bits 177 */ 178 #define ATF_ATAPI_DMA 0x01 /* ATAPI DMA enable bit */ 179 #define ATF_XFRMOD_MDMA 0x20 /* Multi-Word DMA mode */ 180 #define ATF_XFRMOD_UDMA 0x40 /* Ultra DMA mode */ 181 #define ATACM_UDMA_SEL(id) (((id)->ai_ultradma >> 8) & 0x7f) 182 183 /* 184 * Set feature register definitions. 185 */ 186 #define ATSF_SET_XFRMOD 0X03 /* Set transfer mode */ 187 #define ATSF_DIS_REVPOD 0x66 /* Disable reverting to power on defaults */ 188 #define ATSF_ENA_REVPOD 0xcc /* Enable reverting to power on defaults */ 189 190 /* 191 * common bits and options for set features (ATC_SET_FEAT) 192 */ 193 #define FC_WRITE_CACHE_ON 0x02 194 #define FC_WRITE_CACHE_OFF 0x82 195 196 /* Test which version of ATA is supported */ 197 #define IS_ATA_VERSION_SUPPORTED(idp, n) \ 198 ((idp->ai_majorversion != 0xffff) && \ 199 (idp->ai_majorversion & (1<<n))) 200 201 /* Test if supported version >= ATA-n */ 202 #define IS_ATA_VERSION_GE(idp, n) \ 203 ((idp->ai_majorversion != 0xffff) && \ 204 (idp->ai_majorversion != 0) && \ 205 (idp->ai_majorversion >= (1<<n))) 206 207 /* Test whether a device is a CD drive */ 208 #define IS_CDROM(dp) \ 209 ((dp->ad_flags & AD_ATAPI) && \ 210 ((dp->ad_id.ai_config >> 8) & DTYPE_MASK) == \ 211 DTYPE_RODIRECT) 212 213 /* Test whether the device support write cache */ 214 #define IS_WRITE_CACHE_SUPPORTED(x) \ 215 ((((x).ai_cmdset82) & 0x20) >> 5) 216 217 /* macros from old common hba code */ 218 219 #define ATA_INTPROP(devi, pname, pval, plen) \ 220 (ddi_prop_op(DDI_DEV_T_ANY, (devi), PROP_LEN_AND_VAL_BUF, \ 221 DDI_PROP_DONTPASS, (pname), (caddr_t)(pval), (plen))) 222 223 #define ATA_LONGPROP(devi, pname, pval, plen) \ 224 (ddi_getlongprop(DDI_DEV_T_ANY, (devi), DDI_PROP_DONTPASS, \ 225 (pname), (caddr_t)(pval), (plen))) 226 227 /* 228 * 229 * per-controller soft-state data structure 230 * 231 */ 232 233 #define CTL2DRV(cp, t, l) (cp->ac_drvp[t][l]) 234 235 typedef struct ata_ctl { 236 237 dev_info_t *ac_dip; 238 uint_t ac_flags; 239 uint_t ac_timing_flags; 240 struct ata_drv *ac_drvp[ATA_MAXTARG][ATA_MAXLUN]; 241 int ac_max_transfer; /* max transfer in sectors */ 242 uint_t ac_standby_time; /* timer value seconds */ 243 244 ccc_t ac_ccc; /* for GHD module */ 245 struct ata_drv *ac_active_drvp; /* active drive, if any */ 246 struct ata_pkt *ac_active_pktp; /* active packet, if any */ 247 uchar_t ac_state; 248 249 scsi_hba_tran_t *ac_atapi_tran; /* for atapi module */ 250 251 /* 252 * port addresses associated with ioaddr1 253 */ 254 ddi_acc_handle_t ac_iohandle1; /* DDI I/O handle */ 255 caddr_t ac_ioaddr1; 256 ushort_t *ac_data; /* data register */ 257 uchar_t *ac_error; /* error register (read) */ 258 uchar_t *ac_feature; /* features (write) */ 259 uchar_t *ac_count; /* sector count */ 260 uchar_t *ac_sect; /* sector number */ 261 uchar_t *ac_lcyl; /* cylinder low byte */ 262 uchar_t *ac_hcyl; /* cylinder high byte */ 263 uchar_t *ac_drvhd; /* drive/head register */ 264 uchar_t *ac_status; /* status/command register */ 265 uchar_t *ac_cmd; /* status/command register */ 266 267 /* 268 * port addresses associated with ioaddr2 269 */ 270 ddi_acc_handle_t ac_iohandle2; /* DDI I/O handle */ 271 caddr_t ac_ioaddr2; 272 uchar_t *ac_altstatus; /* alternate status (read) */ 273 uchar_t *ac_devctl; /* device control (write) */ 274 275 /* 276 * handle and port addresss for PCI-IDE Bus Master controller 277 */ 278 ddi_acc_handle_t ac_bmhandle; /* DDI I/O handle */ 279 caddr_t ac_bmaddr; /* base addr of Bus Master Regs */ 280 uchar_t ac_pciide; /* PCI-IDE device */ 281 uchar_t ac_pciide_bm; /* Bus Mastering PCI-IDE device */ 282 283 /* 284 * Scatter/Gather list for PCI-IDE Bus Mastering controllers 285 */ 286 caddr_t ac_sg_list; /* virtual addr of S/G list */ 287 paddr_t ac_sg_paddr; /* phys addr of S/G list */ 288 ddi_acc_handle_t ac_sg_acc_handle; 289 ddi_dma_handle_t ac_sg_handle; 290 291 /* 292 * data for managing ARQ on ATAPI devices 293 */ 294 struct ata_pkt *ac_arq_pktp; /* pkt for performing ATAPI ARQ */ 295 struct ata_pkt *ac_fault_pktp; /* pkt that caused ARQ */ 296 uchar_t ac_arq_cdb[6]; 297 298 /* 299 * Power Management 300 */ 301 int ac_pm_support; 302 int ac_pm_level; 303 } ata_ctl_t; 304 305 /* ac_flags (per-controller) */ 306 307 #define AC_GHD_INIT 0x02 308 #define AC_ATAPI_INIT 0x04 309 #define AC_DISK_INIT 0x08 310 #define AC_ATTACHED 0x10 311 #define AC_SCSI_HBA_TRAN_ALLOC 0x1000 312 #define AC_SCSI_HBA_ATTACH 0x2000 313 314 #define AC_BMSTATREG_PIO_BROKEN 0x80000000 315 316 /* 317 * Bug 1256489: 318 * 319 * If AC_BSY_WAIT needs to be set for laptops that do 320 * suspend/resume but do not correctly wait for the busy bit to 321 * drop after a resume. 322 */ 323 324 /* ac_timing_flags (per-controller) */ 325 #define AC_BSY_WAIT 0x1 /* tweak timing in ata_start & atapi_start */ 326 327 328 329 /* Identify drive data */ 330 struct ata_id { 331 /* WORD */ 332 /* OFFSET COMMENT */ 333 ushort_t ai_config; /* 0 general configuration bits */ 334 ushort_t ai_fixcyls; /* 1 # of fixed cylinders */ 335 ushort_t ai_resv0; /* 2 # reserved */ 336 ushort_t ai_heads; /* 3 # of heads */ 337 ushort_t ai_trksiz; /* 4 # of unformatted bytes/track */ 338 ushort_t ai_secsiz; /* 5 # of unformatted bytes/sector */ 339 ushort_t ai_sectors; /* 6 # of sectors/track */ 340 ushort_t ai_resv1[3]; /* 7 "Vendor Unique" */ 341 char ai_drvser[20]; /* 10 Serial number */ 342 ushort_t ai_buftype; /* 20 Buffer type */ 343 ushort_t ai_bufsz; /* 21 Buffer size in 512 byte incr */ 344 ushort_t ai_ecc; /* 22 # of ecc bytes avail on rd/wr */ 345 char ai_fw[8]; /* 23 Firmware revision */ 346 char ai_model[40]; /* 27 Model # */ 347 ushort_t ai_mult1; /* 47 Multiple command flags */ 348 ushort_t ai_dwcap; /* 48 Doubleword capabilities */ 349 ushort_t ai_cap; /* 49 Capabilities */ 350 ushort_t ai_resv2; /* 50 Reserved */ 351 ushort_t ai_piomode; /* 51 PIO timing mode */ 352 ushort_t ai_dmamode; /* 52 DMA timing mode */ 353 ushort_t ai_validinfo; /* 53 bit0: wds 54-58, bit1: 64-70 */ 354 ushort_t ai_curcyls; /* 54 # of current cylinders */ 355 ushort_t ai_curheads; /* 55 # of current heads */ 356 ushort_t ai_cursectrk; /* 56 # of current sectors/track */ 357 ushort_t ai_cursccp[2]; /* 57 current sectors capacity */ 358 ushort_t ai_mult2; /* 59 multiple sectors info */ 359 ushort_t ai_addrsec[2]; /* 60 LBA only: no of addr secs */ 360 ushort_t ai_sworddma; /* 62 single word dma modes */ 361 ushort_t ai_dworddma; /* 63 double word dma modes */ 362 ushort_t ai_advpiomode; /* 64 advanced PIO modes supported */ 363 ushort_t ai_minmwdma; /* 65 min multi-word dma cycle info */ 364 ushort_t ai_recmwdma; /* 66 rec multi-word dma cycle info */ 365 ushort_t ai_minpio; /* 67 min PIO cycle info */ 366 ushort_t ai_minpioflow; /* 68 min PIO cycle info w/flow ctl */ 367 ushort_t ai_resv3[2]; /* 69,70 reserved */ 368 ushort_t ai_resv4[4]; /* 71-74 reserved */ 369 ushort_t ai_qdepth; /* 75 queue depth */ 370 ushort_t ai_resv5[4]; /* 76-79 reserved */ 371 ushort_t ai_majorversion; /* 80 major versions supported */ 372 ushort_t ai_minorversion; /* 81 minor version number supported */ 373 ushort_t ai_cmdset82; /* 82 command set supported */ 374 ushort_t ai_cmdset83; /* 83 more command sets supported */ 375 ushort_t ai_cmdset84; /* 84 more command sets supported */ 376 ushort_t ai_features85; /* 85 enabled features */ 377 ushort_t ai_features86; /* 86 enabled features */ 378 ushort_t ai_features87; /* 87 enabled features */ 379 ushort_t ai_ultradma; /* 88 Ultra DMA mode */ 380 ushort_t ai_erasetime; /* 89 security erase time */ 381 ushort_t ai_erasetimex; /* 90 enhanced security erase time */ 382 ushort_t ai_padding1[9]; /* pad through 99 */ 383 ushort_t ai_addrsecxt[4]; /* 100 extended max LBA sector */ 384 ushort_t ai_padding2[22]; /* pad to 126 */ 385 ushort_t ai_lastlun; /* 126 last LUN, as per SFF-8070i */ 386 ushort_t ai_resv6; /* 127 reserved */ 387 ushort_t ai_securestatus; /* 128 security status */ 388 ushort_t ai_vendor[31]; /* 129-159 vendor specific */ 389 ushort_t ai_padding3[16]; /* 160 pad to 176 */ 390 ushort_t ai_curmedser[30]; /* 176-205 current media serial number */ 391 ushort_t ai_padding4[49]; /* 206 pad to 255 */ 392 ushort_t ai_integrity; /* 255 integrity word */ 393 }; 394 395 /* Identify Drive: general config bits - word 0 */ 396 397 #define ATA_ID_REM_DRV 0x80 398 #define ATA_ID_COMPACT_FLASH 0x848a 399 #define ATA_ID_CF_TO_ATA 0x040a 400 #define ATA_ID_INCMPT 0x0004 401 402 /* Identify Drive: common capability bits - word 49 */ 403 404 #define ATAC_DMA_SUPPORT 0x0100 405 #define ATAC_LBA_SUPPORT 0x0200 406 #define ATAC_IORDY_DISABLE 0x0400 407 #define ATAC_IORDY_SUPPORT 0x0800 408 #define ATAC_RESERVED_IDPKT 0x1000 /* rsrvd for identify pkt dev */ 409 #define ATAC_STANDBYTIMER 0x2000 410 #define ATAC_ATA_TYPE_MASK 0x8001 411 #define ATAC_ATA_TYPE 0x0000 412 #define ATAC_ATAPI_TYPE_MASK 0xc000 413 #define ATAC_ATAPI_TYPE 0x8000 414 415 /* Identify Driver ai_validinfo (word 53) */ 416 417 #define ATAC_VALIDINFO_83 0x0004 /* word 83 supported fields valid */ 418 #define ATAC_VALIDINFO_70_64 0x0002 /* word 70:64 sup. fields valid */ 419 420 /* Identify Drive: ai_dworddma (word 63) */ 421 422 #define ATAC_MDMA_SUP_MASK 0x0007 /* Multiword DMA supported */ 423 #define ATAC_MDMA_SEL_MASK 0x0700 /* Multiword DMA selected */ 424 #define ATAC_MDMA_2_SEL 0x0400 /* Multiword DMA mode 2 selected */ 425 #define ATAC_MDMA_1_SEL 0x0200 /* Multiword DMA mode 1 selected */ 426 #define ATAC_MDMA_0_SEL 0x0100 /* Multiword DMA mode 0 selected */ 427 #define ATAC_MDMA_2_SUP 0x0004 /* Multiword DMA mode 2 supported */ 428 #define ATAC_MDMA_1_SUP 0x0002 /* Multiword DMA mode 1 supported */ 429 #define ATAC_MDMA_0_SUP 0x0001 /* Multiword DMA mode 0 supported */ 430 431 /* Identify Drive: ai_advpiomode (word 64) */ 432 433 #define ATAC_ADVPIO_4_SUP 0x0002 /* PIO mode 4 supported */ 434 #define ATAC_ADVPIO_3_SUP 0x0001 /* PIO mode 3 supported */ 435 #define ATAC_ADVPIO_SERIAL 0x0003 /* Serial interface */ 436 437 /* Identify Drive: ai_majorversion (word 80) */ 438 439 #define ATAC_MAJVER_8 0x0100 /* ATA/ATAPI-8 version supported */ 440 #define ATAC_MAJVER_6 0x0040 /* ATA/ATAPI-6 version supported */ 441 #define ATAC_MAJVER_4 0x0010 /* ATA/ATAPI-4 version supported */ 442 443 /* Identify Drive: command set supported/enabled bits - words 83 and 86 */ 444 445 #define ATACS_EXT48 0x0400 /* 48 bit address feature */ 446 447 /* Identify Drive: ai_features85 (word 85) */ 448 #define ATAC_FEATURES85_WCE 0x0020 /* write cache enabled */ 449 450 /* Identify Drive: ai_ultradma (word 88) */ 451 #define ATAC_UDMA_SUP_MASK 0x007f /* UDMA modes supported */ 452 #define ATAC_UDMA_SEL_MASK 0x7f00 /* UDMA modes selected */ 453 454 455 /* per-drive data struct */ 456 457 typedef struct ata_drv { 458 ata_ctl_t *ad_ctlp; /* pointer back to ctlr */ 459 struct ata_id ad_id; /* IDENTIFY DRIVE data */ 460 461 uint_t ad_flags; 462 uchar_t ad_pciide_dma; /* PCIIDE DMA supported */ 463 uchar_t ad_targ; /* target */ 464 uchar_t ad_lun; /* lun */ 465 uchar_t ad_drive_bits; 466 467 /* Used by atapi side only */ 468 469 uchar_t ad_state; /* state of ATAPI FSM */ 470 uchar_t ad_cdb_len; /* Size of ATAPI CDBs */ 471 472 uchar_t ad_bogus_drq; 473 uchar_t ad_nec_bad_status; 474 475 /* Used by disk side only */ 476 477 struct scsi_device *ad_device; 478 struct scsi_inquiry ad_inquiry; 479 struct ctl_obj ad_ctl_obj; 480 uchar_t ad_rd_cmd; 481 uchar_t ad_wr_cmd; 482 ushort_t ad_acyl; 483 484 /* 485 * Geometry note: The following three values are the geometry 486 * that the driver will use. They may differ from the 487 * geometry reported by the controller and/or BIOS. See note 488 * on ata_fix_large_disk_geometry in ata_disk.c for more 489 * details. 490 */ 491 uint32_t ad_drvrcyl; /* number of cyls */ 492 uint32_t ad_drvrhd; /* number of heads */ 493 uint32_t ad_drvrsec; /* number of sectors */ 494 ushort_t ad_phhd; /* number of phys heads */ 495 ushort_t ad_phsec; /* number of phys sectors */ 496 short ad_block_factor; 497 short ad_bytes_per_block; 498 499 /* 500 * Support for 48-bit LBA (ATA-6) 501 */ 502 uint64_t ad_capacity; /* Total sectors on disk */ 503 504 /* 505 * save/restore the DMA mode for suspend/resume 506 */ 507 ushort_t ad_dma_cap; 508 ushort_t ad_dma_mode; 509 } ata_drv_t; 510 511 /* values for ad_dma_cap */ 512 #define ATA_DMA_ULTRAMODE 0x1 513 #define ATA_DMA_MWORDMODE 0x2 514 515 typedef struct ata_tgt { 516 ata_drv_t *at_drvp; 517 int at_arq; 518 ulong_t at_total_sectors; 519 ddi_dma_attr_t at_dma_attr; 520 } ata_tgt_t; 521 522 /* values for ad_pciide_dma */ 523 #define ATA_DMA_OFF 0x0 524 #define ATA_DMA_ON 0x1 525 #define ATA_DMA_UNINITIALIZED 0x2 526 527 /* 528 * (ata_pkt_t *) to (gcmd_t *) 529 */ 530 #define APKT2GCMD(apktp) (apktp->ap_gcmdp) 531 532 /* 533 * (gcmd_t *) to (ata_pkt_t *) 534 */ 535 #define GCMD2APKT(gcmdp) ((ata_pkt_t *)gcmdp->cmd_private) 536 537 /* 538 * (gtgt_t *) to (ata_ctl_t *) 539 */ 540 #define GTGTP2ATAP(gtgtp) ((ata_ctl_t *)GTGTP2HBA(gtgtp)) 541 542 /* 543 * (gtgt_t *) to (ata_tgt_t *) 544 */ 545 #define GTGTP2ATATGTP(gtgtp) ((ata_tgt_t *)GTGTP2TARGET(gtgtp)) 546 547 /* 548 * (gtgt_t *) to (ata_drv_t *) 549 */ 550 #define GTGTP2ATADRVP(gtgtp) (GTGTP2ATATGTP(gtgtp)->at_drvp) 551 552 /* 553 * (gcmd_t *) to (ata_tgt_t *) 554 */ 555 #define GCMD2TGT(gcmdp) GTGTP2ATATGTP(GCMDP2GTGTP(gcmdp)) 556 557 /* 558 * (gcmd_t *) to (ata_drv_t *) 559 */ 560 #define GCMD2DRV(gcmdp) GTGTP2ATADRVP(GCMDP2GTGTP(gcmdp)) 561 562 /* 563 * (ata_pkt_t *) to (ata_drv_t *) 564 */ 565 #define APKT2DRV(apktp) GCMD2DRV(APKT2GCMD(apktp)) 566 567 568 /* 569 * (struct hba_tran *) to (ata_ctl_t *) 570 */ 571 #define TRAN2ATAP(tranp) ((ata_ctl_t *)TRAN2HBA(tranp)) 572 573 574 /* 575 * ata common packet structure 576 */ 577 typedef struct ata_pkt { 578 579 gcmd_t *ap_gcmdp; /* GHD command struct */ 580 581 uint_t ap_flags; /* packet flags */ 582 583 caddr_t ap_baddr; /* I/O buffer base address */ 584 size_t ap_boffset; /* current offset into I/O buffer */ 585 size_t ap_bcount; /* # bytes in this request */ 586 587 caddr_t ap_v_addr; /* I/O buffer address */ 588 size_t ap_resid; /* # bytes left to read/write */ 589 590 uchar_t ap_pciide_dma; /* This pkt uses DMA transfer mode */ 591 prde_t ap_sg_list[ATA_DMA_NSEGS]; /* Scatter/Gather list */ 592 int ap_sg_cnt; /* number of entries in S/G list */ 593 594 /* command, starting sector number, sector count */ 595 596 daddr_t ap_startsec; /* starting sector number */ 597 ushort_t ap_count; /* sector count */ 598 uchar_t ap_sec; 599 uchar_t ap_lwcyl; 600 uchar_t ap_hicyl; 601 uchar_t ap_hd; 602 uchar_t ap_cmd; 603 604 /* saved status and error registers for error case */ 605 606 uchar_t ap_status; 607 uchar_t ap_error; 608 609 /* disk/atapi callback routines */ 610 611 int (*ap_start)(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 612 struct ata_pkt *ata_pktp); 613 int (*ap_intr)(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 614 struct ata_pkt *ata_pktp); 615 void (*ap_complete)(ata_drv_t *ata_drvp, 616 struct ata_pkt *ata_pktp, int do_callback); 617 618 /* Used by disk side */ 619 620 char ap_cdb; /* disk command */ 621 char ap_scb; /* status after disk cmd */ 622 uint_t ap_bytes_per_block; /* blk mode factor */ 623 uint_t ap_wrt_count; /* size of last write */ 624 caddr_t ap_v_addr_sav; /* Original I/O buffer address. */ 625 size_t ap_resid_sav; /* Original # of bytes */ 626 /* left to read/write. */ 627 628 /* Used by atapi side */ 629 630 uchar_t *ap_cdbp; /* ptr to SCSI CDB */ 631 uchar_t ap_cdb_len; /* length of SCSI CDB (in bytes) */ 632 uchar_t ap_cdb_pad; /* padding after SCSI CDB (in shorts) */ 633 634 struct scsi_arq_status *ap_scbp; /* ptr to SCSI status block */ 635 uchar_t ap_statuslen; /* length of SCSI status block */ 636 } ata_pkt_t; 637 638 639 /* 640 * defines for ap_flags 641 */ 642 #define AP_ATAPI 0x0001 /* device is atapi */ 643 #define AP_ERROR 0x0002 /* normal error */ 644 #define AP_TRAN_ERROR 0x0004 /* transport error */ 645 #define AP_READ 0x0008 /* read data */ 646 #define AP_WRITE 0x0010 /* write data */ 647 #define AP_ABORT 0x0020 /* packet aborted */ 648 #define AP_TIMEOUT 0x0040 /* packet timed out */ 649 #define AP_BUS_RESET 0x0080 /* bus reset */ 650 #define AP_DEV_RESET 0x0100 /* device reset */ 651 652 #define AP_SENT_CMD 0x0200 /* atapi: cdb sent */ 653 #define AP_XFERRED_DATA 0x0400 /* atapi: data transferred */ 654 #define AP_GOT_STATUS 0x0800 /* atapi: status received */ 655 #define AP_ARQ_ON_ERROR 0x1000 /* atapi: do ARQ on error */ 656 #define AP_ARQ_OKAY 0x2000 657 #define AP_ARQ_ERROR 0x4000 658 659 #define AP_FREE 0x80000000u /* packet is free! */ 660 661 662 /* 663 * public function prototypes 664 */ 665 666 int ata_check_drive_blacklist(struct ata_id *aidp, uint_t flags); 667 int ata_command(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, int expect_drdy, 668 int silent, uint_t busy_wait, uchar_t cmd, uchar_t feature, 669 uchar_t count, uchar_t sector, uchar_t head, uchar_t cyl_low, 670 uchar_t cyl_hi); 671 int ata_get_status_clear_intr(ata_ctl_t *ata_ctlp, ata_pkt_t *ata_pktp); 672 int ata_id_common(uchar_t id_cmd, int drdy_expected, 673 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 674 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 675 struct ata_id *ata_idp); 676 int ata_prop_create(dev_info_t *tgt_dip, ata_drv_t *ata_drvp, char *name); 677 int ata_queue_cmd(int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 678 void *arg, ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 679 gtgt_t *gtgtp); 680 int ata_set_feature(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 681 uchar_t feature, uchar_t value); 682 int ata_wait(ddi_acc_handle_t io_hdl, caddr_t ioaddr, uchar_t onbits, 683 uchar_t offbits, uint_t timeout_usec); 684 int ata_wait3(ddi_acc_handle_t io_hdl, caddr_t ioaddr, uchar_t onbits1, 685 uchar_t offbits1, uchar_t failure_onbits2, 686 uchar_t failure_offbits2, uchar_t failure_onbits3, 687 uchar_t failure_offbits3, uint_t timeout_usec); 688 int ata_test_lba_support(struct ata_id *aidp); 689 void ata_nsecwait(clock_t count); 690 int ata_set_dma_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp); 691 void ata_reset_dma_mode(ata_drv_t *ata_drvp); 692 void atapi_reset_dma_mode(ata_drv_t *ata_drvp, int need_wait); 693 694 695 /* 696 * PCIIDE DMA (Bus Mastering) functions and data in ata_dma.c 697 */ 698 extern ddi_dma_attr_t ata_pciide_dma_attr; 699 extern int ata_dma_disabled; 700 701 int ata_pciide_alloc(dev_info_t *dip, ata_ctl_t *ata_ctlp); 702 void ata_pciide_free(ata_ctl_t *ata_ctlp); 703 704 void ata_pciide_dma_sg_func(gcmd_t *gcmdp, ddi_dma_cookie_t *dmackp, 705 int single_segment, int seg_index); 706 void ata_pciide_dma_setup(ata_ctl_t *ata_ctlp, prde_t *srcp, int sg_cnt); 707 void ata_pciide_dma_start(ata_ctl_t *ata_ctlp, uchar_t direction); 708 void ata_pciide_dma_stop(ata_ctl_t *ata_ctlp); 709 int ata_pciide_status_clear(ata_ctl_t *ata_ctlp); 710 int ata_pciide_status_dmacheck_clear(ata_ctl_t *ata_ctlp); 711 int ata_pciide_status_pending(ata_ctl_t *ata_ctlp); 712 713 #ifdef __cplusplus 714 } 715 #endif 716 717 #endif /* _ATA_COMMON_H */ 718
Indexes created Wed Feb 10 04:24:43 UTC 2010
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