1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ 28 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ 29 /* All Rights Reserved */ 30 /* */ 31 /* Copyright (c) 1987, 1988 Microsoft Corporation */ 32 /* All Rights Reserved */ 33 /* */ 34 35 #include <sys/types.h> 36 #include <sys/sysmacros.h> 37 #include <sys/param.h> 38 #include <sys/signal.h> 39 #include <sys/systm.h> 40 #include <sys/user.h> 41 #include <sys/proc.h> 42 #include <sys/disp.h> 43 #include <sys/class.h> 44 #include <sys/core.h> 45 #include <sys/syscall.h> 46 #include <sys/cpuvar.h> 47 #include <sys/vm.h> 48 #include <sys/sysinfo.h> 49 #include <sys/fault.h> 50 #include <sys/stack.h> 51 #include <sys/psw.h> 52 #include <sys/regset.h> 53 #include <sys/fp.h> 54 #include <sys/trap.h> 55 #include <sys/kmem.h> 56 #include <sys/vtrace.h> 57 #include <sys/cmn_err.h> 58 #include <sys/prsystm.h> 59 #include <sys/mutex_impl.h> 60 #include <sys/machsystm.h> 61 #include <sys/archsystm.h> 62 #include <sys/sdt.h> 63 #include <sys/avintr.h> 64 #include <sys/kobj.h> 65 66 #include <vm/hat.h> 67 68 #include <vm/seg_kmem.h> 69 #include <vm/as.h> 70 #include <vm/seg.h> 71 #include <vm/hat_pte.h> 72 #include <vm/hat_i86.h> 73 74 #include <sys/procfs.h> 75 76 #include <sys/reboot.h> 77 #include <sys/debug.h> 78 #include <sys/debugreg.h> 79 #include <sys/modctl.h> 80 #include <sys/aio_impl.h> 81 #include <sys/tnf.h> 82 #include <sys/tnf_probe.h> 83 #include <sys/cred.h> 84 #include <sys/mman.h> 85 #include <sys/x86_archext.h> 86 #include <sys/copyops.h> 87 #include <c2/audit.h> 88 #include <sys/ftrace.h> 89 #include <sys/panic.h> 90 #include <sys/traptrace.h> 91 #include <sys/ontrap.h> 92 #include <sys/cpc_impl.h> 93 #include <sys/bootconf.h> 94 #include <sys/bootinfo.h> 95 #include <sys/promif.h> 96 #include <sys/mach_mmu.h> 97 #if defined(__xpv) 98 #include <sys/hypervisor.h> 99 #endif 100 #include <sys/contract/process_impl.h> 101 102 #define USER 0x10000 /* user-mode flag added to trap type */ 103 104 static const char *trap_type_mnemonic[] = { 105 "de", "db", "2", "bp", 106 "of", "br", "ud", "nm", 107 "df", "9", "ts", "np", 108 "ss", "gp", "pf", "15", 109 "mf", "ac", "mc", "xf" 110 }; 111 112 static const char *trap_type[] = { 113 "Divide error", /* trap id 0 */ 114 "Debug", /* trap id 1 */ 115 "NMI interrupt", /* trap id 2 */ 116 "Breakpoint", /* trap id 3 */ 117 "Overflow", /* trap id 4 */ 118 "BOUND range exceeded", /* trap id 5 */ 119 "Invalid opcode", /* trap id 6 */ 120 "Device not available", /* trap id 7 */ 121 "Double fault", /* trap id 8 */ 122 "Coprocessor segment overrun", /* trap id 9 */ 123 "Invalid TSS", /* trap id 10 */ 124 "Segment not present", /* trap id 11 */ 125 "Stack segment fault", /* trap id 12 */ 126 "General protection", /* trap id 13 */ 127 "Page fault", /* trap id 14 */ 128 "Reserved", /* trap id 15 */ 129 "x87 floating point error", /* trap id 16 */ 130 "Alignment check", /* trap id 17 */ 131 "Machine check", /* trap id 18 */ 132 "SIMD floating point exception", /* trap id 19 */ 133 }; 134 135 #define TRAP_TYPES (sizeof (trap_type) / sizeof (trap_type[0])) 136 137 #define SLOW_SCALL_SIZE 2 138 #define FAST_SCALL_SIZE 2 139 140 int tudebug = 0; 141 int tudebugbpt = 0; 142 int tudebugfpe = 0; 143 int tudebugsse = 0; 144 145 #if defined(TRAPDEBUG) || defined(lint) 146 int tdebug = 0; 147 int lodebug = 0; 148 int faultdebug = 0; 149 #else 150 #define tdebug 0 151 #define lodebug 0 152 #define faultdebug 0 153 #endif /* defined(TRAPDEBUG) || defined(lint) */ 154 155 #if defined(TRAPTRACE) 156 /* 157 * trap trace record for cpu0 is allocated here. 158 * trap trace records for non-boot cpus are allocated in mp_startup_init(). 159 */ 160 static trap_trace_rec_t trap_tr0[TRAPTR_NENT]; 161 trap_trace_ctl_t trap_trace_ctl[NCPU] = { 162 { 163 (uintptr_t)trap_tr0, /* next record */ 164 (uintptr_t)trap_tr0, /* first record */ 165 (uintptr_t)(trap_tr0 + TRAPTR_NENT), /* limit */ 166 (uintptr_t)0 /* current */ 167 }, 168 }; 169 170 /* 171 * default trap buffer size 172 */ 173 size_t trap_trace_bufsize = TRAPTR_NENT * sizeof (trap_trace_rec_t); 174 int trap_trace_freeze = 0; 175 int trap_trace_off = 0; 176 177 /* 178 * A dummy TRAPTRACE entry to use after death. 179 */ 180 trap_trace_rec_t trap_trace_postmort; 181 182 static void dump_ttrace(void); 183 #endif /* TRAPTRACE */ 184 static void dumpregs(struct regs *); 185 static void showregs(uint_t, struct regs *, caddr_t); 186 static int kern_gpfault(struct regs *); 187 188 /*ARGSUSED*/ 189 static int 190 die(uint_t type, struct regs *rp, caddr_t addr, processorid_t cpuid) 191 { 192 struct panic_trap_info ti; 193 const char *trap_name, *trap_mnemonic; 194 195 if (type < TRAP_TYPES) { 196 trap_name = trap_type[type]; 197 trap_mnemonic = trap_type_mnemonic[type]; 198 } else { 199 trap_name = "trap"; 200 trap_mnemonic = "-"; 201 } 202 203 #ifdef TRAPTRACE 204 TRAPTRACE_FREEZE; 205 #endif 206 207 ti.trap_regs = rp; 208 ti.trap_type = type & ~USER; 209 ti.trap_addr = addr; 210 211 curthread->t_panic_trap = &ti; 212 213 if (type == T_PGFLT && addr < (caddr_t)KERNELBASE) { 214 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p " 215 "occurred in module \"%s\" due to %s", 216 type, trap_mnemonic, trap_name, (void *)rp, (void *)addr, 217 mod_containing_pc((caddr_t)rp->r_pc), 218 addr < (caddr_t)PAGESIZE ? 219 "a NULL pointer dereference" : 220 "an illegal access to a user address"); 221 } else 222 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p", 223 type, trap_mnemonic, trap_name, (void *)rp, (void *)addr); 224 return (0); 225 } 226 227 /* 228 * Rewrite the instruction at pc to be an int $T_SYSCALLINT instruction. 229 * 230 * int <vector> is two bytes: 0xCD <vector> 231 */ 232 233 static int 234 rewrite_syscall(caddr_t pc) 235 { 236 uchar_t instr[SLOW_SCALL_SIZE] = { 0xCD, T_SYSCALLINT }; 237 238 if (uwrite(curthread->t_procp, instr, SLOW_SCALL_SIZE, 239 (uintptr_t)pc) != 0) 240 return (1); 241 242 return (0); 243 } 244 245 /* 246 * Test to see if the instruction at pc is sysenter or syscall. The second 247 * argument should be the x86 feature flag corresponding to the expected 248 * instruction. 249 * 250 * sysenter is two bytes: 0x0F 0x34 251 * syscall is two bytes: 0x0F 0x05 252 * int $T_SYSCALLINT is two bytes: 0xCD 0x91 253 */ 254 255 static int 256 instr_is_other_syscall(caddr_t pc, int which) 257 { 258 uchar_t instr[FAST_SCALL_SIZE]; 259 260 ASSERT(which == X86_SEP || which == X86_ASYSC || which == 0xCD); 261 262 if (copyin_nowatch(pc, (caddr_t)instr, FAST_SCALL_SIZE) != 0) 263 return (0); 264 265 switch (which) { 266 case X86_SEP: 267 if (instr[0] == 0x0F && instr[1] == 0x34) 268 return (1); 269 break; 270 case X86_ASYSC: 271 if (instr[0] == 0x0F && instr[1] == 0x05) 272 return (1); 273 break; 274 case 0xCD: 275 if (instr[0] == 0xCD && instr[1] == T_SYSCALLINT) 276 return (1); 277 break; 278 } 279 280 return (0); 281 } 282 283 static const char * 284 syscall_insn_string(int syscall_insn) 285 { 286 switch (syscall_insn) { 287 case X86_SEP: 288 return ("sysenter"); 289 case X86_ASYSC: 290 return ("syscall"); 291 case 0xCD: 292 return ("int"); 293 default: 294 return ("Unknown"); 295 } 296 } 297 298 static int 299 ldt_rewrite_syscall(struct regs *rp, proc_t *p, int syscall_insn) 300 { 301 caddr_t linearpc; 302 int return_code = 0; 303 304 mutex_enter(&p->p_ldtlock); /* Must be held across linear_pc() */ 305 306 if (linear_pc(rp, p, &linearpc) == 0) { 307 308 /* 309 * If another thread beat us here, it already changed 310 * this site to the slower (int) syscall instruction. 311 */ 312 if (instr_is_other_syscall(linearpc, 0xCD)) { 313 return_code = 1; 314 } else if (instr_is_other_syscall(linearpc, syscall_insn)) { 315 316 if (rewrite_syscall(linearpc) == 0) { 317 return_code = 1; 318 } 319 #ifdef DEBUG 320 else 321 cmn_err(CE_WARN, "failed to rewrite %s " 322 "instruction in process %d", 323 syscall_insn_string(syscall_insn), 324 p->p_pid); 325 #endif /* DEBUG */ 326 } 327 } 328 329 mutex_exit(&p->p_ldtlock); /* Must be held across linear_pc() */ 330 331 return (return_code); 332 } 333 334 /* 335 * Test to see if the instruction at pc is a system call instruction. 336 * 337 * The bytes of an lcall instruction used for the syscall trap. 338 * static uchar_t lcall[7] = { 0x9a, 0, 0, 0, 0, 0x7, 0 }; 339 * static uchar_t lcallalt[7] = { 0x9a, 0, 0, 0, 0, 0x27, 0 }; 340 */ 341 342 #define LCALLSIZE 7 343 344 static int 345 instr_is_lcall_syscall(caddr_t pc) 346 { 347 uchar_t instr[LCALLSIZE]; 348 349 if (copyin_nowatch(pc, (caddr_t)instr, LCALLSIZE) == 0 && 350 instr[0] == 0x9a && 351 instr[1] == 0 && 352 instr[2] == 0 && 353 instr[3] == 0 && 354 instr[4] == 0 && 355 (instr[5] == 0x7 || instr[5] == 0x27) && 356 instr[6] == 0) 357 return (1); 358 359 return (0); 360 } 361 362 #ifdef __amd64 363 364 /* 365 * In the first revisions of amd64 CPUs produced by AMD, the LAHF and 366 * SAHF instructions were not implemented in 64-bit mode. Later revisions 367 * did implement these instructions. An extension to the cpuid instruction 368 * was added to check for the capability of executing these instructions 369 * in 64-bit mode. 370 * 371 * Intel originally did not implement these instructions in EM64T either, 372 * but added them in later revisions. 373 * 374 * So, there are different chip revisions by both vendors out there that 375 * may or may not implement these instructions. The easy solution is to 376 * just always emulate these instructions on demand. 377 * 378 * SAHF == store %ah in the lower 8 bits of %rflags (opcode 0x9e) 379 * LAHF == load the lower 8 bits of %rflags into %ah (opcode 0x9f) 380 */ 381 382 #define LSAHFSIZE 1 383 384 static int 385 instr_is_lsahf(caddr_t pc, uchar_t *instr) 386 { 387 if (copyin_nowatch(pc, (caddr_t)instr, LSAHFSIZE) == 0 && 388 (*instr == 0x9e || *instr == 0x9f)) 389 return (1); 390 return (0); 391 } 392 393 /* 394 * Emulate the LAHF and SAHF instructions. The reference manuals define 395 * these instructions to always load/store bit 1 as a 1, and bits 3 and 5 396 * as a 0. The other, defined, bits are copied (the PS_ICC bits and PS_P). 397 * 398 * Note that %ah is bits 8-15 of %rax. 399 */ 400 static void 401 emulate_lsahf(struct regs *rp, uchar_t instr) 402 { 403 if (instr == 0x9e) { 404 /* sahf. Copy bits from %ah to flags. */ 405 rp->r_ps = (rp->r_ps & ~0xff) | 406 ((rp->r_rax >> 8) & PSL_LSAHFMASK) | PS_MB1; 407 } else { 408 /* lahf. Copy bits from flags to %ah. */ 409 rp->r_rax = (rp->r_rax & ~0xff00) | 410 (((rp->r_ps & PSL_LSAHFMASK) | PS_MB1) << 8); 411 } 412 rp->r_pc += LSAHFSIZE; 413 } 414 #endif /* __amd64 */ 415 416 #ifdef OPTERON_ERRATUM_91 417 418 /* 419 * Test to see if the instruction at pc is a prefetch instruction. 420 * 421 * The first byte of prefetch instructions is always 0x0F. 422 * The second byte is 0x18 for regular prefetch or 0x0D for AMD 3dnow prefetch. 423 * The third byte (ModRM) contains the register field bits (bits 3-5). 424 * These bits must be between 0 and 3 inclusive for regular prefetch and 425 * 0 and 1 inclusive for AMD 3dnow prefetch. 426 * 427 * In 64-bit mode, there may be a one-byte REX prefex (0x40-0x4F). 428 */ 429 430 static int 431 cmp_to_prefetch(uchar_t *p) 432 { 433 #ifdef _LP64 434 if ((p[0] & 0xF0) == 0x40) /* 64-bit REX prefix */ 435 p++; 436 #endif 437 return ((p[0] == 0x0F && p[1] == 0x18 && ((p[2] >> 3) & 7) <= 3) || 438 (p[0] == 0x0F && p[1] == 0x0D && ((p[2] >> 3) & 7) <= 1)); 439 } 440 441 static int 442 instr_is_prefetch(caddr_t pc) 443 { 444 uchar_t instr[4]; /* optional REX prefix plus 3-byte opcode */ 445 446 return (copyin_nowatch(pc, instr, sizeof (instr)) == 0 && 447 cmp_to_prefetch(instr)); 448 } 449 450 #endif /* OPTERON_ERRATUM_91 */ 451 452 /* 453 * Called from the trap handler when a processor trap occurs. 454 * 455 * Note: All user-level traps that might call stop() must exit 456 * trap() by 'goto out' or by falling through. 457 * Note Also: trap() is usually called with interrupts enabled, (PS_IE == 1) 458 * however, there are paths that arrive here with PS_IE == 0 so special care 459 * must be taken in those cases. 460 */ 461 void 462 trap(struct regs *rp, caddr_t addr, processorid_t cpuid) 463 { 464 kthread_t *ct = curthread; 465 enum seg_rw rw; 466 unsigned type; 467 proc_t *p = ttoproc(ct); 468 klwp_t *lwp = ttolwp(ct); 469 uintptr_t lofault; 470 faultcode_t pagefault(), res, errcode; 471 enum fault_type fault_type; 472 k_siginfo_t siginfo; 473 uint_t fault = 0; 474 int mstate; 475 int sicode = 0; 476 int watchcode; 477 int watchpage; 478 caddr_t vaddr; 479 int singlestep_twiddle; 480 size_t sz; 481 int ta; 482 #ifdef __amd64 483 uchar_t instr; 484 #endif 485 486 ASSERT_STACK_ALIGNED(); 487 488 type = rp->r_trapno; 489 CPU_STATS_ADDQ(CPU, sys, trap, 1); 490 ASSERT(ct->t_schedflag & TS_DONT_SWAP); 491 492 if (type == T_PGFLT) { 493 494 errcode = rp->r_err; 495 if (errcode & PF_ERR_WRITE) 496 rw = S_WRITE; 497 else if ((caddr_t)rp->r_pc == addr || 498 (mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC))) 499 rw = S_EXEC; 500 else 501 rw = S_READ; 502 503 #if defined(__i386) 504 /* 505 * Pentium Pro work-around 506 */ 507 if ((errcode & PF_ERR_PROT) && pentiumpro_bug4046376) { 508 uint_t attr; 509 uint_t priv_violation; 510 uint_t access_violation; 511 512 if (hat_getattr(addr < (caddr_t)kernelbase ? 513 curproc->p_as->a_hat : kas.a_hat, addr, &attr) 514 == -1) { 515 errcode &= ~PF_ERR_PROT; 516 } else { 517 priv_violation = (errcode & PF_ERR_USER) && 518 !(attr & PROT_USER); 519 access_violation = (errcode & PF_ERR_WRITE) && 520 !(attr & PROT_WRITE); 521 if (!priv_violation && !access_violation) 522 goto cleanup; 523 } 524 } 525 #endif /* __i386 */ 526 527 } else if (type == T_SGLSTP && lwp != NULL) 528 lwp->lwp_pcb.pcb_drstat = (uintptr_t)addr; 529 530 if (tdebug) 531 showregs(type, rp, addr); 532 533 if (USERMODE(rp->r_cs)) { 534 /* 535 * Set up the current cred to use during this trap. u_cred 536 * no longer exists. t_cred is used instead. 537 * The current process credential applies to the thread for 538 * the entire trap. If trapping from the kernel, this 539 * should already be set up. 540 */ 541 if (ct->t_cred != p->p_cred) { 542 cred_t *oldcred = ct->t_cred; 543 /* 544 * DTrace accesses t_cred in probe context. t_cred 545 * must always be either NULL, or point to a valid, 546 * allocated cred structure. 547 */ 548 ct->t_cred = crgetcred(); 549 crfree(oldcred); 550 } 551 ASSERT(lwp != NULL); 552 type |= USER; 553 ASSERT(lwptoregs(lwp) == rp); 554 lwp->lwp_state = LWP_SYS; 555 556 switch (type) { 557 case T_PGFLT + USER: 558 if ((caddr_t)rp->r_pc == addr) 559 mstate = LMS_TFAULT; 560 else 561 mstate = LMS_DFAULT; 562 break; 563 default: 564 mstate = LMS_TRAP; 565 break; 566 } 567 /* Kernel probe */ 568 TNF_PROBE_1(thread_state, "thread", /* CSTYLED */, 569 tnf_microstate, state, mstate); 570 mstate = new_mstate(ct, mstate); 571 572 bzero(&siginfo, sizeof (siginfo)); 573 } 574 575 switch (type) { 576 case T_PGFLT + USER: 577 case T_SGLSTP: 578 case T_SGLSTP + USER: 579 case T_BPTFLT + USER: 580 break; 581 582 default: 583 FTRACE_2("trap(): type=0x%lx, regs=0x%lx", 584 (ulong_t)type, (ulong_t)rp); 585 break; 586 } 587 588 switch (type) { 589 case T_SIMDFPE: 590 /* Make sure we enable interrupts before die()ing */ 591 sti(); /* The SIMD exception comes in via cmninttrap */ 592 /*FALLTHROUGH*/ 593 default: 594 if (type & USER) { 595 if (tudebug) 596 showregs(type, rp, (caddr_t)0); 597 printf("trap: Unknown trap type %d in user mode\n", 598 type & ~USER); 599 siginfo.si_signo = SIGILL; 600 siginfo.si_code = ILL_ILLTRP; 601 siginfo.si_addr = (caddr_t)rp->r_pc; 602 siginfo.si_trapno = type & ~USER; 603 fault = FLTILL; 604 break; 605 } else { 606 (void) die(type, rp, addr, cpuid); 607 /*NOTREACHED*/ 608 } 609 610 case T_PGFLT: /* system page fault */ 611 /* 612 * If we're under on_trap() protection (see <sys/ontrap.h>), 613 * set ot_trap and bounce back to the on_trap() call site 614 * via the installed trampoline. 615 */ 616 if ((ct->t_ontrap != NULL) && 617 (ct->t_ontrap->ot_prot & OT_DATA_ACCESS)) { 618 ct->t_ontrap->ot_trap |= OT_DATA_ACCESS; 619 rp->r_pc = ct->t_ontrap->ot_trampoline; 620 goto cleanup; 621 } 622 623 /* 624 * See if we can handle as pagefault. Save lofault 625 * across this. Here we assume that an address 626 * less than KERNELBASE is a user fault. 627 * We can do this as copy.s routines verify that the 628 * starting address is less than KERNELBASE before 629 * starting and because we know that we always have 630 * KERNELBASE mapped as invalid to serve as a "barrier". 631 */ 632 lofault = ct->t_lofault; 633 ct->t_lofault = 0; 634 635 mstate = new_mstate(ct, LMS_KFAULT); 636 637 if (addr < (caddr_t)kernelbase) { 638 res = pagefault(addr, 639 (errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 0); 640 if (res == FC_NOMAP && 641 addr < p->p_usrstack && 642 grow(addr)) 643 res = 0; 644 } else { 645 res = pagefault(addr, 646 (errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 1); 647 } 648 (void) new_mstate(ct, mstate); 649 650 /* 651 * Restore lofault. If we resolved the fault, exit. 652 * If we didn't and lofault wasn't set, die. 653 */ 654 ct->t_lofault = lofault; 655 if (res == 0) 656 goto cleanup; 657 658 #if defined(OPTERON_ERRATUM_93) && defined(_LP64) 659 if (lofault == 0 && opteron_erratum_93) { 660 /* 661 * Workaround for Opteron Erratum 93. On return from 662 * a System Managment Interrupt at a HLT instruction 663 * the %rip might be truncated to a 32 bit value. 664 * BIOS is supposed to fix this, but some don't. 665 * If this occurs we simply restore the high order bits. 666 * The HLT instruction is 1 byte of 0xf4. 667 */ 668 uintptr_t rip = rp->r_pc; 669 670 if ((rip & 0xfffffffful) == rip) { 671 rip |= 0xfffffffful << 32; 672 if (hat_getpfnum(kas.a_hat, (caddr_t)rip) != 673 PFN_INVALID && 674 (*(uchar_t *)rip == 0xf4 || 675 *(uchar_t *)(rip - 1) == 0xf4)) { 676 rp->r_pc = rip; 677 goto cleanup; 678 } 679 } 680 } 681 #endif /* OPTERON_ERRATUM_93 && _LP64 */ 682 683 #ifdef OPTERON_ERRATUM_91 684 if (lofault == 0 && opteron_erratum_91) { 685 /* 686 * Workaround for Opteron Erratum 91. Prefetches may 687 * generate a page fault (they're not supposed to do 688 * that!). If this occurs we simply return back to the 689 * instruction. 690 */ 691 caddr_t pc = (caddr_t)rp->r_pc; 692 693 /* 694 * If the faulting PC is not mapped, this is a 695 * legitimate kernel page fault that must result in a 696 * panic. If the faulting PC is mapped, it could contain 697 * a prefetch instruction. Check for that here. 698 */ 699 if (hat_getpfnum(kas.a_hat, pc) != PFN_INVALID) { 700 if (cmp_to_prefetch((uchar_t *)pc)) { 701 #ifdef DEBUG 702 cmn_err(CE_WARN, "Opteron erratum 91 " 703 "occurred: kernel prefetch" 704 " at %p generated a page fault!", 705 (void *)rp->r_pc); 706 #endif /* DEBUG */ 707 goto cleanup; 708 } 709 } 710 (void) die(type, rp, addr, cpuid); 711 } 712 #endif /* OPTERON_ERRATUM_91 */ 713 714 if (lofault == 0) 715 (void) die(type, rp, addr, cpuid); 716 717 /* 718 * Cannot resolve fault. Return to lofault. 719 */ 720 if (lodebug) { 721 showregs(type, rp, addr); 722 traceregs(rp); 723 } 724 if (FC_CODE(res) == FC_OBJERR) 725 res = FC_ERRNO(res); 726 else 727 res = EFAULT; 728 rp->r_r0 = res; 729 rp->r_pc = ct->t_lofault; 730 goto cleanup; 731 732 case T_PGFLT + USER: /* user page fault */ 733 if (faultdebug) { 734 char *fault_str; 735 736 switch (rw) { 737 case S_READ: 738 fault_str = "read"; 739 break; 740 case S_WRITE: 741 fault_str = "write"; 742 break; 743 case S_EXEC: 744 fault_str = "exec"; 745 break; 746 default: 747 fault_str = ""; 748 break; 749 } 750 printf("user %s fault: addr=0x%lx errcode=0x%x\n", 751 fault_str, (uintptr_t)addr, errcode); 752 } 753 754 #if defined(OPTERON_ERRATUM_100) && defined(_LP64) 755 /* 756 * Workaround for AMD erratum 100 757 * 758 * A 32-bit process may receive a page fault on a non 759 * 32-bit address by mistake. The range of the faulting 760 * address will be 761 * 762 * 0xffffffff80000000 .. 0xffffffffffffffff or 763 * 0x0000000100000000 .. 0x000000017fffffff 764 * 765 * The fault is always due to an instruction fetch, however 766 * the value of r_pc should be correct (in 32 bit range), 767 * so we ignore the page fault on the bogus address. 768 */ 769 if (p->p_model == DATAMODEL_ILP32 && 770 (0xffffffff80000000 <= (uintptr_t)addr || 771 (0x100000000 <= (uintptr_t)addr && 772 (uintptr_t)addr <= 0x17fffffff))) { 773 if (!opteron_erratum_100) 774 panic("unexpected erratum #100"); 775 if (rp->r_pc <= 0xffffffff) 776 goto out; 777 } 778 #endif /* OPTERON_ERRATUM_100 && _LP64 */ 779 780 ASSERT(!(curthread->t_flag & T_WATCHPT)); 781 watchpage = (pr_watch_active(p) && pr_is_watchpage(addr, rw)); 782 #ifdef __i386 783 /* 784 * In 32-bit mode, the lcall (system call) instruction fetches 785 * one word from the stack, at the stack pointer, because of the 786 * way the call gate is constructed. This is a bogus 787 * read and should not be counted as a read watchpoint. 788 * We work around the problem here by testing to see if 789 * this situation applies and, if so, simply jumping to 790 * the code in locore.s that fields the system call trap. 791 * The registers on the stack are already set up properly 792 * due to the match between the call gate sequence and the 793 * trap gate sequence. We just have to adjust the pc. 794 */ 795 if (watchpage && addr == (caddr_t)rp->r_sp && 796 rw == S_READ && instr_is_lcall_syscall((caddr_t)rp->r_pc)) { 797 extern void watch_syscall(void); 798 799 rp->r_pc += LCALLSIZE; 800 watch_syscall(); /* never returns */ 801 /* NOTREACHED */ 802 } 803 #endif /* __i386 */ 804 vaddr = addr; 805 if (!watchpage || (sz = instr_size(rp, &vaddr, rw)) <= 0) 806 fault_type = (errcode & PF_ERR_PROT)? F_PROT: F_INVAL; 807 else if ((watchcode = pr_is_watchpoint(&vaddr, &ta, 808 sz, NULL, rw)) != 0) { 809 if (ta) { 810 do_watch_step(vaddr, sz, rw, 811 watchcode, rp->r_pc); 812 fault_type = F_INVAL; 813 } else { 814 bzero(&siginfo, sizeof (siginfo)); 815 siginfo.si_signo = SIGTRAP; 816 siginfo.si_code = watchcode; 817 siginfo.si_addr = vaddr; 818 siginfo.si_trapafter = 0; 819 siginfo.si_pc = (caddr_t)rp->r_pc; 820 fault = FLTWATCH; 821 break; 822 } 823 } else { 824 /* XXX pr_watch_emul() never succeeds (for now) */ 825 if (rw != S_EXEC && pr_watch_emul(rp, vaddr, rw)) 826 goto out; 827 do_watch_step(vaddr, sz, rw, 0, 0); 828 fault_type = F_INVAL; 829 } 830 831 res = pagefault(addr, fault_type, rw, 0); 832 833 /* 834 * If pagefault() succeeded, ok. 835 * Otherwise attempt to grow the stack. 836 */ 837 if (res == 0 || 838 (res == FC_NOMAP && 839 addr < p->p_usrstack && 840 grow(addr))) { 841 lwp->lwp_lastfault = FLTPAGE; 842 lwp->lwp_lastfaddr = addr; 843 if (prismember(&p->p_fltmask, FLTPAGE)) { 844 bzero(&siginfo, sizeof (siginfo)); 845 siginfo.si_addr = addr; 846 (void) stop_on_fault(FLTPAGE, &siginfo); 847 } 848 goto out; 849 } else if (res == FC_PROT && addr < p->p_usrstack && 850 (mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC))) { 851 report_stack_exec(p, addr); 852 } 853 854 #ifdef OPTERON_ERRATUM_91 855 /* 856 * Workaround for Opteron Erratum 91. Prefetches may generate a 857 * page fault (they're not supposed to do that!). If this 858 * occurs we simply return back to the instruction. 859 * 860 * We rely on copyin to properly fault in the page with r_pc. 861 */ 862 if (opteron_erratum_91 && 863 addr != (caddr_t)rp->r_pc && 864 instr_is_prefetch((caddr_t)rp->r_pc)) { 865 #ifdef DEBUG 866 cmn_err(CE_WARN, "Opteron erratum 91 occurred: " 867 "prefetch at %p in pid %d generated a trap!", 868 (void *)rp->r_pc, p->p_pid); 869 #endif /* DEBUG */ 870 goto out; 871 } 872 #endif /* OPTERON_ERRATUM_91 */ 873 874 if (tudebug) 875 showregs(type, rp, addr); 876 /* 877 * In the case where both pagefault and grow fail, 878 * set the code to the value provided by pagefault. 879 * We map all errors returned from pagefault() to SIGSEGV. 880 */ 881 bzero(&siginfo, sizeof (siginfo)); 882 siginfo.si_addr = addr; 883 switch (FC_CODE(res)) { 884 case FC_HWERR: 885 case FC_NOSUPPORT: 886 siginfo.si_signo = SIGBUS; 887 siginfo.si_code = BUS_ADRERR; 888 fault = FLTACCESS; 889 break; 890 case FC_ALIGN: 891 siginfo.si_signo = SIGBUS; 892 siginfo.si_code = BUS_ADRALN; 893 fault = FLTACCESS; 894 break; 895 case FC_OBJERR: 896 if ((siginfo.si_errno = FC_ERRNO(res)) != EINTR) { 897 siginfo.si_signo = SIGBUS; 898 siginfo.si_code = BUS_OBJERR; 899 fault = FLTACCESS; 900 } 901 break; 902 default: /* FC_NOMAP or FC_PROT */ 903 siginfo.si_signo = SIGSEGV; 904 siginfo.si_code = 905 (res == FC_NOMAP)? SEGV_MAPERR : SEGV_ACCERR; 906 fault = FLTBOUNDS; 907 break; 908 } 909 break; 910 911 case T_ILLINST + USER: /* invalid opcode fault */ 912 /* 913 * If the syscall instruction is disabled due to LDT usage, a 914 * user program that attempts to execute it will trigger a #ud 915 * trap. Check for that case here. If this occurs on a CPU which 916 * doesn't even support syscall, the result of all of this will 917 * be to emulate that particular instruction. 918 */ 919 if (p->p_ldt != NULL && 920 ldt_rewrite_syscall(rp, p, X86_ASYSC)) 921 goto out; 922 923 #ifdef __amd64 924 /* 925 * Emulate the LAHF and SAHF instructions if needed. 926 * See the instr_is_lsahf function for details. 927 */ 928 if (p->p_model == DATAMODEL_LP64 && 929 instr_is_lsahf((caddr_t)rp->r_pc, &instr)) { 930 emulate_lsahf(rp, instr); 931 goto out; 932 } 933 #endif 934 935 /*FALLTHROUGH*/ 936 937 if (tudebug) 938 showregs(type, rp, (caddr_t)0); 939 siginfo.si_signo = SIGILL; 940 siginfo.si_code = ILL_ILLOPC; 941 siginfo.si_addr = (caddr_t)rp->r_pc; 942 fault = FLTILL; 943 break; 944 945 case T_ZERODIV + USER: /* integer divide by zero */ 946 if (tudebug && tudebugfpe) 947 showregs(type, rp, (caddr_t)0); 948 siginfo.si_signo = SIGFPE; 949 siginfo.si_code = FPE_INTDIV; 950 siginfo.si_addr = (caddr_t)rp->r_pc; 951 fault = FLTIZDIV; 952 break; 953 954 case T_OVFLW + USER: /* integer overflow */ 955 if (tudebug && tudebugfpe) 956 showregs(type, rp, (caddr_t)0); 957 siginfo.si_signo = SIGFPE; 958 siginfo.si_code = FPE_INTOVF; 959 siginfo.si_addr = (caddr_t)rp->r_pc; 960 fault = FLTIOVF; 961 break; 962 963 case T_NOEXTFLT + USER: /* math coprocessor not available */ 964 if (tudebug && tudebugfpe) 965 showregs(type, rp, addr); 966 if (fpnoextflt(rp)) { 967 siginfo.si_signo = SIGILL; 968 siginfo.si_code = ILL_ILLOPC; 969 siginfo.si_addr = (caddr_t)rp->r_pc; 970 fault = FLTILL; 971 } 972 break; 973 974 case T_EXTOVRFLT: /* extension overrun fault */ 975 /* check if we took a kernel trap on behalf of user */ 976 { 977 extern void ndptrap_frstor(void); 978 if (rp->r_pc != (uintptr_t)ndptrap_frstor) { 979 sti(); /* T_EXTOVRFLT comes in via cmninttrap */ 980 (void) die(type, rp, addr, cpuid); 981 } 982 type |= USER; 983 } 984 /*FALLTHROUGH*/ 985 case T_EXTOVRFLT + USER: /* extension overrun fault */ 986 if (tudebug && tudebugfpe) 987 showregs(type, rp, addr); 988 if (fpextovrflt(rp)) { 989 siginfo.si_signo = SIGSEGV; 990 siginfo.si_code = SEGV_MAPERR; 991 siginfo.si_addr = (caddr_t)rp->r_pc; 992 fault = FLTBOUNDS; 993 } 994 break; 995 996 case T_EXTERRFLT: /* x87 floating point exception pending */ 997 /* check if we took a kernel trap on behalf of user */ 998 { 999 extern void ndptrap_frstor(void); 1000 if (rp->r_pc != (uintptr_t)ndptrap_frstor) { 1001 sti(); /* T_EXTERRFLT comes in via cmninttrap */ 1002 (void) die(type, rp, addr, cpuid); 1003 } 1004 type |= USER; 1005 } 1006 /*FALLTHROUGH*/ 1007 1008 case T_EXTERRFLT + USER: /* x87 floating point exception pending */ 1009 if (tudebug && tudebugfpe) 1010 showregs(type, rp, addr); 1011 if (sicode = fpexterrflt(rp)) { 1012 siginfo.si_signo = SIGFPE; 1013 siginfo.si_code = sicode; 1014 siginfo.si_addr = (caddr_t)rp->r_pc; 1015 fault = FLTFPE; 1016 } 1017 break; 1018 1019 case T_SIMDFPE + USER: /* SSE and SSE2 exceptions */ 1020 if (tudebug && tudebugsse) 1021 showregs(type, rp, addr); 1022 if ((x86_feature & (X86_SSE|X86_SSE2)) == 0) { 1023 /* 1024 * There are rumours that some user instructions 1025 * on older CPUs can cause this trap to occur; in 1026 * which case send a SIGILL instead of a SIGFPE. 1027 */ 1028 siginfo.si_signo = SIGILL; 1029 siginfo.si_code = ILL_ILLTRP; 1030 siginfo.si_addr = (caddr_t)rp->r_pc; 1031 siginfo.si_trapno = type & ~USER; 1032 fault = FLTILL; 1033 } else if ((sicode = fpsimderrflt(rp)) != 0) { 1034 siginfo.si_signo = SIGFPE; 1035 siginfo.si_code = sicode; 1036 siginfo.si_addr = (caddr_t)rp->r_pc; 1037 fault = FLTFPE; 1038 } 1039 1040 sti(); /* The SIMD exception comes in via cmninttrap */ 1041 break; 1042 1043 case T_BPTFLT: /* breakpoint trap */ 1044 /* 1045 * Kernel breakpoint traps should only happen when kmdb is 1046 * active, and even then, it'll have interposed on the IDT, so 1047 * control won't get here. If it does, we've hit a breakpoint 1048 * without the debugger, which is very strange, and very 1049 * fatal. 1050 */ 1051 if (tudebug && tudebugbpt) 1052 showregs(type, rp, (caddr_t)0); 1053 1054 (void) die(type, rp, addr, cpuid); 1055 break; 1056 1057 case T_SGLSTP: /* single step/hw breakpoint exception */ 1058 1059 /* Now evaluate how we got here */ 1060 if (lwp != NULL && (lwp->lwp_pcb.pcb_drstat & DR_SINGLESTEP)) { 1061 /* 1062 * i386 single-steps even through lcalls which 1063 * change the privilege level. So we take a trap at 1064 * the first instruction in privileged mode. 1065 * 1066 * Set a flag to indicate that upon completion of 1067 * the system call, deal with the single-step trap. 1068 * 1069 * The same thing happens for sysenter, too. 1070 */ 1071 singlestep_twiddle = 0; 1072 if (rp->r_pc == (uintptr_t)sys_sysenter || 1073 rp->r_pc == (uintptr_t)brand_sys_sysenter) { 1074 singlestep_twiddle = 1; 1075 #if defined(__amd64) 1076 /* 1077 * Since we are already on the kernel's 1078 * %gs, on 64-bit systems the sysenter case 1079 * needs to adjust the pc to avoid 1080 * executing the swapgs instruction at the 1081 * top of the handler. 1082 */ 1083 if (rp->r_pc == (uintptr_t)sys_sysenter) 1084 rp->r_pc = (uintptr_t) 1085 _sys_sysenter_post_swapgs; 1086 else 1087 rp->r_pc = (uintptr_t) 1088 _brand_sys_sysenter_post_swapgs; 1089 #endif 1090 } 1091 #if defined(__i386) 1092 else if (rp->r_pc == (uintptr_t)sys_call || 1093 rp->r_pc == (uintptr_t)brand_sys_call) { 1094 singlestep_twiddle = 1; 1095 } 1096 #endif 1097 else { 1098 /* not on sysenter/syscall; uregs available */ 1099 if (tudebug && tudebugbpt) 1100 showregs(type, rp, (caddr_t)0); 1101 } 1102 if (singlestep_twiddle) { 1103 rp->r_ps &= ~PS_T; /* turn off trace */ 1104 lwp->lwp_pcb.pcb_flags |= DEBUG_PENDING; 1105 ct->t_post_sys = 1; 1106 aston(curthread); 1107 goto cleanup; 1108 } 1109 } 1110 /* XXX - needs review on debugger interface? */ 1111 if (boothowto & RB_DEBUG) 1112 debug_enter((char *)NULL); 1113 else 1114 (void) die(type, rp, addr, cpuid); 1115 break; 1116 1117 case T_NMIFLT: /* NMI interrupt */ 1118 printf("Unexpected NMI in system mode\n"); 1119 goto cleanup; 1120 1121 case T_NMIFLT + USER: /* NMI interrupt */ 1122 printf("Unexpected NMI in user mode\n"); 1123 break; 1124 1125 case T_GPFLT: /* general protection violation */ 1126 /* 1127 * Any #GP that occurs during an on_trap .. no_trap bracket 1128 * with OT_DATA_ACCESS or OT_SEGMENT_ACCESS protection, 1129 * or in a on_fault .. no_fault bracket, is forgiven 1130 * and we trampoline. This protection is given regardless 1131 * of whether we are 32/64 bit etc - if a distinction is 1132 * required then define new on_trap protection types. 1133 * 1134 * On amd64, we can get a #gp from referencing addresses 1135 * in the virtual address hole e.g. from a copyin or in 1136 * update_sregs while updating user segment registers. 1137 * 1138 * On the 32-bit hypervisor we could also generate one in 1139 * mfn_to_pfn by reaching around or into where the hypervisor 1140 * lives which is protected by segmentation. 1141 */ 1142 1143 /* 1144 * If we're under on_trap() protection (see <sys/ontrap.h>), 1145 * set ot_trap and trampoline back to the on_trap() call site 1146 * for OT_DATA_ACCESS or OT_SEGMENT_ACCESS. 1147 */ 1148 if (ct->t_ontrap != NULL) { 1149 int ttype = ct->t_ontrap->ot_prot & 1150 (OT_DATA_ACCESS | OT_SEGMENT_ACCESS); 1151 1152 if (ttype != 0) { 1153 ct->t_ontrap->ot_trap |= ttype; 1154 if (tudebug) 1155 showregs(type, rp, (caddr_t)0); 1156 rp->r_pc = ct->t_ontrap->ot_trampoline; 1157 goto cleanup; 1158 } 1159 } 1160 1161 /* 1162 * If we're under lofault protection (copyin etc.), 1163 * longjmp back to lofault with an EFAULT. 1164 */ 1165 if (ct->t_lofault) { 1166 /* 1167 * Fault is not resolvable, so just return to lofault 1168 */ 1169 if (lodebug) { 1170 showregs(type, rp, addr); 1171 traceregs(rp); 1172 } 1173 rp->r_r0 = EFAULT; 1174 rp->r_pc = ct->t_lofault; 1175 goto cleanup; 1176 } 1177 1178 /* 1179 * We fall through to the next case, which repeats 1180 * the OT_SEGMENT_ACCESS check which we've already 1181 * done, so we'll always fall through to the 1182 * T_STKFLT case. 1183 */ 1184 /*FALLTHROUGH*/ 1185 case T_SEGFLT: /* segment not present fault */ 1186 /* 1187 * One example of this is #NP in update_sregs while 1188 * attempting to update a user segment register 1189 * that points to a descriptor that is marked not 1190 * present. 1191 */ 1192 if (ct->t_ontrap != NULL && 1193 ct->t_ontrap->ot_prot & OT_SEGMENT_ACCESS) { 1194 ct->t_ontrap->ot_trap |= OT_SEGMENT_ACCESS; 1195 if (tudebug) 1196 showregs(type, rp, (caddr_t)0); 1197 rp->r_pc = ct->t_ontrap->ot_trampoline; 1198 goto cleanup; 1199 } 1200 /*FALLTHROUGH*/ 1201 case T_STKFLT: /* stack fault */ 1202 case T_TSSFLT: /* invalid TSS fault */ 1203 if (tudebug) 1204 showregs(type, rp, (caddr_t)0); 1205 if (kern_gpfault(rp)) 1206 (void) die(type, rp, addr, cpuid); 1207 goto cleanup; 1208 1209 /* 1210 * ONLY 32-bit PROCESSES can USE a PRIVATE LDT! 64-bit apps 1211 * should have no need for them, so we put a stop to it here. 1212 * 1213 * So: not-present fault is ONLY valid for 32-bit processes with 1214 * a private LDT trying to do a system call. Emulate it. 1215 * 1216 * #gp fault is ONLY valid for 32-bit processes also, which DO NOT 1217 * have a private LDT, and are trying to do a system call. Emulate it. 1218 */ 1219 1220 case T_SEGFLT + USER: /* segment not present fault */ 1221 case T_GPFLT + USER: /* general protection violation */ 1222 #ifdef _SYSCALL32_IMPL 1223 if (p->p_model != DATAMODEL_NATIVE) { 1224 #endif /* _SYSCALL32_IMPL */ 1225 if (instr_is_lcall_syscall((caddr_t)rp->r_pc)) { 1226 if (type == T_SEGFLT + USER) 1227 ASSERT(p->p_ldt != NULL); 1228 1229 if ((p->p_ldt == NULL && type == T_GPFLT + USER) || 1230 type == T_SEGFLT + USER) { 1231 1232 /* 1233 * The user attempted a system call via the obsolete 1234 * call gate mechanism. Because the process doesn't have 1235 * an LDT (i.e. the ldtr contains 0), a #gp results. 1236 * Emulate the syscall here, just as we do above for a 1237 * #np trap. 1238 */ 1239 1240 /* 1241 * Since this is a not-present trap, rp->r_pc points to 1242 * the trapping lcall instruction. We need to bump it 1243 * to the next insn so the app can continue on. 1244 */ 1245 rp->r_pc += LCALLSIZE; 1246 lwp->lwp_regs = rp; 1247 1248 /* 1249 * Normally the microstate of the LWP is forced back to 1250 * LMS_USER by the syscall handlers. Emulate that 1251 * behavior here. 1252 */ 1253 mstate = LMS_USER; 1254 1255 dosyscall(); 1256 goto out; 1257 } 1258 } 1259 #ifdef _SYSCALL32_IMPL 1260 } 1261 #endif /* _SYSCALL32_IMPL */ 1262 /* 1263 * If the current process is using a private LDT and the 1264 * trapping instruction is sysenter, the sysenter instruction 1265 * has been disabled on the CPU because it destroys segment 1266 * registers. If this is the case, rewrite the instruction to 1267 * be a safe system call and retry it. If this occurs on a CPU 1268 * which doesn't even support sysenter, the result of all of 1269 * this will be to emulate that particular instruction. 1270 */ 1271 if (p->p_ldt != NULL && 1272 ldt_rewrite_syscall(rp, p, X86_SEP)) 1273 goto out; 1274 1275 /*FALLTHROUGH*/ 1276 1277 case T_BOUNDFLT + USER: /* bound fault */ 1278 case T_STKFLT + USER: /* stack fault */ 1279 case T_TSSFLT + USER: /* invalid TSS fault */ 1280 if (tudebug) 1281 showregs(type, rp, (caddr_t)0); 1282 siginfo.si_signo = SIGSEGV; 1283 siginfo.si_code = SEGV_MAPERR; 1284 siginfo.si_addr = (caddr_t)rp->r_pc; 1285 fault = FLTBOUNDS; 1286 break; 1287 1288 case T_ALIGNMENT + USER: /* user alignment error (486) */ 1289 if (tudebug) 1290 showregs(type, rp, (caddr_t)0); 1291 bzero(&siginfo, sizeof (siginfo)); 1292 siginfo.si_signo = SIGBUS; 1293 siginfo.si_code = BUS_ADRALN; 1294 siginfo.si_addr = (caddr_t)rp->r_pc; 1295 fault = FLTACCESS; 1296 break; 1297 1298 case T_SGLSTP + USER: /* single step/hw breakpoint exception */ 1299 if (tudebug && tudebugbpt) 1300 showregs(type, rp, (caddr_t)0); 1301 1302 /* Was it single-stepping? */ 1303 if (lwp->lwp_pcb.pcb_drstat & DR_SINGLESTEP) { 1304 pcb_t *pcb = &lwp->lwp_pcb; 1305 1306 rp->r_ps &= ~PS_T; 1307 /* 1308 * If both NORMAL_STEP and WATCH_STEP are in effect, 1309 * give precedence to WATCH_STEP. If neither is set, 1310 * user must have set the PS_T bit in %efl; treat this 1311 * as NORMAL_STEP. 1312 */ 1313 if ((fault = undo_watch_step(&siginfo)) == 0 && 1314 ((pcb->pcb_flags & NORMAL_STEP) || 1315 !(pcb->pcb_flags & WATCH_STEP))) { 1316 siginfo.si_signo = SIGTRAP; 1317 siginfo.si_code = TRAP_TRACE; 1318 siginfo.si_addr = (caddr_t)rp->r_pc; 1319 fault = FLTTRACE; 1320 } 1321 pcb->pcb_flags &= ~(NORMAL_STEP|WATCH_STEP); 1322 } else { 1323 cmn_err(CE_WARN, 1324 "Unexpected INT 1 in user mode, dr6=%lx", 1325 lwp->lwp_pcb.pcb_drstat); 1326 } 1327 break; 1328 1329 case T_BPTFLT + USER: /* breakpoint trap */ 1330 if (tudebug && tudebugbpt) 1331 showregs(type, rp, (caddr_t)0); 1332 /* 1333 * int 3 (the breakpoint instruction) leaves the pc referring 1334 * to the address one byte after the breakpointed address. 1335 * If the P_PR_BPTADJ flag has been set via /proc, We adjust 1336 * it back so it refers to the breakpointed address. 1337 */ 1338 if (p->p_proc_flag & P_PR_BPTADJ) 1339 rp->r_pc--; 1340 siginfo.si_signo = SIGTRAP; 1341 siginfo.si_code = TRAP_BRKPT; 1342 siginfo.si_addr = (caddr_t)rp->r_pc; 1343 fault = FLTBPT; 1344 break; 1345 1346 case T_AST: 1347 /* 1348 * This occurs only after the cs register has been made to 1349 * look like a kernel selector, either through debugging or 1350 * possibly by functions like setcontext(). The thread is 1351 * about to cause a general protection fault at common_iret() 1352 * in locore. We let that happen immediately instead of 1353 * doing the T_AST processing. 1354 */ 1355 goto cleanup; 1356 1357 case T_AST + USER: /* profiling, resched, h/w error pseudo trap */ 1358 if (lwp->lwp_pcb.pcb_flags & ASYNC_HWERR) { 1359 proc_t *p = ttoproc(curthread); 1360 extern void print_msg_hwerr(ctid_t ct_id, proc_t *p); 1361 1362 lwp->lwp_pcb.pcb_flags &= ~ASYNC_HWERR; 1363 print_msg_hwerr(p->p_ct_process->conp_contract.ct_id, 1364 p); 1365 contract_process_hwerr(p->p_ct_process, p); 1366 siginfo.si_signo = SIGKILL; 1367 siginfo.si_code = SI_NOINFO; 1368 } else if (lwp->lwp_pcb.pcb_flags & CPC_OVERFLOW) { 1369 lwp->lwp_pcb.pcb_flags &= ~CPC_OVERFLOW; 1370 if (kcpc_overflow_ast()) { 1371 /* 1372 * Signal performance counter overflow 1373 */ 1374 if (tudebug) 1375 showregs(type, rp, (caddr_t)0); 1376 bzero(&siginfo, sizeof (siginfo)); 1377 siginfo.si_signo = SIGEMT; 1378 siginfo.si_code = EMT_CPCOVF; 1379 siginfo.si_addr = (caddr_t)rp->r_pc; 1380 fault = FLTCPCOVF; 1381 } 1382 } 1383 1384 break; 1385 } 1386 1387 /* 1388 * We can't get here from a system trap 1389 */ 1390 ASSERT(type & USER); 1391 1392 if (fault) { 1393 /* We took a fault so abort single step. */ 1394 lwp->lwp_pcb.pcb_flags &= ~(NORMAL_STEP|WATCH_STEP); 1395 /* 1396 * Remember the fault and fault adddress 1397 * for real-time (SIGPROF) profiling. 1398 */ 1399 lwp->lwp_lastfault = fault; 1400 lwp->lwp_lastfaddr = siginfo.si_addr; 1401 1402 DTRACE_PROC2(fault, int, fault, ksiginfo_t *, &siginfo); 1403 1404 /* 1405 * If a debugger has declared this fault to be an 1406 * event of interest, stop the lwp. Otherwise just 1407 * deliver the associated signal. 1408 */ 1409 if (siginfo.si_signo != SIGKILL && 1410 prismember(&p->p_fltmask, fault) && 1411 stop_on_fault(fault, &siginfo) == 0) 1412 siginfo.si_signo = 0; 1413 } 1414 1415 if (siginfo.si_signo) 1416 trapsig(&siginfo, (fault != FLTFPE && fault != FLTCPCOVF)); 1417 1418 if (lwp->lwp_oweupc) 1419 profil_tick(rp->r_pc); 1420 1421 if (ct->t_astflag | ct->t_sig_check) { 1422 /* 1423 * Turn off the AST flag before checking all the conditions that 1424 * may have caused an AST. This flag is on whenever a signal or 1425 * unusual condition should be handled after the next trap or 1426 * syscall. 1427 */ 1428 astoff(ct); 1429 /* 1430 * If a single-step trap occurred on a syscall (see above) 1431 * recognize it now. Do this before checking for signals 1432 * because deferred_singlestep_trap() may generate a SIGTRAP to 1433 * the LWP or may otherwise mark the LWP to call issig(FORREAL). 1434 */ 1435 if (lwp->lwp_pcb.pcb_flags & DEBUG_PENDING) 1436 deferred_singlestep_trap((caddr_t)rp->r_pc); 1437 1438 ct->t_sig_check = 0; 1439 1440 mutex_enter(&p->p_lock); 1441 if (curthread->t_proc_flag & TP_CHANGEBIND) { 1442 timer_lwpbind(); 1443 curthread->t_proc_flag &= ~TP_CHANGEBIND; 1444 } 1445 mutex_exit(&p->p_lock); 1446 1447 /* 1448 * for kaio requests that are on the per-process poll queue, 1449 * aiop->aio_pollq, they're AIO_POLL bit is set, the kernel 1450 * should copyout their result_t to user memory. by copying 1451 * out the result_t, the user can poll on memory waiting 1452 * for the kaio request to complete. 1453 */ 1454 if (p->p_aio) 1455 aio_cleanup(0); 1456 /* 1457 * If this LWP was asked to hold, call holdlwp(), which will 1458 * stop. holdlwps() sets this up and calls pokelwps() which 1459 * sets the AST flag. 1460 * 1461 * Also check TP_EXITLWP, since this is used by fresh new LWPs 1462 * through lwp_rtt(). That flag is set if the lwp_create(2) 1463 * syscall failed after creating the LWP. 1464 */ 1465 if (ISHOLD(p)) 1466 holdlwp(); 1467 1468 /* 1469 * All code that sets signals and makes ISSIG evaluate true must 1470 * set t_astflag afterwards. 1471 */ 1472 if (ISSIG_PENDING(ct, lwp, p)) { 1473 if (issig(FORREAL)) 1474 psig(); 1475 ct->t_sig_check = 1; 1476 } 1477 1478 if (ct->t_rprof != NULL) { 1479 realsigprof(0, 0, 0); 1480 ct->t_sig_check = 1; 1481 } 1482 1483 /* 1484 * /proc can't enable/disable the trace bit itself 1485 * because that could race with the call gate used by 1486 * system calls via "lcall". If that happened, an 1487 * invalid EFLAGS would result. prstep()/prnostep() 1488 * therefore schedule an AST for the purpose. 1489 */ 1490 if (lwp->lwp_pcb.pcb_flags & REQUEST_STEP) { 1491 lwp->lwp_pcb.pcb_flags &= ~REQUEST_STEP; 1492 rp->r_ps |= PS_T; 1493 } 1494 if (lwp->lwp_pcb.pcb_flags & REQUEST_NOSTEP) { 1495 lwp->lwp_pcb.pcb_flags &= ~REQUEST_NOSTEP; 1496 rp->r_ps &= ~PS_T; 1497 } 1498 } 1499 1500 out: /* We can't get here from a system trap */ 1501 ASSERT(type & USER); 1502 1503 if (ISHOLD(p)) 1504 holdlwp(); 1505 1506 /* 1507 * Set state to LWP_USER here so preempt won't give us a kernel 1508 * priority if it occurs after this point. Call CL_TRAPRET() to 1509 * restore the user-level priority. 1510 * 1511 * It is important that no locks (other than spinlocks) be entered 1512 * after this point before returning to user mode (unless lwp_state 1513 * is set back to LWP_SYS). 1514 */ 1515 lwp->lwp_state = LWP_USER; 1516 1517 if (ct->t_trapret) { 1518 ct->t_trapret = 0; 1519 thread_lock(ct); 1520 CL_TRAPRET(ct); 1521 thread_unlock(ct); 1522 } 1523 if (CPU->cpu_runrun || curthread->t_schedflag & TS_ANYWAITQ) 1524 preempt(); 1525 prunstop(); 1526 (void) new_mstate(ct, mstate); 1527 1528 /* Kernel probe */ 1529 TNF_PROBE_1(thread_state, "thread", /* CSTYLED */, 1530 tnf_microstate, state, LMS_USER); 1531 1532 return; 1533 1534 cleanup: /* system traps end up here */ 1535 ASSERT(!(type & USER)); 1536 } 1537 1538 /* 1539 * Patch non-zero to disable preemption of threads in the kernel. 1540 */ 1541 int IGNORE_KERNEL_PREEMPTION = 0; /* XXX - delete this someday */ 1542 1543 struct kpreempt_cnts { /* kernel preemption statistics */ 1544 int kpc_idle; /* executing idle thread */ 1545 int kpc_intr; /* executing interrupt thread */ 1546 int kpc_clock; /* executing clock thread */ 1547 int kpc_blocked; /* thread has blocked preemption (t_preempt) */ 1548 int kpc_notonproc; /* thread is surrendering processor */ 1549 int kpc_inswtch; /* thread has ratified scheduling decision */ 1550 int kpc_prilevel; /* processor interrupt level is too high */ 1551 int kpc_apreempt; /* asynchronous preemption */ 1552 int kpc_spreempt; /* synchronous preemption */ 1553 } kpreempt_cnts; 1554 1555 /* 1556 * kernel preemption: forced rescheduling, preempt the running kernel thread. 1557 * the argument is old PIL for an interrupt, 1558 * or the distingished value KPREEMPT_SYNC. 1559 */ 1560 void 1561 kpreempt(int asyncspl) 1562 { 1563 kthread_t *ct = curthread; 1564 1565 if (IGNORE_KERNEL_PREEMPTION) { 1566 aston(CPU->cpu_dispthread); 1567 return; 1568 } 1569 1570 /* 1571 * Check that conditions are right for kernel preemption 1572 */ 1573 do { 1574 if (ct->t_preempt) { 1575 /* 1576 * either a privileged thread (idle, panic, interrupt) 1577 * or will check when t_preempt is lowered 1578 * We need to specifically handle the case where 1579 * the thread is in the middle of swtch (resume has 1580 * been called) and has its t_preempt set 1581 * [idle thread and a thread which is in kpreempt 1582 * already] and then a high priority thread is 1583 * available in the local dispatch queue. 1584 * In this case the resumed thread needs to take a 1585 * trap so that it can call kpreempt. We achieve 1586 * this by using siron(). 1587 * How do we detect this condition: 1588 * idle thread is running and is in the midst of 1589 * resume: curthread->t_pri == -1 && CPU->dispthread 1590 * != CPU->thread 1591 * Need to ensure that this happens only at high pil 1592 * resume is called at high pil 1593 * Only in resume_from_idle is the pil changed. 1594 */ 1595 if (ct->t_pri < 0) { 1596 kpreempt_cnts.kpc_idle++; 1597 if (CPU->cpu_dispthread != CPU->cpu_thread) 1598 siron(); 1599 } else if (ct->t_flag & T_INTR_THREAD) { 1600 kpreempt_cnts.kpc_intr++; 1601 if (ct->t_pil == CLOCK_LEVEL) 1602 kpreempt_cnts.kpc_clock++; 1603 } else { 1604 kpreempt_cnts.kpc_blocked++; 1605 if (CPU->cpu_dispthread != CPU->cpu_thread) 1606 siron(); 1607 } 1608 aston(CPU->cpu_dispthread); 1609 return; 1610 } 1611 if (ct->t_state != TS_ONPROC || 1612 ct->t_disp_queue != CPU->cpu_disp) { 1613 /* this thread will be calling swtch() shortly */ 1614 kpreempt_cnts.kpc_notonproc++; 1615 if (CPU->cpu_thread != CPU->cpu_dispthread) { 1616 /* already in swtch(), force another */ 1617 kpreempt_cnts.kpc_inswtch++; 1618 siron(); 1619 } 1620 return; 1621 } 1622 if (getpil() >= DISP_LEVEL) { 1623 /* 1624 * We can't preempt this thread if it is at 1625 * a PIL >= DISP_LEVEL since it may be holding 1626 * a spin lock (like sched_lock). 1627 */ 1628 siron(); /* check back later */ 1629 kpreempt_cnts.kpc_prilevel++; 1630 return; 1631 } 1632 if (!interrupts_enabled()) { 1633 /* 1634 * Can't preempt while running with ints disabled 1635 */ 1636 kpreempt_cnts.kpc_prilevel++; 1637 return; 1638 } 1639 if (asyncspl != KPREEMPT_SYNC) 1640 kpreempt_cnts.kpc_apreempt++; 1641 else 1642 kpreempt_cnts.kpc_spreempt++; 1643 1644 ct->t_preempt++; 1645 preempt(); 1646 ct->t_preempt--; 1647 } while (CPU->cpu_kprunrun); 1648 } 1649 1650 /* 1651 * Print out debugging info. 1652 */ 1653 static void 1654 showregs(uint_t type, struct regs *rp, caddr_t addr) 1655 { 1656 int s; 1657 1658 s = spl7(); 1659 type &= ~USER; 1660 if (PTOU(curproc)->u_comm[0]) 1661 printf("%s: ", PTOU(curproc)->u_comm); 1662 if (type < TRAP_TYPES) 1663 printf("#%s %s\n", trap_type_mnemonic[type], trap_type[type]); 1664 else 1665 switch (type) { 1666 case T_SYSCALL: 1667 printf("Syscall Trap:\n"); 1668 break; 1669 case T_AST: 1670 printf("AST\n"); 1671 break; 1672 default: 1673 printf("Bad Trap = %d\n", type); 1674 break; 1675 } 1676 if (type == T_PGFLT) { 1677 printf("Bad %s fault at addr=0x%lx\n", 1678 USERMODE(rp->r_cs) ? "user": "kernel", (uintptr_t)addr); 1679 } else if (addr) { 1680 printf("addr=0x%lx\n", (uintptr_t)addr); 1681 } 1682 1683 printf("pid=%d, pc=0x%lx, sp=0x%lx, eflags=0x%lx\n", 1684 (ttoproc(curthread) && ttoproc(curthread)->p_pidp) ? 1685 ttoproc(curthread)->p_pid : 0, rp->r_pc, rp->r_sp, rp->r_ps); 1686 1687 #if defined(__lint) 1688 /* 1689 * this clause can be deleted when lint bug 4870403 is fixed 1690 * (lint thinks that bit 32 is illegal in a %b format string) 1691 */ 1692 printf("cr0: %x cr4: %b\n", 1693 (uint_t)getcr0(), (uint_t)getcr4(), FMT_CR4); 1694 #else 1695 printf("cr0: %b cr4: %b\n", 1696 (uint_t)getcr0(), FMT_CR0, (uint_t)getcr4(), FMT_CR4); 1697 #endif /* __lint */ 1698 1699 printf("cr2: %lx", getcr2()); 1700 #if !defined(__xpv) 1701 printf("cr3: %lx", getcr3()); 1702 #if defined(__amd64) 1703 printf("cr8: %lx\n", getcr8()); 1704 #endif 1705 #endif 1706 printf("\n"); 1707 1708 dumpregs(rp); 1709 splx(s); 1710 } 1711 1712 static void 1713 dumpregs(struct regs *rp) 1714 { 1715 #if defined(__amd64) 1716 const char fmt[] = "\t%3s: %16lx %3s: %16lx %3s: %16lx\n"; 1717 1718 printf(fmt, "rdi", rp->r_rdi, "rsi", rp->r_rsi, "rdx", rp->r_rdx); 1719 printf(fmt, "rcx", rp->r_rcx, " r8", rp->r_r8, " r9", rp->r_r9); 1720 printf(fmt, "rax", rp->r_rax, "rbx", rp->r_rbx, "rbp", rp->r_rbp); 1721 printf(fmt, "r10", rp->r_r10, "r11", rp->r_r11, "r12", rp->r_r12); 1722 printf(fmt, "r13", rp->r_r13, "r14", rp->r_r14, "r15", rp->r_r15); 1723 1724 printf(fmt, "fsb", rdmsr(MSR_AMD_FSBASE), "gsb", rdmsr(MSR_AMD_GSBASE), 1725 " ds", rp->r_ds); 1726 printf(fmt, " es", rp->r_es, " fs", rp->r_fs, " gs", rp->r_gs); 1727 1728 printf(fmt, "trp", rp->r_trapno, "err", rp->r_err, "rip", rp->r_rip); 1729 printf(fmt, " cs", rp->r_cs, "rfl", rp->r_rfl, "rsp", rp->r_rsp); 1730 1731 printf("\t%3s: %16lx\n", " ss", rp->r_ss); 1732 1733 #elif defined(__i386) 1734 const char fmt[] = "\t%3s: %8lx %3s: %8lx %3s: %8lx %3s: %8lx\n"; 1735 1736 printf(fmt, " gs", rp->r_gs, " fs", rp->r_fs, 1737 " es", rp->r_es, " ds", rp->r_ds); 1738 printf(fmt, "edi", rp->r_edi, "esi", rp->r_esi, 1739 "ebp", rp->r_ebp, "esp", rp->r_esp); 1740 printf(fmt, "ebx", rp->r_ebx, "edx", rp->r_edx, 1741 "ecx", rp->r_ecx, "eax", rp->r_eax); 1742 printf(fmt, "trp", rp->r_trapno, "err", rp->r_err, 1743 "eip", rp->r_eip, " cs", rp->r_cs); 1744 printf("\t%3s: %8lx %3s: %8lx %3s: %8lx\n", 1745 "efl", rp->r_efl, "usp", rp->r_uesp, " ss", rp->r_ss); 1746 1747 #endif /* __i386 */ 1748 } 1749 1750 /* 1751 * Test to see if the instruction is iret on i386 or iretq on amd64. 1752 * 1753 * On the hypervisor we can only test for nopop_sys_rtt_syscall. If true 1754 * then we are in the context of hypervisor's failsafe handler because it 1755 * tried to iret and failed due to a bad selector. See xen_failsafe_callback. 1756 */ 1757 static int 1758 instr_is_iret(caddr_t pc) 1759 { 1760 1761 #if defined(__xpv) 1762 extern void nopop_sys_rtt_syscall(void); 1763 return ((pc == (caddr_t)nopop_sys_rtt_syscall) ? 1 : 0); 1764 1765 #else 1766 1767 #if defined(__amd64) 1768 static const uint8_t iret_insn[2] = { 0x48, 0xcf }; /* iretq */ 1769 1770 #elif defined(__i386) 1771 static const uint8_t iret_insn[1] = { 0xcf }; /* iret */ 1772 #endif /* __i386 */ 1773 return (bcmp(pc, iret_insn, sizeof (iret_insn)) == 0); 1774 1775 #endif /* __xpv */ 1776 } 1777 1778 #if defined(__i386) 1779 1780 /* 1781 * Test to see if the instruction is part of __SEGREGS_POP 1782 * 1783 * Note carefully the appallingly awful dependency between 1784 * the instruction sequence used in __SEGREGS_POP and these 1785 * instructions encoded here. 1786 */ 1787 static int 1788 instr_is_segregs_pop(caddr_t pc) 1789 { 1790 static const uint8_t movw_0_esp_gs[4] = { 0x8e, 0x6c, 0x24, 0x0 }; 1791 static const uint8_t movw_4_esp_fs[4] = { 0x8e, 0x64, 0x24, 0x4 }; 1792 static const uint8_t movw_8_esp_es[4] = { 0x8e, 0x44, 0x24, 0x8 }; 1793 static const uint8_t movw_c_esp_ds[4] = { 0x8e, 0x5c, 0x24, 0xc }; 1794 1795 if (bcmp(pc, movw_0_esp_gs, sizeof (movw_0_esp_gs)) == 0 || 1796 bcmp(pc, movw_4_esp_fs, sizeof (movw_4_esp_fs)) == 0 || 1797 bcmp(pc, movw_8_esp_es, sizeof (movw_8_esp_es)) == 0 || 1798 bcmp(pc, movw_c_esp_ds, sizeof (movw_c_esp_ds)) == 0) 1799 return (1); 1800 1801 return (0); 1802 } 1803 1804 #endif /* __i386 */ 1805 1806 /* 1807 * Test to see if the instruction is part of _sys_rtt. 1808 * 1809 * Again on the hypervisor if we try to IRET to user land with a bad code 1810 * or stack selector we will get vectored through xen_failsafe_callback. 1811 * In which case we assume we got here via _sys_rtt since we only allow 1812 * IRET to user land to take place in _sys_rtt. 1813 */ 1814 static int 1815 instr_is_sys_rtt(caddr_t pc) 1816 { 1817 extern void _sys_rtt(), _sys_rtt_end(); 1818 1819 if ((uintptr_t)pc < (uintptr_t)_sys_rtt || 1820 (uintptr_t)pc > (uintptr_t)_sys_rtt_end) 1821 return (0); 1822 1823 return (1); 1824 } 1825 1826 /* 1827 * Handle #gp faults in kernel mode. 1828 * 1829 * One legitimate way this can happen is if we attempt to update segment 1830 * registers to naughty values on the way out of the kernel. 1831 * 1832 * This can happen in a couple of ways: someone - either accidentally or 1833 * on purpose - creates (setcontext(2), lwp_create(2)) or modifies 1834 * (signal(2)) a ucontext that contains silly segment register values. 1835 * Or someone - either accidentally or on purpose - modifies the prgregset_t 1836 * of a subject process via /proc to contain silly segment register values. 1837 * 1838 * (The unfortunate part is that we can end up discovering the bad segment 1839 * register value in the middle of an 'iret' after we've popped most of the 1840 * stack. So it becomes quite difficult to associate an accurate ucontext 1841 * with the lwp, because the act of taking the #gp trap overwrites most of 1842 * what we were going to send the lwp.) 1843 * 1844 * OTOH if it turns out that's -not- the problem, and we're -not- an lwp 1845 * trying to return to user mode and we get a #gp fault, then we need 1846 * to die() -- which will happen if we return non-zero from this routine. 1847 */ 1848 static int 1849 kern_gpfault(struct regs *rp) 1850 { 1851 kthread_t *t = curthread; 1852 proc_t *p = ttoproc(t); 1853 klwp_t *lwp = ttolwp(t); 1854 struct regs tmpregs, *trp = NULL; 1855 caddr_t pc = (caddr_t)rp->r_pc; 1856 int v; 1857 1858 /* 1859 * if we're not an lwp, or in the case of running native the 1860 * pc range is outside _sys_rtt, then we should immediately 1861 * be die()ing horribly. 1862 */ 1863 if (lwp == NULL || !instr_is_sys_rtt(pc)) 1864 return (1); 1865 1866 /* 1867 * So at least we're in the right part of the kernel. 1868 * 1869 * Disassemble the instruction at the faulting pc. 1870 * Once we know what it is, we carefully reconstruct the stack 1871 * based on the order in which the stack is deconstructed in 1872 * _sys_rtt. Ew. 1873 */ 1874 if (instr_is_iret(pc)) { 1875 /* 1876 * We took the #gp while trying to perform the IRET. 1877 * This means that either %cs or %ss are bad. 1878 * All we know for sure is that most of the general 1879 * registers have been restored, including the 1880 * segment registers, and all we have left on the 1881 * topmost part of the lwp's stack are the 1882 * registers that the iretq was unable to consume. 1883 * 1884 * All the rest of the state was crushed by the #gp 1885 * which pushed -its- registers atop our old save area 1886 * (because we had to decrement the stack pointer, sigh) so 1887 * all that we can try and do is to reconstruct the 1888 * crushed frame from the #gp trap frame itself. 1889 */ 1890 trp = &tmpregs; 1891 trp->r_ss = lwptoregs(lwp)->r_ss; 1892 trp->r_sp = lwptoregs(lwp)->r_sp; 1893 trp->r_ps = lwptoregs(lwp)->r_ps; 1894 trp->r_cs = lwptoregs(lwp)->r_cs; 1895 trp->r_pc = lwptoregs(lwp)->r_pc; 1896 bcopy(rp, trp, offsetof(struct regs, r_pc)); 1897 1898 /* 1899 * Validate simple math 1900 */ 1901 ASSERT(trp->r_pc == lwptoregs(lwp)->r_pc); 1902 ASSERT(trp->r_err == rp->r_err); 1903 1904 1905 1906 } 1907 1908 #if defined(__amd64) 1909 if (trp == NULL && lwp->lwp_pcb.pcb_rupdate != 0) { 1910 1911 /* 1912 * This is the common case -- we're trying to load 1913 * a bad segment register value in the only section 1914 * of kernel code that ever loads segment registers. 1915 * 1916 * We don't need to do anything at this point because 1917 * the pcb contains all the pending segment register 1918 * state, and the regs are still intact because we 1919 * didn't adjust the stack pointer yet. Given the fidelity 1920 * of all this, we could conceivably send a signal 1921 * to the lwp, rather than core-ing. 1922 */ 1923 trp = lwptoregs(lwp); 1924 ASSERT((caddr_t)trp == (caddr_t)rp->r_sp); 1925 } 1926 1927 #elif defined(__i386) 1928 1929 if (trp == NULL && instr_is_segregs_pop(pc)) 1930 trp = lwptoregs(lwp); 1931 1932 #endif /* __i386 */ 1933 1934 if (trp == NULL) 1935 return (1); 1936 1937 /* 1938 * If we get to here, we're reasonably confident that we've 1939 * correctly decoded what happened on the way out of the kernel. 1940 * Rewrite the lwp's registers so that we can create a core dump 1941 * the (at least vaguely) represents the mcontext we were 1942 * being asked to restore when things went so terribly wrong. 1943 */ 1944 1945 /* 1946 * Make sure that we have a meaningful %trapno and %err. 1947 */ 1948 trp->r_trapno = rp->r_trapno; 1949 trp->r_err = rp->r_err; 1950 1951 if ((caddr_t)trp != (caddr_t)lwptoregs(lwp)) 1952 bcopy(trp, lwptoregs(lwp), sizeof (*trp)); 1953 1954 1955 mutex_enter(&p->p_lock); 1956 lwp->lwp_cursig = SIGSEGV; 1957 mutex_exit(&p->p_lock); 1958 1959 /* 1960 * Terminate all LWPs but don't discard them. If another lwp beat 1961 * us to the punch by calling exit(), evaporate now. 1962 */ 1963 proc_is_exiting(p); 1964 if (exitlwps(1) != 0) { 1965 mutex_enter(&p->p_lock); 1966 lwp_exit(); 1967 } 1968 1969 if (audit_active) /* audit core dump */ 1970 audit_core_start(SIGSEGV); 1971 v = core(SIGSEGV, B_FALSE); 1972 if (audit_active) /* audit core dump */ 1973 audit_core_finish(v ? CLD_KILLED : CLD_DUMPED); 1974 exit(v ? CLD_KILLED : CLD_DUMPED, SIGSEGV); 1975 return (0); 1976 } 1977 1978 /* 1979 * dump_tss() - Display the TSS structure 1980 */ 1981 1982 #if !defined(__xpv) 1983 #if defined(__amd64) 1984 1985 static void 1986 dump_tss(void) 1987 { 1988 const char tss_fmt[] = "tss.%s:\t0x%p\n"; /* Format string */ 1989 struct tss *tss = CPU->cpu_tss; 1990 1991 printf(tss_fmt, "tss_rsp0", (void *)tss->tss_rsp0); 1992 printf(tss_fmt, "tss_rsp1", (void *)tss->tss_rsp1); 1993 printf(tss_fmt, "tss_rsp2", (void *)tss->tss_rsp2); 1994 1995 printf(tss_fmt, "tss_ist1", (void *)tss->tss_ist1); 1996 printf(tss_fmt, "tss_ist2", (void *)tss->tss_ist2); 1997 printf(tss_fmt, "tss_ist3", (void *)tss->tss_ist3); 1998 printf(tss_fmt, "tss_ist4", (void *)tss->tss_ist4); 1999 printf(tss_fmt, "tss_ist5", (void *)tss->tss_ist5); 2000 printf(tss_fmt, "tss_ist6", (void *)tss->tss_ist6); 2001 printf(tss_fmt, "tss_ist7", (void *)tss->tss_ist7); 2002 } 2003 2004 #elif defined(__i386) 2005 2006 static void 2007 dump_tss(void) 2008 { 2009 const char tss_fmt[] = "tss.%s:\t0x%p\n"; /* Format string */ 2010 struct tss *tss = CPU->cpu_tss; 2011 2012 printf(tss_fmt, "tss_link", (void *)(uintptr_t)tss->tss_link); 2013 printf(tss_fmt, "tss_esp0", (void *)(uintptr_t)tss->tss_esp0); 2014 printf(tss_fmt, "tss_ss0", (void *)(uintptr_t)tss->tss_ss0); 2015 printf(tss_fmt, "tss_esp1", (void *)(uintptr_t)tss->tss_esp1); 2016 printf(tss_fmt, "tss_ss1", (void *)(uintptr_t)tss->tss_ss1); 2017 printf(tss_fmt, "tss_esp2", (void *)(uintptr_t)tss->tss_esp2); 2018 printf(tss_fmt, "tss_ss2", (void *)(uintptr_t)tss->tss_ss2); 2019 printf(tss_fmt, "tss_cr3", (void *)(uintptr_t)tss->tss_cr3); 2020 printf(tss_fmt, "tss_eip", (void *)(uintptr_t)tss->tss_eip); 2021 printf(tss_fmt, "tss_eflags", (void *)(uintptr_t)tss->tss_eflags); 2022 printf(tss_fmt, "tss_eax", (void *)(uintptr_t)tss->tss_eax); 2023 printf(tss_fmt, "tss_ebx", (void *)(uintptr_t)tss->tss_ebx); 2024 printf(tss_fmt, "tss_ecx", (void *)(uintptr_t)tss->tss_ecx); 2025 printf(tss_fmt, "tss_edx", (void *)(uintptr_t)tss->tss_edx); 2026 printf(tss_fmt, "tss_esp", (void *)(uintptr_t)tss->tss_esp); 2027 } 2028 2029 #endif /* __amd64 */ 2030 #endif /* !__xpv */ 2031 2032 #if defined(TRAPTRACE) 2033 2034 int ttrace_nrec = 10; /* number of records to dump out */ 2035 int ttrace_dump_nregs = 0; /* dump out this many records with regs too */ 2036 2037 /* 2038 * Dump out the last ttrace_nrec traptrace records on each CPU 2039 */ 2040 static void 2041 dump_ttrace(void) 2042 { 2043 trap_trace_ctl_t *ttc; 2044 trap_trace_rec_t *rec; 2045 uintptr_t current; 2046 int i, j, k; 2047 int n = NCPU; 2048 #if defined(__amd64) 2049 const char banner[] = 2050 "\ncpu address timestamp " 2051 "type vc handler pc\n"; 2052 const char fmt1[] = "%3d %016lx %12llx "; 2053 #elif defined(__i386) 2054 const char banner[] = 2055 "\ncpu address timestamp type vc handler pc\n"; 2056 const char fmt1[] = "%3d %08lx %12llx "; 2057 #endif 2058 const char fmt2[] = "%4s %3x "; 2059 const char fmt3[] = "%8s "; 2060 2061 if (ttrace_nrec == 0) 2062 return; 2063 2064 printf(banner); 2065 2066 for (i = 0; i < n; i++) { 2067 ttc = &trap_trace_ctl[i]; 2068 if (ttc->ttc_first == NULL) 2069 continue; 2070 2071 current = ttc->ttc_next - sizeof (trap_trace_rec_t); 2072 for (j = 0; j < ttrace_nrec; j++) { 2073 struct sysent *sys; 2074 struct autovec *vec; 2075 extern struct av_head autovect[]; 2076 int type; 2077 ulong_t off; 2078 char *sym, *stype; 2079 2080 if (current < ttc->ttc_first) 2081 current = 2082 ttc->ttc_limit - sizeof (trap_trace_rec_t); 2083 2084 if (current == NULL) 2085 continue; 2086 2087 rec = (trap_trace_rec_t *)current; 2088 2089 if (rec->ttr_stamp == 0) 2090 break; 2091 2092 printf(fmt1, i, (uintptr_t)rec, rec->ttr_stamp); 2093 2094 switch (rec->ttr_marker) { 2095 case TT_SYSCALL: 2096 case TT_SYSENTER: 2097 case TT_SYSC: 2098 case TT_SYSC64: 2099 #if defined(__amd64) 2100 sys = &sysent32[rec->ttr_sysnum]; 2101 switch (rec->ttr_marker) { 2102 case TT_SYSC64: 2103 sys = &sysent[rec->ttr_sysnum]; 2104 /*FALLTHROUGH*/ 2105 #elif defined(__i386) 2106 sys = &sysent[rec->ttr_sysnum]; 2107 switch (rec->ttr_marker) { 2108 case TT_SYSC64: 2109 #endif 2110 case TT_SYSC: 2111 stype = "sysc"; /* syscall */ 2112 break; 2113 case TT_SYSCALL: 2114 stype = "lcal"; /* lcall */ 2115 break; 2116 case TT_SYSENTER: 2117 stype = "syse"; /* sysenter */ 2118 break; 2119 default: 2120 break; 2121 } 2122 printf(fmt2, "sysc", rec->ttr_sysnum); 2123 if (sys != NULL) { 2124 sym = kobj_getsymname( 2125 (uintptr_t)sys->sy_callc, 2126 &off); 2127 if (sym != NULL) 2128 printf(fmt3, sym); 2129 else 2130 printf("%p ", sys->sy_callc); 2131 } else { 2132 printf(fmt3, "unknown"); 2133 } 2134 break; 2135 2136 case TT_INTERRUPT: 2137 printf(fmt2, "intr", rec->ttr_vector); 2138 vec = (&autovect[rec->ttr_vector])->avh_link; 2139 if (vec != NULL) { 2140 sym = kobj_getsymname( 2141 (uintptr_t)vec->av_vector, &off); 2142 if (sym != NULL) 2143 printf(fmt3, sym); 2144 else 2145 printf("%p ", vec->av_vector); 2146 } else { 2147 printf(fmt3, "unknown "); 2148 } 2149 break; 2150 2151 case TT_TRAP: 2152 case TT_EVENT: 2153 type = rec->ttr_regs.r_trapno; 2154 printf(fmt2, "trap", type); 2155 if (type < TRAP_TYPES) 2156 printf(" #%s ", 2157 trap_type_mnemonic[type]); 2158 else 2159 switch (type) { 2160 case T_AST: 2161 printf(fmt3, "ast"); 2162 break; 2163 default: 2164 printf(fmt3, ""); 2165 break; 2166 } 2167 break; 2168 2169 default: 2170 break; 2171 } 2172 2173 sym = kobj_getsymname(rec->ttr_regs.r_pc, &off); 2174 if (sym != NULL) 2175 printf("%s+%lx\n", sym, off); 2176 else 2177 printf("%lx\n", rec->ttr_regs.r_pc); 2178 2179 if (ttrace_dump_nregs-- > 0) { 2180 int s; 2181 2182 if (rec->ttr_marker == TT_INTERRUPT) 2183 printf( 2184 "\t\tipl %x spl %x pri %x\n", 2185 rec->ttr_ipl, 2186 rec->ttr_spl, 2187 rec->ttr_pri); 2188 2189 dumpregs(&rec->ttr_regs); 2190 2191 printf("\t%3s: %p\n\n", " ct", 2192 (void *)rec->ttr_curthread); 2193 2194 /* 2195 * print out the pc stack that we recorded 2196 * at trap time (if any) 2197 */ 2198 for (s = 0; s < rec->ttr_sdepth; s++) { 2199 uintptr_t fullpc; 2200 2201 if (s >= TTR_STACK_DEPTH) { 2202 printf("ttr_sdepth corrupt\n"); 2203 break; 2204 } 2205 2206 fullpc = (uintptr_t)rec->ttr_stack[s]; 2207 2208 sym = kobj_getsymname(fullpc, &off); 2209 if (sym != NULL) 2210 printf("-> %s+0x%lx()\n", 2211 sym, off); 2212 else 2213 printf("-> 0x%lx()\n", fullpc); 2214 } 2215 printf("\n"); 2216 } 2217 current -= sizeof (trap_trace_rec_t); 2218 } 2219 } 2220 } 2221 2222 #endif /* TRAPTRACE */ 2223 2224 void 2225 panic_showtrap(struct panic_trap_info *tip) 2226 { 2227 showregs(tip->trap_type, tip->trap_regs, tip->trap_addr); 2228 2229 #if defined(TRAPTRACE) 2230 dump_ttrace(); 2231 #endif 2232 2233 #if !defined(__xpv) 2234 if (tip->trap_type == T_DBLFLT) 2235 dump_tss(); 2236 #endif 2237 } 2238 2239 void 2240 panic_savetrap(panic_data_t *pdp, struct panic_trap_info *tip) 2241 { 2242 panic_saveregs(pdp, tip->trap_regs); 2243 } 2244
Indexes created Fri Nov 27 03:38:04 UTC 2009
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