1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCIE_IMPL_H 27 #define _SYS_PCIE_IMPL_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/pcie.h> 34 #include <sys/pciev.h> 35 36 #define PCI_GET_BDF(dip) \ 37 PCIE_DIP2BUS(dip)->bus_bdf 38 #define PCI_GET_SEC_BUS(dip) \ 39 PCIE_DIP2BUS(dip)->bus_bdg_secbus 40 #define PCI_GET_PCIE2PCI_SECBUS(dip) \ 41 PCIE_DIP2BUS(dip)->bus_bdg_secbus 42 43 #define DEVI_PORT_TYPE_PCI \ 44 ((PCI_CLASS_BRIDGE << 16) | (PCI_BRIDGE_PCI << 8) | \ 45 PCI_BRIDGE_PCI_IF_PCI2PCI) 46 47 #define PCIE_DIP2BUS(dip) \ 48 (ndi_port_type(dip, B_TRUE, DEVI_PORT_TYPE_PCI) ? \ 49 PCIE_DIP2UPBUS(dip) : \ 50 ndi_port_type(dip, B_FALSE, DEVI_PORT_TYPE_PCI) ? \ 51 PCIE_DIP2DOWNBUS(dip) : NULL) 52 53 #define PCIE_DIP2UPBUS(dip) \ 54 ((pcie_bus_t *)ndi_get_bus_private(dip, B_TRUE)) 55 #define PCIE_DIP2DOWNBUS(dip) \ 56 ((pcie_bus_t *)ndi_get_bus_private(dip, B_FALSE)) 57 #define PCIE_DIP2PFD(dip) (PCIE_DIP2BUS(dip))->bus_pfd 58 #define PCIE_PFD2BUS(pfd_p) pfd_p->pe_bus_p 59 #define PCIE_PFD2DIP(pfd_p) PCIE_PFD2BUS(pfd_p)->bus_dip 60 #define PCIE_BUS2DIP(bus_p) bus_p->bus_dip 61 #define PCIE_BUS2PFD(bus_p) PCIE_DIP2PFD(PCIE_BUS2DIP(bus_p)) 62 #define PCIE_BUS2DOM(bus_p) bus_p->bus_dom 63 #define PCIE_DIP2DOM(dip) PCIE_BUS2DOM(PCIE_DIP2BUS(dip)) 64 65 /* 66 * These macros depend on initialization of type related data in bus_p. 67 */ 68 #define PCIE_IS_PCIE(bus_p) (bus_p->bus_pcie_off) 69 #define PCIE_IS_PCIX(bus_p) (bus_p->bus_pcix_off) 70 #define PCIE_IS_PCI(bus_p) (!PCIE_IS_PCIE(bus_p)) 71 #define PCIE_HAS_AER(bus_p) (bus_p->bus_aer_off) 72 /* IS_ROOT = is RC or RP */ 73 #define PCIE_IS_ROOT(bus_p) (PCIE_IS_RC(bus_p) || PCIE_IS_RP(bus_p)) 74 75 #define PCIE_IS_HOTPLUG_CAPABLE(dip) \ 76 (PCIE_DIP2BUS(dip)->bus_hp_sup_modes) 77 78 #define PCIE_IS_HOTPLUG_ENABLED(dip) \ 79 ((PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_PCI_HP_MODE) || \ 80 (PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_NATIVE_HP_MODE)) 81 82 /* 83 * This is a pseudo pcie "device type", but it's needed to explain describe 84 * nodes such as PX and NPE, which aren't really PCI devices but do control or 85 * interaction with PCI error handling. 86 */ 87 #define PCIE_IS_RC(bus_p) \ 88 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO) 89 #define PCIE_IS_RP(bus_p) \ 90 ((bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) && \ 91 PCIE_IS_PCIE(bus_p)) 92 #define PCIE_IS_SWU(bus_p) \ 93 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_UP) 94 #define PCIE_IS_SWD(bus_p) \ 95 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN) 96 #define PCIE_IS_SW(bus_p) \ 97 (PCIE_IS_SWU(bus_p) || PCIE_IS_SWD(bus_p)) 98 #define PCIE_IS_BDG(bus_p) (bus_p->bus_hdr_type == PCI_HEADER_ONE) 99 #define PCIE_IS_PCI_BDG(bus_p) (PCIE_IS_PCI(bus_p) && PCIE_IS_BDG(bus_p)) 100 #define PCIE_IS_PCIE_BDG(bus_p) \ 101 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) 102 #define PCIE_IS_PCI2PCIE(bus_p) \ 103 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE) 104 #define PCIE_IS_PCIE_SEC(bus_p) \ 105 (PCIE_IS_PCIE(bus_p) && PCIE_IS_BDG(bus_p) && !PCIE_IS_PCIE_BDG(bus_p)) 106 #define PCIX_ECC_VERSION_CHECK(bus_p) \ 107 ((bus_p->bus_ecc_ver == PCI_PCIX_VER_1) || \ 108 (bus_p->bus_ecc_ver == PCI_PCIX_VER_2)) 109 110 #define PCIE_VENID(bus_p) (bus_p->bus_dev_ven_id & 0xffff) 111 #define PCIE_DEVID(bus_p) ((bus_p->bus_dev_ven_id >> 16) & 0xffff) 112 113 /* PCIE Cap/AER shortcuts */ 114 #define PCIE_GET(sz, bus_p, off) \ 115 pci_config_get ## sz(bus_p->bus_cfg_hdl, off) 116 #define PCIE_PUT(sz, bus_p, off, val) \ 117 pci_config_put ## sz(bus_p->bus_cfg_hdl, off, val) 118 #define PCIE_CAP_GET(sz, bus_p, off) \ 119 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcie_off, off) 120 #define PCIE_CAP_PUT(sz, bus_p, off, val) \ 121 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcie_off, off, \ 122 val) 123 #define PCIE_AER_GET(sz, bus_p, off) \ 124 PCI_XCAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_aer_off, off) 125 #define PCIE_AER_PUT(sz, bus_p, off, val) \ 126 PCI_XCAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_aer_off, off, \ 127 val) 128 #define PCIX_CAP_GET(sz, bus_p, off) \ 129 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcix_off, off) 130 #define PCIX_CAP_PUT(sz, bus_p, off, val) \ 131 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcix_off, off, \ 132 val) 133 134 /* Translate PF error return values to DDI_FM values */ 135 #define PF_ERR2DDIFM_ERR(sts) \ 136 (sts & PF_ERR_FATAL_FLAGS ? DDI_FM_FATAL : \ 137 (sts == PF_ERR_NO_ERROR ? DDI_FM_OK : DDI_FM_NONFATAL)) 138 139 /* 140 * The following flag is used for Broadcom 5714/5715 bridge prefetch issue. 141 * This flag will be used both by px and pcieb nexus drivers. 142 */ 143 #define PX_DMAI_FLAGS_MAP_BUFZONE 0x40000 144 145 /* 146 * PCI(e/-X) structures used to to gather and report errors detected by 147 * PCI(e/-X) compliant devices. These registers only contain "dynamic" data. 148 * Static data such as Capability Offsets and Version #s is saved in the parent 149 * private data. 150 */ 151 #define PCI_ERR_REG(pfd_p) pfd_p->pe_pci_regs 152 #define PCI_BDG_ERR_REG(pfd_p) PCI_ERR_REG(pfd_p)->pci_bdg_regs 153 #define PCIX_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcix_regs 154 #define PCIX_ECC_REG(pfd_p) PCIX_ERR_REG(pfd_p)->pcix_ecc_regs 155 #define PCIX_BDG_ERR_REG(pfd_p) pfd_p->pe_pcix_bdg_regs 156 #define PCIX_BDG_ECC_REG(pfd_p, n) PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_ecc_regs[n] 157 #define PCIE_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcie_regs 158 #define PCIE_RP_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_rp_regs 159 #define PCIE_ROOT_FAULT(pfd_p) pfd_p->pe_root_fault 160 #define PCIE_ROOT_EH_SRC(pfd_p) pfd_p->pe_root_eh_src 161 #define PCIE_ADV_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_adv_regs 162 #define PCIE_ADV_HDR(pfd_p, n) PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[n] 163 #define PCIE_ADV_BDG_REG(pfd_p) \ 164 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_bdg_regs 165 #define PCIE_ADV_BDG_HDR(pfd_p, n) PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[n] 166 #define PCIE_ADV_RP_REG(pfd_p) \ 167 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_rp_regs 168 #define PFD_AFFECTED_DEV(pfd_p) pfd_p->pe_affected_dev 169 170 #define PFD_IS_ROOT(pfd_p) PCIE_IS_ROOT(PCIE_PFD2BUS(pfd_p)) 171 #define PFD_IS_RC(pfd_p) PCIE_IS_RC(PCIE_PFD2BUS(pfd_p)) 172 #define PFD_IS_RP(pfd_p) PCIE_IS_RP(PCIE_PFD2BUS(pfd_p)) 173 174 /* bus_hp_mode field */ 175 typedef enum { 176 PCIE_NONE_HP_MODE = 0x0, 177 PCIE_ACPI_HP_MODE = 0x1, 178 PCIE_PCI_HP_MODE = 0x2, 179 PCIE_NATIVE_HP_MODE = 0x4 180 } pcie_hp_mode_t; 181 182 typedef struct pf_pci_bdg_err_regs { 183 uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */ 184 uint16_t pci_bdg_ctrl; /* PCI bridge control reg */ 185 } pf_pci_bdg_err_regs_t; 186 187 typedef struct pf_pci_err_regs { 188 uint16_t pci_err_status; /* pci status register */ 189 uint16_t pci_cfg_comm; /* pci command register */ 190 pf_pci_bdg_err_regs_t *pci_bdg_regs; 191 } pf_pci_err_regs_t; 192 193 typedef struct pf_pcix_ecc_regs { 194 uint32_t pcix_ecc_ctlstat; /* pcix ecc control status reg */ 195 uint32_t pcix_ecc_fstaddr; /* pcix ecc first address reg */ 196 uint32_t pcix_ecc_secaddr; /* pcix ecc second address reg */ 197 uint32_t pcix_ecc_attr; /* pcix ecc attributes reg */ 198 } pf_pcix_ecc_regs_t; 199 200 typedef struct pf_pcix_err_regs { 201 uint16_t pcix_command; /* pcix command register */ 202 uint32_t pcix_status; /* pcix status register */ 203 pf_pcix_ecc_regs_t *pcix_ecc_regs; /* pcix ecc registers */ 204 } pf_pcix_err_regs_t; 205 206 typedef struct pf_pcix_bdg_err_regs { 207 uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */ 208 uint32_t pcix_bdg_stat; /* pcix bridge status reg */ 209 pf_pcix_ecc_regs_t *pcix_bdg_ecc_regs[2]; /* pcix ecc registers */ 210 } pf_pcix_bdg_err_regs_t; 211 212 typedef struct pf_pcie_adv_bdg_err_regs { 213 uint32_t pcie_sue_ctl; /* pcie bridge secondary ue control */ 214 uint32_t pcie_sue_status; /* pcie bridge secondary ue status */ 215 uint32_t pcie_sue_mask; /* pcie bridge secondary ue mask */ 216 uint32_t pcie_sue_sev; /* pcie bridge secondary ue severity */ 217 uint32_t pcie_sue_hdr[4]; /* pcie bridge secondary ue hdr log */ 218 uint32_t pcie_sue_tgt_trans; /* Fault trans type from SAER Logs */ 219 uint64_t pcie_sue_tgt_addr; /* Fault addr from SAER Logs */ 220 pcie_req_id_t pcie_sue_tgt_bdf; /* Fault bdf from SAER Logs */ 221 } pf_pcie_adv_bdg_err_regs_t; 222 223 typedef struct pf_pcie_adv_rp_err_regs { 224 uint32_t pcie_rp_err_status; /* pcie root complex error status reg */ 225 uint32_t pcie_rp_err_cmd; /* pcie root complex error cmd reg */ 226 uint16_t pcie_rp_ce_src_id; /* pcie root complex ce sourpe id */ 227 uint16_t pcie_rp_ue_src_id; /* pcie root complex ue sourpe id */ 228 } pf_pcie_adv_rp_err_regs_t; 229 230 typedef struct pf_pcie_adv_err_regs { 231 uint32_t pcie_adv_ctl; /* pcie advanced control reg */ 232 uint32_t pcie_ue_status; /* pcie ue error status reg */ 233 uint32_t pcie_ue_mask; /* pcie ue error mask reg */ 234 uint32_t pcie_ue_sev; /* pcie ue error severity reg */ 235 uint32_t pcie_ue_hdr[4]; /* pcie ue header log */ 236 uint32_t pcie_ce_status; /* pcie ce error status reg */ 237 uint32_t pcie_ce_mask; /* pcie ce error mask reg */ 238 union { 239 pf_pcie_adv_bdg_err_regs_t *pcie_adv_bdg_regs; /* bdg regs */ 240 pf_pcie_adv_rp_err_regs_t *pcie_adv_rp_regs; /* rp regs */ 241 } pcie_ext; 242 uint32_t pcie_ue_tgt_trans; /* Fault trans type from AER Logs */ 243 uint64_t pcie_ue_tgt_addr; /* Fault addr from AER Logs */ 244 pcie_req_id_t pcie_ue_tgt_bdf; /* Fault bdf from AER Logs */ 245 } pf_pcie_adv_err_regs_t; 246 247 typedef struct pf_pcie_rp_err_regs { 248 uint32_t pcie_rp_status; /* root complex status register */ 249 uint16_t pcie_rp_ctl; /* root complex control register */ 250 } pf_pcie_rp_err_regs_t; 251 252 typedef struct pf_pcie_err_regs { 253 uint16_t pcie_err_status; /* pcie device status register */ 254 uint16_t pcie_err_ctl; /* pcie error control register */ 255 uint32_t pcie_dev_cap; /* pcie device capabilities register */ 256 pf_pcie_rp_err_regs_t *pcie_rp_regs; /* pcie root complex regs */ 257 pf_pcie_adv_err_regs_t *pcie_adv_regs; /* pcie aer regs */ 258 } pf_pcie_err_regs_t; 259 260 typedef enum { 261 PF_INTR_TYPE_NONE = 0, 262 PF_INTR_TYPE_FABRIC = 1, /* Fabric Message */ 263 PF_INTR_TYPE_DATA, /* Data Access Failure, failed loads */ 264 PF_INTR_TYPE_AER, /* Root Port AER MSI */ 265 PF_INTR_TYPE_INTERNAL /* Chip specific internal errors */ 266 } pf_intr_type_t; 267 268 typedef struct pf_root_eh_src { 269 pf_intr_type_t intr_type; 270 void *intr_data; /* Interrupt Data */ 271 } pf_root_eh_src_t; 272 273 typedef struct pf_root_fault { 274 pcie_req_id_t scan_bdf; /* BDF from error logs */ 275 uint64_t scan_addr; /* Addr from error logs */ 276 boolean_t full_scan; /* Option to do a full scan */ 277 } pf_root_fault_t; 278 279 typedef struct pf_data pf_data_t; 280 281 /* 282 * For hot plugged device, these data are init'ed during during probe 283 * For non-hotplugged device, these data are init'ed in pci_autoconfig (on x86), 284 * or in px_attach()(on sparc). 285 * 286 * For root complex the fields are initialized in pcie_rc_init_bus(); 287 * for others part of the fields are initialized in pcie_init_bus(), 288 * and part of fields initialized in pcie_post_init_bus(). See comments 289 * on top of respective functions for details. 290 */ 291 typedef struct pcie_bus { 292 /* Needed for PCI/PCIe fabric error handling */ 293 dev_info_t *bus_dip; 294 dev_info_t *bus_rp_dip; 295 ddi_acc_handle_t bus_cfg_hdl; /* error handling acc hdle */ 296 uint_t bus_fm_flags; 297 uint_t bus_soft_state; 298 299 /* Static PCI/PCIe information */ 300 pcie_req_id_t bus_bdf; 301 pcie_req_id_t bus_rp_bdf; /* BDF of device's Root Port */ 302 uint32_t bus_dev_ven_id; /* device/vendor ID */ 303 uint8_t bus_rev_id; /* revision ID */ 304 uint8_t bus_hdr_type; /* pci header type, see pci.h */ 305 uint16_t bus_dev_type; /* PCI-E dev type, see pcie.h */ 306 uint8_t bus_bdg_secbus; /* Bridge secondary bus num */ 307 uint16_t bus_pcie_off; /* PCIe Capability Offset */ 308 uint16_t bus_aer_off; /* PCIe Advanced Error Offset */ 309 uint16_t bus_pcix_off; /* PCIx Capability Offset */ 310 uint16_t bus_pci_hp_off; /* PCI HP (SHPC) Cap Offset */ 311 uint16_t bus_ecc_ver; /* PCIX ecc version */ 312 pci_bus_range_t bus_bus_range; /* pci bus-range property */ 313 ppb_ranges_t *bus_addr_ranges; /* pci range property */ 314 int bus_addr_entries; /* number of range prop */ 315 pci_regspec_t *bus_assigned_addr; /* "assigned-address" prop */ 316 int bus_assigned_entries; /* number of prop entries */ 317 318 /* Cache of last fault data */ 319 pf_data_t *bus_pfd; 320 pcie_domain_t *bus_dom; 321 322 int bus_mps; /* Maximum Payload Size */ 323 324 void *bus_plat_private; /* Platform specific */ 325 /* Hotplug specific fields */ 326 pcie_hp_mode_t bus_hp_sup_modes; /* HP modes supported */ 327 pcie_hp_mode_t bus_hp_curr_mode; /* HP mode used */ 328 void *bus_hp_ctrl; /* HP bus ctrl data */ 329 int bus_ari; /* ARI device */ 330 331 uint64_t bus_cfgacc_base; /* config space base address */ 332 } pcie_bus_t; 333 334 /* 335 * Data structure to log what devices are affected in relationship to the 336 * severity after all the errors bits have been analyzed. 337 */ 338 #define PF_AFFECTED_ROOT (1 << 0) /* RP/RC is affected */ 339 #define PF_AFFECTED_SELF (1 << 1) /* Reporting Device is affected */ 340 #define PF_AFFECTED_PARENT (1 << 2) /* Parent device is affected */ 341 #define PF_AFFECTED_CHILDREN (1 << 3) /* All children below are affected */ 342 #define PF_AFFECTED_BDF (1 << 4) /* See affected_bdf */ 343 #define PF_AFFECTED_AER (1 << 5) /* See AER Registers */ 344 #define PF_AFFECTED_SAER (1 << 6) /* See SAER Registers */ 345 #define PF_AFFECTED_ADDR (1 << 7) /* Device targeted by addr */ 346 347 #define PF_MAX_AFFECTED_FLAG PF_AFFECTED_ADDR 348 349 typedef struct pf_affected_dev { 350 uint16_t pe_affected_flags; 351 pcie_req_id_t pe_affected_bdf; 352 } pf_affected_dev_t; 353 354 struct pf_data { 355 boolean_t pe_lock; 356 boolean_t pe_valid; 357 uint32_t pe_severity_flags; /* Severity of error */ 358 uint32_t pe_orig_severity_flags; /* Original severity */ 359 pf_affected_dev_t *pe_affected_dev; 360 pcie_bus_t *pe_bus_p; 361 pf_root_fault_t *pe_root_fault; /* Only valid for RC and RP */ 362 pf_root_eh_src_t *pe_root_eh_src; /* Only valid for RC and RP */ 363 pf_pci_err_regs_t *pe_pci_regs; /* PCI error reg */ 364 union { 365 pf_pcix_err_regs_t *pe_pcix_regs; /* PCI-X error reg */ 366 pf_pcie_err_regs_t *pe_pcie_regs; /* PCIe error reg */ 367 } pe_ext; 368 pf_pcix_bdg_err_regs_t *pe_pcix_bdg_regs; /* PCI-X bridge regs */ 369 pf_data_t *pe_prev; /* Next error in queue */ 370 pf_data_t *pe_next; /* Next error in queue */ 371 boolean_t pe_rber_fatal; 372 }; 373 374 /* Information used while handling errors in the fabric. */ 375 typedef struct pf_impl { 376 ddi_fm_error_t *pf_derr; 377 pf_root_fault_t *pf_fault; /* captured fault bdf/addr to scan */ 378 pf_data_t *pf_dq_head_p; /* ptr to fault data queue */ 379 pf_data_t *pf_dq_tail_p; /* ptr pt last fault data q */ 380 uint32_t pf_total; /* total non RC pf_datas */ 381 } pf_impl_t; 382 383 /* bus_fm_flags field */ 384 #define PF_FM_READY (1 << 0) /* bus_fm_lock initialized */ 385 #define PF_FM_IS_NH (1 << 1) /* known as non-hardened */ 386 387 /* 388 * PCIe fabric handle lookup address flags. Used to define what type of 389 * transaction the address is for. These same value are defined again in 390 * fabric-xlate FM module. Do not modify these variables, without modifying 391 * those. 392 */ 393 #define PF_ADDR_DMA (1 << 0) 394 #define PF_ADDR_PIO (1 << 1) 395 #define PF_ADDR_CFG (1 << 2) 396 397 /* PCIe fabric error scanning status flags */ 398 #define PF_SCAN_SUCCESS (1 << 0) 399 #define PF_SCAN_CB_FAILURE (1 << 1) /* hardened device callback failure */ 400 #define PF_SCAN_NO_ERR_IN_CHILD (1 << 2) /* no errors in bridge sec stat reg */ 401 #define PF_SCAN_IN_DQ (1 << 3) /* already present in the faultq */ 402 #define PF_SCAN_DEADLOCK (1 << 4) /* deadlock detected */ 403 #define PF_SCAN_BAD_RESPONSE (1 << 5) /* Incorrect device response */ 404 405 /* PCIe fabric error handling severity return flags */ 406 #define PF_ERR_NO_ERROR (1 << 0) /* No error seen */ 407 #define PF_ERR_CE (1 << 1) /* Correctable Error */ 408 #define PF_ERR_NO_PANIC (1 << 2) /* Error should not panic sys */ 409 #define PF_ERR_MATCHED_DEVICE (1 << 3) /* Error Handled By Device */ 410 #define PF_ERR_MATCHED_RC (1 << 4) /* Error Handled By RC */ 411 #define PF_ERR_MATCHED_PARENT (1 << 5) /* Error Handled By Parent */ 412 #define PF_ERR_PANIC (1 << 6) /* Error should panic system */ 413 #define PF_ERR_PANIC_DEADLOCK (1 << 7) /* deadlock detected */ 414 #define PF_ERR_PANIC_BAD_RESPONSE (1 << 8) /* Device no response */ 415 #define PF_ERR_MATCH_DOM (1 << 9) /* Error Handled By IO domain */ 416 417 #define PF_ERR_FATAL_FLAGS \ 418 (PF_ERR_PANIC | PF_ERR_PANIC_DEADLOCK | PF_ERR_PANIC_BAD_RESPONSE) 419 420 #define PF_HDL_FOUND 1 421 #define PF_HDL_NOTFOUND 2 422 423 /* 424 * PCIe Capability Device Type Pseudo Definitions. 425 * 426 * PCI_PSEUDO is used on real PCI devices. The Legacy PCI definition in the 427 * PCIe spec really refers to PCIe devices that *require* IO Space access. IO 428 * Space access is usually frowned upon now in PCIe, but there for legacy 429 * purposes. 430 */ 431 #define PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO 0x100 432 #define PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO 0x101 433 434 #define PCIE_INVALID_BDF 0xFFFF 435 #define PCIE_CHECK_VALID_BDF(x) (x != PCIE_INVALID_BDF) 436 437 typedef struct { 438 dev_info_t *dip; 439 int highest_common_mps; 440 } pcie_max_supported_t; 441 442 /* 443 * Default interrupt priority for all PCI and PCIe nexus drivers including 444 * hotplug interrupts. 445 */ 446 #define PCIE_INTR_PRI (LOCK_LEVEL - 1) 447 448 /* 449 * XXX - PCIE_IS_PCIE check is required in order not to invoke these macros 450 * for non-standard PCI or PCI Express Hotplug Controllers. 451 */ 452 #define PCIE_ENABLE_ERRORS(dip) \ 453 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \ 454 pcie_enable_errors(dip); \ 455 (void) pcie_enable_ce(dip); \ 456 } 457 458 #define PCIE_DISABLE_ERRORS(dip) \ 459 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \ 460 pcie_disable_errors(dip); \ 461 } 462 463 /* 464 * pcie_init_buspcie_fini_bus specific flags 465 */ 466 #define PCIE_BUS_INITIAL 0x0001 467 #define PCIE_BUS_FINAL 0x0002 468 #define PCIE_BUS_ALL (PCIE_BUS_INITIAL | PCIE_BUS_FINAL) 469 470 #ifdef DEBUG 471 #define PCIE_DBG pcie_dbg 472 /* Common Debugging shortcuts */ 473 #define PCIE_DBG_CFG(dip, bus_p, name, sz, off, org) \ 474 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 475 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 476 PCIE_GET(sz, bus_p, off)) 477 #define PCIE_DBG_CAP(dip, bus_p, name, sz, off, org) \ 478 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 479 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 480 PCIE_CAP_GET(sz, bus_p, off)) 481 #define PCIE_DBG_AER(dip, bus_p, name, sz, off, org) \ 482 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 483 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 484 PCIE_AER_GET(sz, bus_p, off)) 485 486 #else /* DEBUG */ 487 488 #define PCIE_DBG_CFG 0 && 489 #define PCIE_DBG 0 && 490 #define PCIE_ARI_DBG 0 && 491 #define PCIE_DBG_CAP 0 && 492 #define PCIE_DBG_AER 0 && 493 494 #endif /* DEBUG */ 495 496 /* PCIe Friendly Functions */ 497 extern int pcie_init(dev_info_t *dip, caddr_t arg); 498 extern int pcie_uninit(dev_info_t *dip); 499 extern int pcie_hpintr_enable(dev_info_t *dip); 500 extern int pcie_hpintr_disable(dev_info_t *dip); 501 extern int pcie_intr(dev_info_t *dip); 502 extern int pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp, 503 cred_t *credp); 504 extern int pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp, 505 cred_t *credp); 506 extern int pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg, 507 int mode, cred_t *credp, int *rvalp); 508 extern int pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 509 int flags, char *name, caddr_t valuep, int *lengthp); 510 511 extern void pcie_init_root_port_mps(dev_info_t *dip); 512 extern int pcie_initchild(dev_info_t *dip); 513 extern void pcie_uninitchild(dev_info_t *dip); 514 extern int pcie_init_cfghdl(dev_info_t *dip); 515 extern void pcie_fini_cfghdl(dev_info_t *dip); 516 extern void pcie_clear_errors(dev_info_t *dip); 517 extern int pcie_postattach_child(dev_info_t *dip); 518 extern void pcie_enable_errors(dev_info_t *dip); 519 extern void pcie_disable_errors(dev_info_t *dip); 520 extern int pcie_enable_ce(dev_info_t *dip); 521 extern boolean_t pcie_bridge_is_link_disabled(dev_info_t *); 522 523 extern pcie_bus_t *pcie_init_bus(dev_info_t *dip, pcie_req_id_t bdf, 524 uint8_t flags); 525 extern void pcie_fini_bus(dev_info_t *dip, uint8_t flags); 526 extern void pcie_fab_init_bus(dev_info_t *dip, uint8_t flags); 527 extern void pcie_fab_fini_bus(dev_info_t *dip, uint8_t flags); 528 extern void pcie_rc_init_bus(dev_info_t *dip); 529 extern void pcie_rc_fini_bus(dev_info_t *dip); 530 extern void pcie_rc_init_pfd(dev_info_t *dip, pf_data_t *pfd); 531 extern void pcie_rc_fini_pfd(pf_data_t *pfd); 532 extern boolean_t pcie_is_child(dev_info_t *dip, dev_info_t *rdip); 533 extern int pcie_get_bdf_from_dip(dev_info_t *dip, pcie_req_id_t *bdf); 534 extern dev_info_t *pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip); 535 extern uint32_t pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip); 536 extern int pcie_dev(dev_info_t *dip); 537 extern void pcie_get_fabric_mps(dev_info_t *rc_dip, dev_info_t *dip, 538 int *max_supported); 539 extern int pcie_root_port(dev_info_t *dip); 540 extern int pcie_initchild_mps(dev_info_t *dip); 541 extern void pcie_set_rber_fatal(dev_info_t *dip, boolean_t val); 542 extern boolean_t pcie_get_rber_fatal(dev_info_t *dip); 543 544 extern uint32_t pcie_get_aer_uce_mask(); 545 extern uint32_t pcie_get_aer_ce_mask(); 546 extern uint32_t pcie_get_aer_suce_mask(); 547 extern uint32_t pcie_get_serr_mask(); 548 extern void pcie_set_aer_uce_mask(uint32_t mask); 549 extern void pcie_set_aer_ce_mask(uint32_t mask); 550 extern void pcie_set_aer_suce_mask(uint32_t mask); 551 extern void pcie_set_serr_mask(uint32_t mask); 552 extern void pcie_init_plat(dev_info_t *dip); 553 extern void pcie_fini_plat(dev_info_t *dip); 554 extern int pcie_read_only_probe(dev_info_t *, char *, dev_info_t **); 555 extern dev_info_t *pcie_func_to_dip(dev_info_t *dip, pcie_req_id_t function); 556 extern int pcie_ari_disable(dev_info_t *dip); 557 extern int pcie_ari_enable(dev_info_t *dip); 558 559 #define PCIE_ARI_FORW_NOT_SUPPORTED 0 560 #define PCIE_ARI_FORW_SUPPORTED 1 561 562 extern int pcie_ari_supported(dev_info_t *dip); 563 564 #define PCIE_ARI_FORW_DISABLED 0 565 #define PCIE_ARI_FORW_ENABLED 1 566 567 extern int pcie_ari_is_enabled(dev_info_t *dip); 568 569 #define PCIE_NOT_ARI_DEVICE 0 570 #define PCIE_ARI_DEVICE 1 571 572 extern int pcie_ari_device(dev_info_t *dip); 573 extern int pcie_ari_get_next_function(dev_info_t *dip, int *func); 574 575 /* PCIe error handling functions */ 576 extern void pf_eh_enter(pcie_bus_t *bus_p); 577 extern void pf_eh_exit(pcie_bus_t *bus_p); 578 extern int pf_scan_fabric(dev_info_t *rpdip, ddi_fm_error_t *derr, 579 pf_data_t *root_pfd_p); 580 extern void pf_init(dev_info_t *, ddi_iblock_cookie_t, ddi_attach_cmd_t); 581 extern void pf_fini(dev_info_t *, ddi_detach_cmd_t); 582 extern int pf_hdl_lookup(dev_info_t *, uint64_t, uint32_t, uint64_t, 583 pcie_req_id_t); 584 extern int pf_tlp_decode(pcie_bus_t *, pf_pcie_adv_err_regs_t *); 585 extern void pcie_force_fullscan(); 586 587 #ifdef DEBUG 588 extern uint_t pcie_debug_flags; 589 extern void pcie_dbg(char *fmt, ...); 590 #endif /* DEBUG */ 591 592 /* PCIe IOV functions */ 593 extern dev_info_t *pcie_find_dip_by_bdf(dev_info_t *rootp, pcie_req_id_t bdf); 594 595 extern boolean_t pf_in_bus_range(pcie_bus_t *, pcie_req_id_t); 596 extern boolean_t pf_in_assigned_addr(pcie_bus_t *, uint64_t); 597 extern int pf_pci_decode(pf_data_t *, uint16_t *); 598 extern pcie_bus_t *pf_find_busp_by_bdf(pf_impl_t *, pcie_req_id_t); 599 extern pcie_bus_t *pf_find_busp_by_addr(pf_impl_t *, uint64_t); 600 extern pcie_bus_t *pf_find_busp_by_aer(pf_impl_t *, pf_data_t *); 601 extern pcie_bus_t *pf_find_busp_by_saer(pf_impl_t *, pf_data_t *); 602 603 extern int pciev_eh(pf_data_t *, pf_impl_t *); 604 extern pcie_bus_t *pciev_get_affected_dev(pf_impl_t *, pf_data_t *, 605 uint16_t, uint16_t); 606 extern void pciev_eh_exit(pf_data_t *, uint_t); 607 extern boolean_t pcie_in_domain(pcie_bus_t *, uint_t); 608 609 #define PCIE_ZALLOC(data) kmem_zalloc(sizeof (data), KM_SLEEP) 610 611 612 #ifdef __cplusplus 613 } 614 #endif 615 616 #endif /* _SYS_PCIE_IMPL_H */ 617
Indexes created Wed Feb 10 05:58:14 UTC 2010
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