1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_H 27 #define _SYS_NXGE_NXGE_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <nxge_mac.h> 34 #include <nxge_ipp.h> 35 #include <nxge_fflp.h> 36 37 /* 38 * NXGE diagnostics IOCTLS. 39 */ 40 #define NXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 41 42 #define NXGE_GET64 (NXGE_IOC|1) 43 #define NXGE_PUT64 (NXGE_IOC|2) 44 #define NXGE_GET_TX_RING_SZ (NXGE_IOC|3) 45 #define NXGE_GET_TX_DESC (NXGE_IOC|4) 46 #define NXGE_GLOBAL_RESET (NXGE_IOC|5) 47 #define NXGE_TX_SIDE_RESET (NXGE_IOC|6) 48 #define NXGE_RX_SIDE_RESET (NXGE_IOC|7) 49 #define NXGE_RESET_MAC (NXGE_IOC|8) 50 51 #define NXGE_GET_MII (NXGE_IOC|11) 52 #define NXGE_PUT_MII (NXGE_IOC|12) 53 #define NXGE_RTRACE (NXGE_IOC|13) 54 #define NXGE_RTRACE_TEST (NXGE_IOC|20) 55 #define NXGE_TX_REGS_DUMP (NXGE_IOC|21) 56 #define NXGE_RX_REGS_DUMP (NXGE_IOC|22) 57 #define NXGE_INT_REGS_DUMP (NXGE_IOC|23) 58 #define NXGE_VIR_REGS_DUMP (NXGE_IOC|24) 59 #define NXGE_VIR_INT_REGS_DUMP (NXGE_IOC|25) 60 #define NXGE_RDUMP (NXGE_IOC|26) 61 #define NXGE_RDC_GRPS_DUMP (NXGE_IOC|27) 62 #define NXGE_PIO_TEST (NXGE_IOC|28) 63 64 #define NXGE_GET_TCAM (NXGE_IOC|29) 65 #define NXGE_PUT_TCAM (NXGE_IOC|30) 66 #define NXGE_INJECT_ERR (NXGE_IOC|40) 67 68 #define NXGE_RX_CLASS (NXGE_IOC|41) 69 #define NXGE_RX_HASH (NXGE_IOC|42) 70 71 #define NXGE_OK 0 72 #define NXGE_ERROR 0x40000000 73 #define NXGE_DDI_FAILED 0x20000000 74 #define NXGE_GET_PORT_NUM(n) n 75 76 /* 77 * Definitions for module_info. 78 */ 79 #define NXGE_IDNUM (0) /* module ID number */ 80 #define NXGE_DRIVER_NAME "nxge" /* module name */ 81 82 #define NXGE_MINPSZ (0) /* min packet size */ 83 #define NXGE_MAXPSZ (ETHERMTU) /* max packet size */ 84 #define NXGE_HIWAT (2048 * NXGE_MAXPSZ) /* hi-water mark */ 85 #define NXGE_LOWAT (1) /* lo-water mark */ 86 #define NXGE_HIWAT_MAX (192000 * NXGE_MAXPSZ) 87 #define NXGE_HIWAT_MIN (2 * NXGE_MAXPSZ) 88 #define NXGE_LOWAT_MAX (192000 * NXGE_MAXPSZ) 89 #define NXGE_LOWAT_MIN (1) 90 91 #ifndef D_HOTPLUG 92 #define D_HOTPLUG 0x00 93 #endif 94 95 #define INIT_BUCKET_SIZE 16 /* Initial Hash Bucket Size */ 96 97 #define NXGE_CHECK_TIMER (5000) 98 99 /* KT/NIU OBP creates a compatible property for KT */ 100 #define KT_NIU_COMPATIBLE "SUNW,niusl-kt" 101 102 typedef enum { 103 param_instance, 104 param_main_instance, 105 param_function_number, 106 param_partition_id, 107 param_read_write_mode, 108 param_fw_version, 109 param_port_mode, 110 param_niu_cfg_type, 111 param_tx_quick_cfg, 112 param_rx_quick_cfg, 113 param_master_cfg_enable, 114 param_master_cfg_value, 115 116 param_autoneg, 117 param_anar_10gfdx, 118 param_anar_10ghdx, 119 param_anar_1000fdx, 120 param_anar_1000hdx, 121 param_anar_100T4, 122 param_anar_100fdx, 123 param_anar_100hdx, 124 param_anar_10fdx, 125 param_anar_10hdx, 126 127 param_anar_asmpause, 128 param_anar_pause, 129 param_use_int_xcvr, 130 param_enable_ipg0, 131 param_ipg0, 132 param_ipg1, 133 param_ipg2, 134 param_txdma_weight, 135 param_txdma_channels_begin, 136 137 param_txdma_channels, 138 param_txdma_info, 139 param_rxdma_channels_begin, 140 param_rxdma_channels, 141 param_rxdma_drr_weight, 142 param_rxdma_full_header, 143 param_rxdma_info, 144 param_rxdma_rbr_size, 145 param_rxdma_rcr_size, 146 param_default_port_rdc, 147 param_rxdma_intr_time, 148 param_rxdma_intr_pkts, 149 150 param_rdc_grps_start, 151 param_rx_rdc_grps, 152 param_default_grp0_rdc, 153 param_default_grp1_rdc, 154 param_default_grp2_rdc, 155 param_default_grp3_rdc, 156 param_default_grp4_rdc, 157 param_default_grp5_rdc, 158 param_default_grp6_rdc, 159 param_default_grp7_rdc, 160 161 param_info_rdc_groups, 162 param_start_ldg, 163 param_max_ldg, 164 param_mac_2rdc_grp, 165 param_vlan_2rdc_grp, 166 param_fcram_part_cfg, 167 param_fcram_access_ratio, 168 param_tcam_access_ratio, 169 param_tcam_enable, 170 param_hash_lookup_enable, 171 param_llc_snap_enable, 172 173 param_h1_init_value, 174 param_h2_init_value, 175 param_class_cfg_ether_usr1, 176 param_class_cfg_ether_usr2, 177 param_class_cfg_ip_usr4, 178 param_class_cfg_ip_usr5, 179 param_class_cfg_ip_usr6, 180 param_class_cfg_ip_usr7, 181 param_class_opt_ip_usr4, 182 param_class_opt_ip_usr5, 183 param_class_opt_ip_usr6, 184 param_class_opt_ip_usr7, 185 param_class_opt_ipv4_tcp, 186 param_class_opt_ipv4_udp, 187 param_class_opt_ipv4_ah, 188 param_class_opt_ipv4_sctp, 189 param_class_opt_ipv6_tcp, 190 param_class_opt_ipv6_udp, 191 param_class_opt_ipv6_ah, 192 param_class_opt_ipv6_sctp, 193 param_nxge_debug_flag, 194 param_npi_debug_flag, 195 param_dump_rdc, 196 param_dump_tdc, 197 param_dump_mac_regs, 198 param_dump_ipp_regs, 199 param_dump_fflp_regs, 200 param_dump_vlan_table, 201 param_dump_rdc_table, 202 param_dump_ptrs, 203 param_end 204 } nxge_param_index_t; 205 206 typedef enum { 207 SOLARIS_DOMAIN, 208 SOLARIS_SERVICE_DOMAIN, 209 SOLARIS_GUEST_DOMAIN, 210 LINUX_SERVICE_DOMAIN, 211 LINUX_GUEST_DOMAIN 212 } nxge_environs_t; 213 214 /* 215 * Named Dispatch Parameter Management Structure 216 */ 217 typedef int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *); 218 typedef int (*nxge_ndsetf_t)(p_nxge_t, queue_t *, 219 MBLKP, char *, caddr_t, cred_t *); 220 221 #define NXGE_PARAM_READ 0x00000001ULL 222 #define NXGE_PARAM_WRITE 0x00000002ULL 223 #define NXGE_PARAM_SHARED 0x00000004ULL 224 #define NXGE_PARAM_PRIV 0x00000008ULL 225 #define NXGE_PARAM_RW NXGE_PARAM_READ | NXGE_PARAM_WRITE 226 #define NXGE_PARAM_RWS NXGE_PARAM_RW | NXGE_PARAM_SHARED 227 #define NXGE_PARAM_RWP NXGE_PARAM_RW | NXGE_PARAM_PRIV 228 229 #define NXGE_PARAM_RXDMA 0x00000010ULL 230 #define NXGE_PARAM_TXDMA 0x00000020ULL 231 #define NXGE_PARAM_CLASS_GEN 0x00000040ULL 232 #define NXGE_PARAM_MAC 0x00000080ULL 233 #define NXGE_PARAM_CLASS_BIN NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN 234 #define NXGE_PARAM_CLASS_HEX NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX 235 #define NXGE_PARAM_CLASS NXGE_PARAM_CLASS_HEX 236 237 #define NXGE_PARAM_CMPLX 0x00010000ULL 238 #define NXGE_PARAM_NDD_WR_OK 0x00020000ULL 239 #define NXGE_PARAM_INIT_ONLY 0x00040000ULL 240 #define NXGE_PARAM_INIT_CONFIG 0x00080000ULL 241 242 #define NXGE_PARAM_READ_PROP 0x00100000ULL 243 #define NXGE_PARAM_PROP_ARR32 0x00200000ULL 244 #define NXGE_PARAM_PROP_ARR64 0x00400000ULL 245 #define NXGE_PARAM_PROP_STR 0x00800000ULL 246 247 #define NXGE_PARAM_BASE_DEC 0x00000000ULL 248 #define NXGE_PARAM_BASE_BIN 0x10000000ULL 249 #define NXGE_PARAM_BASE_HEX 0x20000000ULL 250 #define NXGE_PARAM_BASE_STR 0x40000000ULL 251 #define NXGE_PARAM_DONT_SHOW 0x80000000ULL 252 253 #define NXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 254 #define NXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 255 #define NXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 256 #define NXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 257 258 typedef struct _nxge_param_t { 259 int (*getf)(); 260 int (*setf)(); /* null for read only */ 261 uint64_t type; /* R/W/ Common/Port/ .... */ 262 uint64_t minimum; 263 uint64_t maximum; 264 uint64_t value; /* for array params, pointer to value array */ 265 uint64_t old_value; /* for array params, pointer to old_value array */ 266 char *fcode_name; 267 char *name; 268 } nxge_param_t, *p_nxge_param_t; 269 270 271 /* 272 * Do not change the order of the elements of this enum as that will 273 * break the driver code. 274 */ 275 typedef enum { 276 nxge_lb_normal, 277 nxge_lb_ext10g, 278 nxge_lb_ext1000, 279 nxge_lb_ext100, 280 nxge_lb_ext10, 281 nxge_lb_phy10g, 282 nxge_lb_phy1000, 283 nxge_lb_phy, 284 nxge_lb_serdes10g, 285 nxge_lb_serdes1000, 286 nxge_lb_serdes, 287 nxge_lb_mac10g, 288 nxge_lb_mac1000, 289 nxge_lb_mac 290 } nxge_lb_t; 291 292 enum nxge_mac_state { 293 NXGE_MAC_STOPPED = 0, 294 NXGE_MAC_STARTED, 295 NXGE_MAC_STOPPING 296 }; 297 298 /* 299 * Private DLPI full dlsap address format. 300 */ 301 typedef struct _nxge_dladdr_t { 302 ether_addr_st dl_phys; 303 uint16_t dl_sap; 304 } nxge_dladdr_t, *p_nxge_dladdr_t; 305 306 typedef struct _mc_addr_t { 307 ether_addr_st multcast_addr; 308 uint_t mc_addr_cnt; 309 } mc_addr_t, *p_mc_addr_t; 310 311 typedef struct _mc_bucket_t { 312 p_mc_addr_t addr_list; 313 uint_t list_size; 314 } mc_bucket_t, *p_mc_bucket_t; 315 316 typedef struct _mc_table_t { 317 p_mc_bucket_t bucket_list; 318 uint_t buckets_used; 319 } mc_table_t, *p_mc_table_t; 320 321 typedef struct _filter_t { 322 uint32_t all_phys_cnt; 323 uint32_t all_multicast_cnt; 324 uint32_t all_sap_cnt; 325 } filter_t, *p_filter_t; 326 327 328 typedef struct _nxge_port_stats_t { 329 /* 330 * Overall structure size 331 */ 332 size_t stats_size; 333 334 /* 335 * Link Input/Output stats 336 */ 337 uint64_t ipackets; 338 uint64_t ierrors; 339 uint64_t opackets; 340 uint64_t oerrors; 341 uint64_t collisions; 342 343 /* 344 * MIB II variables 345 */ 346 uint64_t rbytes; /* # bytes received */ 347 uint64_t obytes; /* # bytes transmitted */ 348 uint32_t multircv; /* # multicast packets received */ 349 uint32_t multixmt; /* # multicast packets for xmit */ 350 uint32_t brdcstrcv; /* # broadcast packets received */ 351 uint32_t brdcstxmt; /* # broadcast packets for xmit */ 352 uint32_t norcvbuf; /* # rcv packets discarded */ 353 uint32_t noxmtbuf; /* # xmit packets discarded */ 354 355 /* 356 * Lets the user know the MTU currently in use by 357 * the physical MAC port. 358 */ 359 nxge_lb_t lb_mode; 360 uint32_t qos_mode; 361 uint32_t trunk_mode; 362 uint32_t poll_mode; 363 364 /* 365 * Tx Statistics. 366 */ 367 uint32_t tx_inits; 368 uint32_t tx_starts; 369 uint32_t tx_nocanput; 370 uint32_t tx_msgdup_fail; 371 uint32_t tx_allocb_fail; 372 uint32_t tx_no_desc; 373 uint32_t tx_dma_bind_fail; 374 uint32_t tx_uflo; 375 uint32_t tx_hdr_pkts; 376 uint32_t tx_ddi_pkts; 377 uint32_t tx_dvma_pkts; 378 379 uint32_t tx_max_pend; 380 381 /* 382 * Rx Statistics. 383 */ 384 uint32_t rx_inits; 385 uint32_t rx_hdr_pkts; 386 uint32_t rx_mtu_pkts; 387 uint32_t rx_split_pkts; 388 uint32_t rx_no_buf; 389 uint32_t rx_no_comp_wb; 390 uint32_t rx_ov_flow; 391 uint32_t rx_len_mm; 392 uint32_t rx_tag_err; 393 uint32_t rx_nocanput; 394 uint32_t rx_msgdup_fail; 395 uint32_t rx_allocb_fail; 396 397 /* 398 * Receive buffer management statistics. 399 */ 400 uint32_t rx_new_pages; 401 uint32_t rx_new_hdr_pgs; 402 uint32_t rx_new_mtu_pgs; 403 uint32_t rx_new_nxt_pgs; 404 uint32_t rx_reused_pgs; 405 uint32_t rx_hdr_drops; 406 uint32_t rx_mtu_drops; 407 uint32_t rx_nxt_drops; 408 409 /* 410 * Receive flow statistics 411 */ 412 uint32_t rx_rel_flow; 413 uint32_t rx_rel_bit; 414 415 uint32_t rx_pkts_dropped; 416 417 /* 418 * PCI-E Bus Statistics. 419 */ 420 uint32_t pci_bus_speed; 421 uint32_t pci_err; 422 uint32_t pci_rta_err; 423 uint32_t pci_rma_err; 424 uint32_t pci_parity_err; 425 uint32_t pci_bad_ack_err; 426 uint32_t pci_drto_err; 427 uint32_t pci_dmawz_err; 428 uint32_t pci_dmarz_err; 429 430 uint32_t rx_taskq_waits; 431 432 uint32_t tx_jumbo_pkts; 433 434 /* 435 * Some statistics added to support bringup, these 436 * should be removed. 437 */ 438 uint32_t user_defined; 439 } nxge_port_stats_t, *p_nxge_port_stats_t; 440 441 442 typedef struct _nxge_stats_t { 443 /* 444 * Overall structure size 445 */ 446 size_t stats_size; 447 448 kstat_t *ksp; 449 kstat_t *rdc_ksp[NXGE_MAX_RDCS]; 450 kstat_t *tdc_ksp[NXGE_MAX_TDCS]; 451 kstat_t *rdc_sys_ksp; 452 kstat_t *fflp_ksp[1]; 453 kstat_t *ipp_ksp; 454 kstat_t *txc_ksp; 455 kstat_t *mac_ksp; 456 kstat_t *zcp_ksp; 457 kstat_t *port_ksp; 458 kstat_t *mmac_ksp; 459 460 nxge_mac_stats_t mac_stats; /* Common MAC Statistics */ 461 nxge_xmac_stats_t xmac_stats; /* XMAC Statistics */ 462 nxge_bmac_stats_t bmac_stats; /* BMAC Statistics */ 463 464 nxge_rx_ring_stats_t rx_stats; /* per port RX stats */ 465 nxge_ipp_stats_t ipp_stats; /* per port IPP stats */ 466 nxge_zcp_stats_t zcp_stats; /* per port IPP stats */ 467 nxge_rx_ring_stats_t rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */ 468 nxge_rdc_sys_stats_t rdc_sys_stats; /* per port RDC stats */ 469 470 nxge_tx_ring_stats_t tx_stats; /* per port TX stats */ 471 nxge_txc_stats_t txc_stats; /* per port TX stats */ 472 nxge_tx_ring_stats_t tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */ 473 nxge_fflp_stats_t fflp_stats; /* fflp stats */ 474 nxge_port_stats_t port_stats; /* fflp stats */ 475 nxge_mmac_stats_t mmac_stats; /* Multi mac. stats */ 476 477 } nxge_stats_t, *p_nxge_stats_t; 478 479 480 481 typedef struct _nxge_intr_t { 482 boolean_t intr_registered; /* interrupts are registered */ 483 boolean_t intr_enabled; /* interrupts are enabled */ 484 boolean_t niu_msi_enable; /* debug or configurable? */ 485 int intr_types; /* interrupt types supported */ 486 int intr_type; /* interrupt type to add */ 487 int max_int_cnt; /* max MSIX/INT HW supports */ 488 int start_inum; /* start inum (in sequence?) */ 489 int msi_intx_cnt; /* # msi/intx ints returned */ 490 int intr_added; /* # ints actually needed */ 491 int intr_cap; /* interrupt capabilities */ 492 size_t intr_size; /* size of array to allocate */ 493 ddi_intr_handle_t *htable; /* For array of interrupts */ 494 /* Add interrupt number for each interrupt vector */ 495 int pri; 496 } nxge_intr_t, *p_nxge_intr_t; 497 498 typedef struct _nxge_ldgv_t { 499 uint8_t ndma_ldvs; 500 uint8_t nldvs; 501 uint8_t maxldgs; 502 uint8_t maxldvs; 503 uint8_t ldg_intrs; 504 uint32_t tmres; 505 p_nxge_ldg_t ldgp; 506 p_nxge_ldv_t ldvp; 507 p_nxge_ldv_t ldvp_syserr; 508 boolean_t ldvp_syserr_alloced; 509 } nxge_ldgv_t, *p_nxge_ldgv_t; 510 511 typedef enum { 512 NXGE_TRANSMIT_GROUP, /* Legacy transmit group */ 513 NXGE_RECEIVE_GROUP, /* Legacy receive group */ 514 NXGE_VR_GROUP, /* Virtualization Region group */ 515 EXT_TRANSMIT_GROUP, /* External (Crossbow) transmit group */ 516 EXT_RECEIVE_GROUP /* External (Crossbow) receive group */ 517 } nxge_grp_type_t; 518 519 #define NXGE_ILLEGAL_CHANNEL (NXGE_MAX_TDCS + 1) 520 521 typedef uint8_t nxge_channel_t; 522 523 typedef struct nxge_grp { 524 nxge_t *nxge; 525 nxge_grp_type_t type; /* Tx or Rx */ 526 527 int sequence; /* When it was created. */ 528 int index; /* nxge_grp_set_t.group[index] */ 529 530 struct nx_dc *dc; /* Linked list of DMA channels. */ 531 size_t count; /* A count of <dc> above. */ 532 533 boolean_t active; /* Is it being used? */ 534 535 dc_map_t map; /* A bitmap of the channels in <dc>. */ 536 nxge_channel_t legend[NXGE_MAX_TDCS]; 537 538 } nxge_grp_t; 539 540 typedef struct { 541 lg_map_t map; 542 size_t count; 543 } lg_data_t; 544 545 typedef struct { 546 dc_map_t map; 547 size_t count; 548 } dc_data_t; 549 550 #define NXGE_DC_SET(map, channel) map |= (1 << channel) 551 #define NXGE_DC_RESET(map, channel) map &= (~(1 << channel)) 552 553 /* For now, we only support up to 8 RDC/TDC groups */ 554 #define NXGE_LOGICAL_GROUP_MAX NXGE_MAX_RDC_GROUPS 555 556 typedef struct { 557 int sequence; /* To order groups in time. */ 558 559 /* These are this instance's logical groups. */ 560 nxge_grp_t *group[NXGE_LOGICAL_GROUP_MAX]; 561 lg_data_t lg; 562 563 dc_data_t shared; /* These DCs are being shared. */ 564 dc_data_t owned; /* These DCs belong to me. */ 565 dc_data_t dead; /* These DCs are in an error state. */ 566 567 } nxge_grp_set_t; 568 569 /* 570 * Transmit Ring Group 571 * TX groups will be used exclusively for the purpose of Hybrid I/O. From 572 * the point of view of the nxge driver, the groups will be software 573 * constructs which will be used to establish the relationship between TX 574 * rings and shares. 575 * 576 * Receive Ring Group 577 * One of the advanced virtualization features is the ability to bundle 578 * multiple Receive Rings in a single group. One or more MAC addresses may 579 * be assigned to a group. Incoming packets destined to the group's MAC 580 * address(es) are delivered to any ring member, according to a programmable 581 * or predefined RTS policy. Member rings can be polled individually. 582 * RX ring groups can come with a predefined set of member rings, or they 583 * are programmable by adding and removing rings to/from them. 584 */ 585 typedef struct _nxge_ring_group_t { 586 mac_group_handle_t ghandle; 587 p_nxge_t nxgep; 588 boolean_t started; 589 boolean_t port_default_grp; 590 mac_ring_type_t type; 591 int gindex; 592 int sindex; 593 int rdctbl; 594 int n_mac_addrs; 595 } nxge_ring_group_t; 596 597 /* 598 * Ring Handle 599 */ 600 typedef struct _nxge_ring_handle_t { 601 p_nxge_t nxgep; 602 int index; /* port-wise */ 603 mac_ring_handle_t ring_handle; 604 } nxge_ring_handle_t, *p_nxge_ring_handle_t; 605 606 /* 607 * Share Handle 608 */ 609 typedef struct _nxge_share_handle_t { 610 p_nxge_t nxgep; /* Driver Handle */ 611 int index; 612 void *vrp; 613 uint64_t tmap; 614 uint64_t rmap; 615 int rxgroup; 616 boolean_t active; 617 } nxge_share_handle_t; 618 619 /* 620 * Neptune Device instance state information. 621 * 622 * Each instance is dynamically allocated on first attach. 623 */ 624 struct _nxge_t { 625 dev_info_t *dip; /* device instance */ 626 dev_info_t *p_dip; /* Parent's device instance */ 627 int instance; /* instance number */ 628 int function_num; /* device function number */ 629 int nports; /* # of ports on this device */ 630 int board_ver; /* Board Version */ 631 int use_partition; /* partition is enabled */ 632 uint32_t drv_state; /* driver state bit flags */ 633 uint64_t nxge_debug_level; /* driver state bit flags */ 634 kmutex_t genlock[1]; 635 enum nxge_mac_state nxge_mac_state; 636 637 p_dev_regs_t dev_regs; 638 npi_handle_t npi_handle; 639 npi_handle_t npi_pci_handle; 640 npi_handle_t npi_reg_handle; 641 npi_handle_t npi_msi_handle; 642 npi_handle_t npi_vreg_handle; 643 npi_handle_t npi_v2reg_handle; 644 645 nxge_xcvr_table_t xcvr; 646 boolean_t hot_swappable_phy; 647 boolean_t phy_absent; 648 uint32_t xcvr_addr; 649 uint16_t chip_id; 650 nxge_mac_t mac; 651 nxge_ipp_t ipp; 652 nxge_txc_t txc; 653 nxge_classify_t classifier; 654 655 mac_handle_t mach; /* mac module handle */ 656 p_nxge_stats_t statsp; 657 uint32_t param_count; 658 p_nxge_param_t param_arr; 659 660 uint32_t param_en_pause:1, 661 param_en_asym_pause:1, 662 param_en_1000fdx:1, 663 param_en_100fdx:1, 664 param_en_10fdx:1, 665 param_pad_to_32:27; 666 667 nxge_hw_list_t *nxge_hw_p; /* pointer to per Neptune */ 668 niu_type_t niu_type; 669 platform_type_t platform_type; 670 boolean_t os_addr_mode32; /* set to 1 for 32 bit mode */ 671 672 uint8_t def_rdc; 673 674 nxge_intr_t nxge_intr_type; 675 nxge_dma_pt_cfg_t pt_config; 676 nxge_class_pt_cfg_t class_config; 677 678 /* Logical device and group data structures. */ 679 p_nxge_ldgv_t ldgvp; 680 681 npi_vpd_info_t vpd_info; 682 683 ether_addr_st factaddr; /* factory mac address */ 684 ether_addr_st ouraddr; /* individual address */ 685 boolean_t primary; /* primary addr set?. */ 686 kmutex_t ouraddr_lock; /* lock to protect to uradd */ 687 688 ddi_iblock_cookie_t interrupt_cookie; 689 690 /* 691 * Blocks of memory may be pre-allocated by the 692 * partition manager or the driver. They may include 693 * blocks for configuration and buffers. The idea is 694 * to preallocate big blocks of contiguous areas in 695 * system memory (i.e. with IOMMU). These blocks then 696 * will be broken up to a fixed number of blocks with 697 * each block having the same block size (4K, 8K, 16K or 698 * 32K) in the case of buffer blocks. For systems that 699 * do not support DVMA, more than one big block will be 700 * allocated. 701 */ 702 uint32_t rx_default_block_size; 703 nxge_rx_block_size_t rx_bksize_code; 704 705 p_nxge_dma_pool_t rx_buf_pool_p; 706 p_nxge_dma_pool_t rx_cntl_pool_p; 707 708 p_nxge_dma_pool_t tx_buf_pool_p; 709 p_nxge_dma_pool_t tx_cntl_pool_p; 710 711 /* Receive buffer block ring and completion ring. */ 712 p_rx_rbr_rings_t rx_rbr_rings; 713 p_rx_rcr_rings_t rx_rcr_rings; 714 p_rx_mbox_areas_t rx_mbox_areas_p; 715 716 uint32_t rdc_mask; 717 718 /* Transmit descriptors rings */ 719 p_tx_rings_t tx_rings; 720 p_tx_mbox_areas_t tx_mbox_areas_p; 721 722 ddi_dma_handle_t dmasparehandle; 723 724 ulong_t sys_page_sz; 725 ulong_t sys_page_mask; 726 int suspended; 727 728 mii_bmsr_t bmsr; /* xcvr status at last poll. */ 729 mii_bmsr_t soft_bmsr; /* xcvr status kept by SW. */ 730 731 kmutex_t mif_lock; /* Lock to protect the list. */ 732 733 void (*mii_read)(); 734 void (*mii_write)(); 735 void (*mii_poll)(); 736 filter_t filter; /* Current instance filter */ 737 p_hash_filter_t hash_filter; /* Multicast hash filter. */ 738 krwlock_t filter_lock; /* Lock to protect filters. */ 739 740 ulong_t sys_burst_sz; 741 742 uint8_t cache_line; 743 744 timeout_id_t nxge_link_poll_timerid; 745 timeout_id_t nxge_timerid; 746 747 uint_t need_periodic_reclaim; 748 timeout_id_t reclaim_timer; 749 750 uint8_t msg_min; 751 uint8_t crc_size; 752 753 boolean_t hard_props_read; 754 755 uint32_t nxge_ncpus; 756 uint16_t intr_timeout; 757 uint16_t intr_threshold; 758 759 int fm_capabilities; /* FMA capabilities */ 760 761 uint32_t nxge_port_rbr_size; 762 uint32_t nxge_port_rbr_spare_size; 763 uint32_t nxge_port_rcr_size; 764 uint32_t nxge_port_rx_cntl_alloc_size; 765 uint32_t nxge_port_tx_ring_size; 766 nxge_mmac_t nxge_mmac_info; 767 #if defined(sun4v) 768 boolean_t niu_hsvc_available; 769 hsvc_info_t niu_hsvc; 770 uint64_t niu_min_ver; 771 #endif 772 boolean_t link_notify; 773 int link_check_count; 774 775 kmutex_t poll_lock; 776 kcondvar_t poll_cv; 777 link_mon_enable_t poll_state; 778 #define NXGE_MAGIC 0x3ab434e3 779 uint32_t nxge_magic; 780 781 int soft_lso_enable; 782 /* The following fields are LDOMs-specific additions. */ 783 nxge_environs_t environs; 784 ether_addr_t hio_mac_addr; 785 uint32_t niu_cfg_hdl; 786 kmutex_t group_lock; 787 788 struct nxge_hio_vr *hio_vr; 789 790 nxge_grp_set_t rx_set; 791 nxge_grp_set_t tx_set; 792 boolean_t tdc_is_shared[NXGE_MAX_TDCS]; 793 794 boolean_t rx_channel_started[NXGE_MAX_RDCS]; 795 796 /* Ring Handles */ 797 nxge_ring_handle_t tx_ring_handles[NXGE_MAX_TDCS]; 798 nxge_ring_handle_t rx_ring_handles[NXGE_MAX_RDCS]; 799 800 nxge_ring_group_t tx_hio_groups[NXGE_MAX_TDC_GROUPS]; 801 nxge_ring_group_t rx_hio_groups[NXGE_MAX_RDC_GROUPS]; 802 803 nxge_share_handle_t shares[NXGE_MAX_VRS]; 804 805 /* 806 * KT-NIU: 807 * KT family will have up to 4 NIUs per system. 808 * Differences between N2/NIU and KT/NIU: 809 * SerDes, Hypervisor interfaces, 810 * additional NIU classification features. 811 */ 812 niu_hw_type_t niu_hw_type; 813 }; 814 815 /* 816 * Driver state flags. 817 */ 818 #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 819 #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 820 #define STATE_NODE_CREATED 0x000000004 /* device node created */ 821 #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 822 #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 823 #define STATE_MDIO_LOCK_INIT 0x000000020 /* mdio lock initialized */ 824 #define STATE_MII_LOCK_INIT 0x000000040 /* mii lock initialized */ 825 826 #define STOP_POLL_THRESH 9 827 #define START_POLL_THRESH 2 828 829 typedef struct _nxge_port_kstat_t { 830 /* 831 * Transciever state informations. 832 */ 833 kstat_named_t xcvr_inits; 834 kstat_named_t xcvr_inuse; 835 kstat_named_t xcvr_addr; 836 kstat_named_t xcvr_id; 837 kstat_named_t cap_autoneg; 838 kstat_named_t cap_10gfdx; 839 kstat_named_t cap_10ghdx; 840 kstat_named_t cap_1000fdx; 841 kstat_named_t cap_1000hdx; 842 kstat_named_t cap_100T4; 843 kstat_named_t cap_100fdx; 844 kstat_named_t cap_100hdx; 845 kstat_named_t cap_10fdx; 846 kstat_named_t cap_10hdx; 847 kstat_named_t cap_asmpause; 848 kstat_named_t cap_pause; 849 850 /* 851 * Link partner capabilities. 852 */ 853 kstat_named_t lp_cap_autoneg; 854 kstat_named_t lp_cap_10gfdx; 855 kstat_named_t lp_cap_10ghdx; 856 kstat_named_t lp_cap_1000fdx; 857 kstat_named_t lp_cap_1000hdx; 858 kstat_named_t lp_cap_100T4; 859 kstat_named_t lp_cap_100fdx; 860 kstat_named_t lp_cap_100hdx; 861 kstat_named_t lp_cap_10fdx; 862 kstat_named_t lp_cap_10hdx; 863 kstat_named_t lp_cap_asmpause; 864 kstat_named_t lp_cap_pause; 865 866 /* 867 * Shared link setup. 868 */ 869 kstat_named_t link_T4; 870 kstat_named_t link_speed; 871 kstat_named_t link_duplex; 872 kstat_named_t link_asmpause; 873 kstat_named_t link_pause; 874 kstat_named_t link_up; 875 876 /* 877 * Lets the user know the MTU currently in use by 878 * the physical MAC port. 879 */ 880 kstat_named_t mac_mtu; 881 kstat_named_t lb_mode; 882 kstat_named_t qos_mode; 883 kstat_named_t trunk_mode; 884 885 /* 886 * Misc MAC statistics. 887 */ 888 kstat_named_t ifspeed; 889 kstat_named_t promisc; 890 kstat_named_t rev_id; 891 892 /* 893 * Some statistics added to support bringup, these 894 * should be removed. 895 */ 896 kstat_named_t user_defined; 897 } nxge_port_kstat_t, *p_nxge_port_kstat_t; 898 899 typedef struct _nxge_rdc_kstat { 900 /* 901 * Receive DMA channel statistics. 902 */ 903 kstat_named_t ipackets; 904 kstat_named_t rbytes; 905 kstat_named_t errors; 906 kstat_named_t dcf_err; 907 kstat_named_t rcr_ack_err; 908 909 kstat_named_t dc_fifoflow_err; 910 kstat_named_t rcr_sha_par_err; 911 kstat_named_t rbr_pre_par_err; 912 kstat_named_t wred_drop; 913 kstat_named_t rbr_pre_emty; 914 915 kstat_named_t rcr_shadow_full; 916 kstat_named_t rbr_tmout; 917 kstat_named_t rsp_cnt_err; 918 kstat_named_t byte_en_bus; 919 kstat_named_t rsp_dat_err; 920 921 kstat_named_t pkt_too_long_err; 922 kstat_named_t compl_l2_err; 923 kstat_named_t compl_l4_cksum_err; 924 kstat_named_t compl_zcp_soft_err; 925 kstat_named_t compl_fflp_soft_err; 926 kstat_named_t config_err; 927 928 kstat_named_t rcrincon; 929 kstat_named_t rcrfull; 930 kstat_named_t rbr_empty; 931 kstat_named_t rbrfull; 932 kstat_named_t rbrlogpage; 933 934 kstat_named_t cfiglogpage; 935 kstat_named_t port_drop_pkt; 936 kstat_named_t rcr_to; 937 kstat_named_t rcr_thresh; 938 kstat_named_t rcr_mex; 939 kstat_named_t id_mismatch; 940 kstat_named_t zcp_eop_err; 941 kstat_named_t ipp_eop_err; 942 } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t; 943 944 typedef struct _nxge_rdc_sys_kstat { 945 /* 946 * Receive DMA system statistics. 947 */ 948 kstat_named_t pre_par; 949 kstat_named_t sha_par; 950 kstat_named_t id_mismatch; 951 kstat_named_t ipp_eop_err; 952 kstat_named_t zcp_eop_err; 953 } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t; 954 955 typedef struct _nxge_tdc_kstat { 956 /* 957 * Transmit DMA channel statistics. 958 */ 959 kstat_named_t opackets; 960 kstat_named_t obytes; 961 kstat_named_t oerrors; 962 kstat_named_t tx_inits; 963 kstat_named_t tx_no_buf; 964 965 kstat_named_t mbox_err; 966 kstat_named_t pkt_size_err; 967 kstat_named_t tx_ring_oflow; 968 kstat_named_t pref_buf_ecc_err; 969 kstat_named_t nack_pref; 970 kstat_named_t nack_pkt_rd; 971 kstat_named_t conf_part_err; 972 kstat_named_t pkt_prt_err; 973 kstat_named_t reset_fail; 974 /* used to in the common (per port) counter */ 975 976 kstat_named_t tx_starts; 977 kstat_named_t tx_nocanput; 978 kstat_named_t tx_msgdup_fail; 979 kstat_named_t tx_allocb_fail; 980 kstat_named_t tx_no_desc; 981 kstat_named_t tx_dma_bind_fail; 982 kstat_named_t tx_uflo; 983 kstat_named_t tx_hdr_pkts; 984 kstat_named_t tx_ddi_pkts; 985 kstat_named_t tx_dvma_pkts; 986 kstat_named_t tx_max_pend; 987 } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t; 988 989 typedef struct _nxge_txc_kstat { 990 /* 991 * Transmit port TXC block statistics. 992 */ 993 kstat_named_t pkt_stuffed; 994 kstat_named_t pkt_xmit; 995 kstat_named_t ro_correct_err; 996 kstat_named_t ro_uncorrect_err; 997 kstat_named_t sf_correct_err; 998 kstat_named_t sf_uncorrect_err; 999 kstat_named_t address_failed; 1000 kstat_named_t dma_failed; 1001 kstat_named_t length_failed; 1002 kstat_named_t pkt_assy_dead; 1003 kstat_named_t reorder_err; 1004 } nxge_txc_kstat_t, *p_nxge_txc_kstat_t; 1005 1006 typedef struct _nxge_ipp_kstat { 1007 /* 1008 * Receive port IPP block statistics. 1009 */ 1010 kstat_named_t eop_miss; 1011 kstat_named_t sop_miss; 1012 kstat_named_t dfifo_ue; 1013 kstat_named_t ecc_err_cnt; 1014 kstat_named_t pfifo_perr; 1015 kstat_named_t pfifo_over; 1016 kstat_named_t pfifo_und; 1017 kstat_named_t bad_cs_cnt; 1018 kstat_named_t pkt_dis_cnt; 1019 } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t; 1020 1021 typedef struct _nxge_zcp_kstat { 1022 /* 1023 * ZCP statistics. 1024 */ 1025 kstat_named_t errors; 1026 kstat_named_t inits; 1027 kstat_named_t rrfifo_underrun; 1028 kstat_named_t rrfifo_overrun; 1029 kstat_named_t rspfifo_uncorr_err; 1030 kstat_named_t buffer_overflow; 1031 kstat_named_t stat_tbl_perr; 1032 kstat_named_t dyn_tbl_perr; 1033 kstat_named_t buf_tbl_perr; 1034 kstat_named_t tt_program_err; 1035 kstat_named_t rsp_tt_index_err; 1036 kstat_named_t slv_tt_index_err; 1037 kstat_named_t zcp_tt_index_err; 1038 kstat_named_t access_fail; 1039 kstat_named_t cfifo_ecc; 1040 } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t; 1041 1042 typedef struct _nxge_mac_kstat { 1043 /* 1044 * Transmit MAC statistics. 1045 */ 1046 kstat_named_t tx_frame_cnt; 1047 kstat_named_t tx_underflow_err; 1048 kstat_named_t tx_overflow_err; 1049 kstat_named_t tx_maxpktsize_err; 1050 kstat_named_t tx_fifo_xfr_err; 1051 kstat_named_t tx_byte_cnt; 1052 1053 /* 1054 * Receive MAC statistics. 1055 */ 1056 kstat_named_t rx_frame_cnt; 1057 kstat_named_t rx_underflow_err; 1058 kstat_named_t rx_overflow_err; 1059 kstat_named_t rx_len_err_cnt; 1060 kstat_named_t rx_crc_err_cnt; 1061 kstat_named_t rx_viol_err_cnt; 1062 kstat_named_t rx_byte_cnt; 1063 kstat_named_t rx_hist1_cnt; 1064 kstat_named_t rx_hist2_cnt; 1065 kstat_named_t rx_hist3_cnt; 1066 kstat_named_t rx_hist4_cnt; 1067 kstat_named_t rx_hist5_cnt; 1068 kstat_named_t rx_hist6_cnt; 1069 kstat_named_t rx_hist7_cnt; 1070 kstat_named_t rx_broadcast_cnt; 1071 kstat_named_t rx_mult_cnt; 1072 kstat_named_t rx_frag_cnt; 1073 kstat_named_t rx_frame_align_err_cnt; 1074 kstat_named_t rx_linkfault_err_cnt; 1075 kstat_named_t rx_local_fault_err_cnt; 1076 kstat_named_t rx_remote_fault_err_cnt; 1077 } nxge_mac_kstat_t, *p_nxge_mac_kstat_t; 1078 1079 typedef struct _nxge_xmac_kstat { 1080 /* 1081 * XMAC statistics. 1082 */ 1083 kstat_named_t tx_frame_cnt; 1084 kstat_named_t tx_underflow_err; 1085 kstat_named_t tx_maxpktsize_err; 1086 kstat_named_t tx_overflow_err; 1087 kstat_named_t tx_fifo_xfr_err; 1088 kstat_named_t tx_byte_cnt; 1089 kstat_named_t rx_frame_cnt; 1090 kstat_named_t rx_underflow_err; 1091 kstat_named_t rx_overflow_err; 1092 kstat_named_t rx_crc_err_cnt; 1093 kstat_named_t rx_len_err_cnt; 1094 kstat_named_t rx_viol_err_cnt; 1095 kstat_named_t rx_byte_cnt; 1096 kstat_named_t rx_hist1_cnt; 1097 kstat_named_t rx_hist2_cnt; 1098 kstat_named_t rx_hist3_cnt; 1099 kstat_named_t rx_hist4_cnt; 1100 kstat_named_t rx_hist5_cnt; 1101 kstat_named_t rx_hist6_cnt; 1102 kstat_named_t rx_hist7_cnt; 1103 kstat_named_t rx_broadcast_cnt; 1104 kstat_named_t rx_mult_cnt; 1105 kstat_named_t rx_frag_cnt; 1106 kstat_named_t rx_frame_align_err_cnt; 1107 kstat_named_t rx_linkfault_err_cnt; 1108 kstat_named_t rx_remote_fault_err_cnt; 1109 kstat_named_t rx_local_fault_err_cnt; 1110 kstat_named_t rx_pause_cnt; 1111 kstat_named_t xpcs_deskew_err_cnt; 1112 kstat_named_t xpcs_ln0_symbol_err_cnt; 1113 kstat_named_t xpcs_ln1_symbol_err_cnt; 1114 kstat_named_t xpcs_ln2_symbol_err_cnt; 1115 kstat_named_t xpcs_ln3_symbol_err_cnt; 1116 } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t; 1117 1118 typedef struct _nxge_bmac_kstat { 1119 /* 1120 * BMAC statistics. 1121 */ 1122 kstat_named_t tx_frame_cnt; 1123 kstat_named_t tx_underrun_err; 1124 kstat_named_t tx_max_pkt_err; 1125 kstat_named_t tx_byte_cnt; 1126 kstat_named_t rx_frame_cnt; 1127 kstat_named_t rx_byte_cnt; 1128 kstat_named_t rx_overflow_err; 1129 kstat_named_t rx_align_err_cnt; 1130 kstat_named_t rx_crc_err_cnt; 1131 kstat_named_t rx_len_err_cnt; 1132 kstat_named_t rx_viol_err_cnt; 1133 kstat_named_t rx_pause_cnt; 1134 kstat_named_t tx_pause_state; 1135 kstat_named_t tx_nopause_state; 1136 } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t; 1137 1138 1139 typedef struct _nxge_fflp_kstat { 1140 /* 1141 * FFLP statistics. 1142 */ 1143 1144 kstat_named_t fflp_tcam_perr; 1145 kstat_named_t fflp_tcam_ecc_err; 1146 kstat_named_t fflp_vlan_perr; 1147 kstat_named_t fflp_hasht_lookup_err; 1148 kstat_named_t fflp_hasht_data_err[MAX_PARTITION]; 1149 } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t; 1150 1151 typedef struct _nxge_mmac_kstat { 1152 kstat_named_t mmac_max_addr_cnt; 1153 kstat_named_t mmac_avail_addr_cnt; 1154 kstat_named_t mmac_addr1; 1155 kstat_named_t mmac_addr2; 1156 kstat_named_t mmac_addr3; 1157 kstat_named_t mmac_addr4; 1158 kstat_named_t mmac_addr5; 1159 kstat_named_t mmac_addr6; 1160 kstat_named_t mmac_addr7; 1161 kstat_named_t mmac_addr8; 1162 kstat_named_t mmac_addr9; 1163 kstat_named_t mmac_addr10; 1164 kstat_named_t mmac_addr11; 1165 kstat_named_t mmac_addr12; 1166 kstat_named_t mmac_addr13; 1167 kstat_named_t mmac_addr14; 1168 kstat_named_t mmac_addr15; 1169 kstat_named_t mmac_addr16; 1170 } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t; 1171 1172 /* 1173 * Prototype definitions. 1174 */ 1175 nxge_status_t nxge_init(p_nxge_t); 1176 void nxge_uninit(p_nxge_t); 1177 void nxge_get64(p_nxge_t, p_mblk_t); 1178 void nxge_put64(p_nxge_t, p_mblk_t); 1179 void nxge_pio_loop(p_nxge_t, p_mblk_t); 1180 1181 typedef void (*fptrv_t)(); 1182 timeout_id_t nxge_start_timer(p_nxge_t, fptrv_t, int); 1183 void nxge_stop_timer(p_nxge_t, timeout_id_t); 1184 1185 #ifdef __cplusplus 1186 } 1187 #endif 1188 1189 #endif /* _SYS_NXGE_NXGE_H */ 1190
Indexes created Wed Feb 10 02:29:26 UTC 2010
Terms of Use |
Privacy |
Trademarks |
Copyright Policy |
Site Guidelines |
Site Map |
Help
Your use of this web site or any of its content or software indicates your agreement to be bound by these Terms of Use.
© 2010, Oracle Corporation and/or its affiliates
