1 6629 zf162725 /* 2 6629 zf162725 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 6629 zf162725 * Use is subject to license terms. 4 6629 zf162725 */ 5 6629 zf162725 6 6629 zf162725 /* 7 6629 zf162725 * Copyright (c) 2005, 2006 8 6629 zf162725 * Damien Bergamini <damien.bergamini (at) free.fr> 9 6629 zf162725 * 10 6629 zf162725 * Permission to use, copy, modify, and distribute this software for any 11 6629 zf162725 * purpose with or without fee is hereby granted, provided that the above 12 6629 zf162725 * copyright notice and this permission notice appear in all copies. 13 6629 zf162725 * 14 6629 zf162725 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 6629 zf162725 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 6629 zf162725 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 6629 zf162725 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 6629 zf162725 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 6629 zf162725 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 6629 zf162725 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 6629 zf162725 */ 22 6629 zf162725 #ifndef _URAL_REG_H 23 6629 zf162725 #define _URAL_REG_H 24 6629 zf162725 25 6629 zf162725 #pragma ident "%Z%%M% %I% %E% SMI" 26 6629 zf162725 27 6629 zf162725 #ifdef __cplusplus 28 6629 zf162725 extern "C" { 29 6629 zf162725 #endif 30 6629 zf162725 31 6629 zf162725 #define RAL_RX_DESC_SIZE (sizeof (struct ural_rx_desc)) 32 6629 zf162725 #define RAL_TX_DESC_SIZE (sizeof (struct ural_tx_desc)) 33 6629 zf162725 34 6629 zf162725 #define RAL_CONFIG_NO 1 35 6629 zf162725 #define RAL_IFACE_INDEX 0 36 6629 zf162725 37 6629 zf162725 #define RAL_VENDOR_REQUEST 0x01 38 6629 zf162725 #define RAL_WRITE_MAC 0x02 39 6629 zf162725 #define RAL_READ_MAC 0x03 40 6629 zf162725 #define RAL_WRITE_MULTI_MAC 0x06 41 6629 zf162725 #define RAL_READ_MULTI_MAC 0x07 42 6629 zf162725 #define RAL_READ_EEPROM 0x09 43 6629 zf162725 44 6629 zf162725 /* 45 6629 zf162725 * MAC registers. 46 6629 zf162725 */ 47 6629 zf162725 #define RAL_MAC_CSR0 0x0400 /* ASIC Version */ 48 6629 zf162725 #define RAL_MAC_CSR1 0x0402 /* System control */ 49 6629 zf162725 #define RAL_MAC_CSR2 0x0404 /* MAC addr0 */ 50 6629 zf162725 #define RAL_MAC_CSR3 0x0406 /* MAC addr1 */ 51 6629 zf162725 #define RAL_MAC_CSR4 0x0408 /* MAC addr2 */ 52 6629 zf162725 #define RAL_MAC_CSR5 0x040a /* BSSID0 */ 53 6629 zf162725 #define RAL_MAC_CSR6 0x040c /* BSSID1 */ 54 6629 zf162725 #define RAL_MAC_CSR7 0x040e /* BSSID2 */ 55 6629 zf162725 #define RAL_MAC_CSR8 0x0410 /* Max frame length */ 56 6629 zf162725 #define RAL_MAC_CSR9 0x0412 /* Timer control */ 57 6629 zf162725 #define RAL_MAC_CSR10 0x0414 /* Slot time */ 58 6629 zf162725 #define RAL_MAC_CSR11 0x0416 /* IFS */ 59 6629 zf162725 #define RAL_MAC_CSR12 0x0418 /* EIFS */ 60 6629 zf162725 #define RAL_MAC_CSR13 0x041a /* Power mode0 */ 61 6629 zf162725 #define RAL_MAC_CSR14 0x041c /* Power mode1 */ 62 6629 zf162725 #define RAL_MAC_CSR15 0x041e /* Power saving transition0 */ 63 6629 zf162725 #define RAL_MAC_CSR16 0x0420 /* Power saving transition1 */ 64 6629 zf162725 #define RAL_MAC_CSR17 0x0422 /* Power state control */ 65 6629 zf162725 #define RAL_MAC_CSR18 0x0424 /* Auto wake-up control */ 66 6629 zf162725 #define RAL_MAC_CSR19 0x0426 /* GPIO control */ 67 6629 zf162725 #define RAL_MAC_CSR20 0x0428 /* LED control0 */ 68 6629 zf162725 #define RAL_MAC_CSR22 0x042c /* Not documented */ 69 6629 zf162725 70 6629 zf162725 /* 71 6629 zf162725 * Tx/Rx Registers. 72 6629 zf162725 */ 73 6629 zf162725 #define RAL_TXRX_CSR0 0x0440 /* Security control */ 74 6629 zf162725 #define RAL_TXRX_CSR2 0x0444 /* Rx control */ 75 6629 zf162725 #define RAL_TXRX_CSR5 0x044a /* CCK Tx BBP ID0 */ 76 6629 zf162725 #define RAL_TXRX_CSR6 0x044c /* CCK Tx BBP ID1 */ 77 6629 zf162725 #define RAL_TXRX_CSR7 0x044e /* OFDM Tx BBP ID0 */ 78 6629 zf162725 #define RAL_TXRX_CSR8 0x0450 /* OFDM Tx BBP ID1 */ 79 6629 zf162725 #define RAL_TXRX_CSR10 0x0454 /* Auto responder control */ 80 6629 zf162725 #define RAL_TXRX_CSR11 0x0456 /* Auto responder basic rate */ 81 6629 zf162725 #define RAL_TXRX_CSR18 0x0464 /* Beacon interval */ 82 6629 zf162725 #define RAL_TXRX_CSR19 0x0466 /* Beacon/sync control */ 83 6629 zf162725 #define RAL_TXRX_CSR20 0x0468 /* Beacon alignment */ 84 6629 zf162725 #define RAL_TXRX_CSR21 0x046a /* Not documented */ 85 6629 zf162725 86 6629 zf162725 /* 87 6629 zf162725 * Security registers. 88 6629 zf162725 */ 89 6629 zf162725 #define RAL_SEC_CSR0 0x0480 /* Shared key 0, word 0 */ 90 6629 zf162725 91 6629 zf162725 /* 92 6629 zf162725 * PHY registers. 93 6629 zf162725 */ 94 6629 zf162725 #define RAL_PHY_CSR2 0x04c4 /* Tx MAC configuration */ 95 6629 zf162725 #define RAL_PHY_CSR4 0x04c8 /* Interface configuration */ 96 6629 zf162725 #define RAL_PHY_CSR5 0x04ca /* BBP Pre-Tx CCK */ 97 6629 zf162725 #define RAL_PHY_CSR6 0x04cc /* BBP Pre-Tx OFDM */ 98 6629 zf162725 #define RAL_PHY_CSR7 0x04ce /* BBP serial control */ 99 6629 zf162725 #define RAL_PHY_CSR8 0x04d0 /* BBP serial status */ 100 6629 zf162725 #define RAL_PHY_CSR9 0x04d2 /* RF serial control0 */ 101 6629 zf162725 #define RAL_PHY_CSR10 0x04d4 /* RF serial control1 */ 102 6629 zf162725 103 6629 zf162725 /* 104 6629 zf162725 * Statistics registers. 105 6629 zf162725 */ 106 6629 zf162725 #define RAL_STA_CSR0 0x04e0 /* FCS error */ 107 6629 zf162725 108 6629 zf162725 109 6629 zf162725 #define RAL_DISABLE_RX (1 << 0) 110 6629 zf162725 #define RAL_DROP_CRC (1 << 1) 111 6629 zf162725 #define RAL_DROP_PHY (1 << 2) 112 6629 zf162725 #define RAL_DROP_CTL (1 << 3) 113 6629 zf162725 #define RAL_DROP_NOT_TO_ME (1 << 4) 114 6629 zf162725 #define RAL_DROP_TODS (1 << 5) 115 6629 zf162725 #define RAL_DROP_BAD_VERSION (1 << 6) 116 6629 zf162725 #define RAL_DROP_MULTICAST (1 << 9) 117 6629 zf162725 #define RAL_DROP_BROADCAST (1 << 10) 118 6629 zf162725 119 6629 zf162725 #define RAL_SHORT_PREAMBLE (1 << 2) 120 6629 zf162725 121 6629 zf162725 #define RAL_RESET_ASIC (1 << 0) 122 6629 zf162725 #define RAL_RESET_BBP (1 << 1) 123 6629 zf162725 #define RAL_HOST_READY (1 << 2) 124 6629 zf162725 125 6629 zf162725 #define RAL_ENABLE_TSF (1 << 0) 126 6629 zf162725 #define RAL_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) 127 6629 zf162725 #define RAL_ENABLE_TBCN (1 << 3) 128 6629 zf162725 #define RAL_ENABLE_BEACON_GENERATOR (1 << 4) 129 6629 zf162725 130 6629 zf162725 #define RAL_RF_AWAKE (3 << 7) 131 6629 zf162725 #define RAL_BBP_AWAKE (3 << 5) 132 6629 zf162725 133 6629 zf162725 #define RAL_BBP_WRITE (1 << 15) 134 6629 zf162725 #define RAL_BBP_BUSY (1 << 0) 135 6629 zf162725 136 6629 zf162725 #define RAL_RF1_AUTOTUNE 0x08000 137 6629 zf162725 #define RAL_RF3_AUTOTUNE 0x00040 138 6629 zf162725 139 6629 zf162725 #define RAL_RF_2522 0x00 140 6629 zf162725 #define RAL_RF_2523 0x01 141 6629 zf162725 #define RAL_RF_2524 0x02 142 6629 zf162725 #define RAL_RF_2525 0x03 143 6629 zf162725 #define RAL_RF_2525E 0x04 144 6629 zf162725 #define RAL_RF_2526 0x05 145 6629 zf162725 /* dual-band RF */ 146 6629 zf162725 #define RAL_RF_5222 0x10 147 6629 zf162725 148 6629 zf162725 #define RAL_BBP_VERSION 0 149 6629 zf162725 #define RAL_BBP_TX 2 150 6629 zf162725 #define RAL_BBP_RX 14 151 6629 zf162725 152 6629 zf162725 #define RAL_BBP_ANTA 0x00 153 6629 zf162725 #define RAL_BBP_DIVERSITY 0x01 154 6629 zf162725 #define RAL_BBP_ANTB 0x02 155 6629 zf162725 #define RAL_BBP_ANTMASK 0x03 156 6629 zf162725 #define RAL_BBP_FLIPIQ 0x04 157 6629 zf162725 158 6629 zf162725 #define RAL_JAPAN_FILTER 0x08 159 6629 zf162725 160 6629 zf162725 #pragma pack(1) 161 6629 zf162725 struct ural_tx_desc { 162 6629 zf162725 uint32_t flags; 163 6629 zf162725 #define RAL_TX_RETRY(x) ((x) << 4) 164 6629 zf162725 #define RAL_TX_MORE_FRAG (1 << 8) 165 6629 zf162725 #define RAL_TX_ACK (1 << 9) 166 6629 zf162725 #define RAL_TX_TIMESTAMP (1 << 10) 167 6629 zf162725 #define RAL_TX_OFDM (1 << 11) 168 6629 zf162725 #define RAL_TX_NEWSEQ (1 << 12) 169 6629 zf162725 170 6629 zf162725 #define RAL_TX_IFS_MASK 0x00006000 171 6629 zf162725 #define RAL_TX_IFS_BACKOFF (0 << 13) 172 6629 zf162725 #define RAL_TX_IFS_SIFS (1 << 13) 173 6629 zf162725 #define RAL_TX_IFS_NEWBACKOFF (2 << 13) 174 6629 zf162725 #define RAL_TX_IFS_NONE (3 << 13) 175 6629 zf162725 176 6629 zf162725 uint16_t wme; 177 6629 zf162725 #define RAL_LOGCWMAX(x) (((x) & 0xf) << 12) 178 6629 zf162725 #define RAL_LOGCWMIN(x) (((x) & 0xf) << 8) 179 6629 zf162725 #define RAL_AIFSN(x) (((x) & 0x3) << 6) 180 6629 zf162725 #define RAL_IVOFFSET(x) (((x) & 0x3f)) 181 6629 zf162725 182 6629 zf162725 uint16_t reserved1; 183 6629 zf162725 uint8_t plcp_signal; 184 6629 zf162725 uint8_t plcp_service; 185 6629 zf162725 #define RAL_PLCP_LENGEXT 0x80 186 6629 zf162725 187 6629 zf162725 uint8_t plcp_length_lo; 188 6629 zf162725 uint8_t plcp_length_hi; 189 6629 zf162725 uint32_t iv; 190 6629 zf162725 uint32_t eiv; 191 6629 zf162725 }; 192 6629 zf162725 #pragma pack() 193 6629 zf162725 194 6629 zf162725 #pragma pack(1) 195 6629 zf162725 struct ural_rx_desc { 196 6629 zf162725 uint32_t flags; 197 6629 zf162725 #define RAL_RX_CRC_ERROR (1 << 5) 198 6629 zf162725 #define RAL_RX_OFDM (1 << 6) 199 6629 zf162725 #define RAL_RX_PHY_ERROR (1 << 7) 200 6629 zf162725 201 6629 zf162725 uint8_t rssi; 202 6629 zf162725 uint8_t rate; 203 6629 zf162725 uint16_t reserved; 204 6629 zf162725 205 6629 zf162725 uint32_t iv; 206 6629 zf162725 uint32_t eiv; 207 6629 zf162725 }; 208 6629 zf162725 #pragma pack() 209 6629 zf162725 210 6629 zf162725 #define RAL_RF_LOBUSY (1 << 15) 211 6629 zf162725 #define RAL_RF_BUSY ((uint32_t)1 << 31) 212 6629 zf162725 #define RAL_RF_20BIT (20 << 24) 213 6629 zf162725 214 6629 zf162725 #define RAL_RF1 0 215 6629 zf162725 #define RAL_RF2 2 216 6629 zf162725 #define RAL_RF3 1 217 6629 zf162725 #define RAL_RF4 3 218 6629 zf162725 219 6629 zf162725 #define RAL_EEPROM_ADDRESS 0x0004 220 6629 zf162725 #define RAL_EEPROM_TXPOWER 0x003c 221 6629 zf162725 #define RAL_EEPROM_CONFIG0 0x0016 222 6629 zf162725 #define RAL_EEPROM_BBP_BASE 0x001c 223 6629 zf162725 224 6629 zf162725 #ifdef __cplusplus 225 6629 zf162725 } 226 6629 zf162725 #endif 227 6629 zf162725 228 6629 zf162725 #endif /* _URAL_REG_H */ 229
Indexes created Sat Nov 28 12:39:51 UTC 2009
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