1 6629 zf162725 /* 2 9345 Quaker * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 6629 zf162725 * Use is subject to license terms. 4 6629 zf162725 */ 5 6629 zf162725 6 6629 zf162725 /* 7 6629 zf162725 * Copyright (c) 2005, 2006 8 6629 zf162725 * Damien Bergamini <damien.bergamini (at) free.fr> 9 6629 zf162725 * 10 6629 zf162725 * Permission to use, copy, modify, and distribute this software for any 11 6629 zf162725 * purpose with or without fee is hereby granted, provided that the above 12 6629 zf162725 * copyright notice and this permission notice appear in all copies. 13 6629 zf162725 * 14 6629 zf162725 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 6629 zf162725 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 6629 zf162725 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 6629 zf162725 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 6629 zf162725 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 6629 zf162725 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 6629 zf162725 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 6629 zf162725 */ 22 6629 zf162725 23 6629 zf162725 /* 24 6629 zf162725 * Ralink Technology RT2500USB chipset driver 25 6629 zf162725 * http://www.ralinktech.com/ 26 6629 zf162725 */ 27 6629 zf162725 #include <sys/types.h> 28 6629 zf162725 #include <sys/cmn_err.h> 29 6629 zf162725 #include <sys/strsubr.h> 30 6629 zf162725 #include <sys/modctl.h> 31 6629 zf162725 #include <sys/devops.h> 32 8275 Eric #include <sys/mac_provider.h> 33 6629 zf162725 #include <sys/mac_wifi.h> 34 6629 zf162725 #include <sys/net80211.h> 35 6629 zf162725 36 6629 zf162725 #define USBDRV_MAJOR_VER 2 37 6629 zf162725 #define USBDRV_MINOR_VER 0 38 6629 zf162725 #include <sys/usb/usba.h> 39 9345 Quaker #include <sys/usb/usba/usba_types.h> 40 6629 zf162725 41 6629 zf162725 #include "ural_reg.h" 42 6629 zf162725 #include "ural_var.h" 43 6629 zf162725 44 6629 zf162725 static void *ural_soft_state_p = NULL; 45 6629 zf162725 46 6629 zf162725 #define RAL_TXBUF_SIZE (IEEE80211_MAX_LEN) 47 6629 zf162725 #define RAL_RXBUF_SIZE (IEEE80211_MAX_LEN) 48 6629 zf162725 49 6629 zf162725 /* quickly determine if a given rate is CCK or OFDM */ 50 6629 zf162725 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 51 6629 zf162725 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 52 6629 zf162725 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 53 6629 zf162725 #define RAL_SIFS 10 /* us */ 54 6629 zf162725 #define RAL_RXTX_TURNAROUND 5 /* us */ 55 6629 zf162725 56 6629 zf162725 #define URAL_N(a) (sizeof (a) / sizeof ((a)[0])) 57 6629 zf162725 58 6629 zf162725 /* 59 6629 zf162725 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 60 6629 zf162725 */ 61 6629 zf162725 static const struct ieee80211_rateset ural_rateset_11a = 62 6629 zf162725 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 63 6629 zf162725 64 6629 zf162725 static const struct ieee80211_rateset ural_rateset_11b = 65 6629 zf162725 { 4, { 2, 4, 11, 22 } }; 66 6629 zf162725 67 6629 zf162725 static const struct ieee80211_rateset ural_rateset_11g = 68 6629 zf162725 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 69 6629 zf162725 70 6629 zf162725 /* 71 6629 zf162725 * Default values for MAC registers; values taken from the reference driver. 72 6629 zf162725 */ 73 6629 zf162725 static const struct { 74 6629 zf162725 uint16_t reg; 75 6629 zf162725 uint16_t val; 76 6629 zf162725 } ural_def_mac[] = { 77 6629 zf162725 { RAL_TXRX_CSR5, 0x8c8d }, 78 6629 zf162725 { RAL_TXRX_CSR6, 0x8b8a }, 79 6629 zf162725 { RAL_TXRX_CSR7, 0x8687 }, 80 6629 zf162725 { RAL_TXRX_CSR8, 0x0085 }, 81 6629 zf162725 { RAL_MAC_CSR13, 0x1111 }, 82 6629 zf162725 { RAL_MAC_CSR14, 0x1e11 }, 83 6629 zf162725 { RAL_TXRX_CSR21, 0xe78f }, 84 6629 zf162725 { RAL_MAC_CSR9, 0xff1d }, 85 6629 zf162725 { RAL_MAC_CSR11, 0x0002 }, 86 6629 zf162725 { RAL_MAC_CSR22, 0x0053 }, 87 6629 zf162725 { RAL_MAC_CSR15, 0x0000 }, 88 6629 zf162725 { RAL_MAC_CSR8, 0x0780 }, 89 6629 zf162725 { RAL_TXRX_CSR19, 0x0000 }, 90 6629 zf162725 { RAL_TXRX_CSR18, 0x005a }, 91 6629 zf162725 { RAL_PHY_CSR2, 0x0000 }, 92 6629 zf162725 { RAL_TXRX_CSR0, 0x1ec0 }, 93 6629 zf162725 { RAL_PHY_CSR4, 0x000f } 94 6629 zf162725 }; 95 6629 zf162725 96 6629 zf162725 /* 97 6629 zf162725 * Default values for BBP registers; values taken from the reference driver. 98 6629 zf162725 */ 99 6629 zf162725 static const struct { 100 6629 zf162725 uint8_t reg; 101 6629 zf162725 uint8_t val; 102 6629 zf162725 } ural_def_bbp[] = { 103 6629 zf162725 { 3, 0x02 }, 104 6629 zf162725 { 4, 0x19 }, 105 6629 zf162725 { 14, 0x1c }, 106 6629 zf162725 { 15, 0x30 }, 107 6629 zf162725 { 16, 0xac }, 108 6629 zf162725 { 17, 0x48 }, 109 6629 zf162725 { 18, 0x18 }, 110 6629 zf162725 { 19, 0xff }, 111 6629 zf162725 { 20, 0x1e }, 112 6629 zf162725 { 21, 0x08 }, 113 6629 zf162725 { 22, 0x08 }, 114 6629 zf162725 { 23, 0x08 }, 115 6629 zf162725 { 24, 0x80 }, 116 6629 zf162725 { 25, 0x50 }, 117 6629 zf162725 { 26, 0x08 }, 118 6629 zf162725 { 27, 0x23 }, 119 6629 zf162725 { 30, 0x10 }, 120 6629 zf162725 { 31, 0x2b }, 121 6629 zf162725 { 32, 0xb9 }, 122 6629 zf162725 { 34, 0x12 }, 123 6629 zf162725 { 35, 0x50 }, 124 6629 zf162725 { 39, 0xc4 }, 125 6629 zf162725 { 40, 0x02 }, 126 6629 zf162725 { 41, 0x60 }, 127 6629 zf162725 { 53, 0x10 }, 128 6629 zf162725 { 54, 0x18 }, 129 6629 zf162725 { 56, 0x08 }, 130 6629 zf162725 { 57, 0x10 }, 131 6629 zf162725 { 58, 0x08 }, 132 6629 zf162725 { 61, 0x60 }, 133 6629 zf162725 { 62, 0x10 }, 134 6629 zf162725 { 75, 0xff } 135 6629 zf162725 }; 136 6629 zf162725 137 6629 zf162725 /* 138 6629 zf162725 * Default values for RF register R2 indexed by channel numbers. 139 6629 zf162725 */ 140 6629 zf162725 static const uint32_t ural_rf2522_r2[] = { 141 6629 zf162725 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 142 6629 zf162725 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 143 6629 zf162725 }; 144 6629 zf162725 145 6629 zf162725 static const uint32_t ural_rf2523_r2[] = { 146 6629 zf162725 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 147 6629 zf162725 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 148 6629 zf162725 }; 149 6629 zf162725 150 6629 zf162725 static const uint32_t ural_rf2524_r2[] = { 151 6629 zf162725 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 152 6629 zf162725 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 153 6629 zf162725 }; 154 6629 zf162725 155 6629 zf162725 static const uint32_t ural_rf2525_r2[] = { 156 6629 zf162725 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 157 6629 zf162725 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 158 6629 zf162725 }; 159 6629 zf162725 160 6629 zf162725 static const uint32_t ural_rf2525_hi_r2[] = { 161 6629 zf162725 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 162 6629 zf162725 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 163 6629 zf162725 }; 164 6629 zf162725 165 6629 zf162725 static const uint32_t ural_rf2525e_r2[] = { 166 6629 zf162725 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 167 6629 zf162725 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 168 6629 zf162725 }; 169 6629 zf162725 170 6629 zf162725 static const uint32_t ural_rf2526_hi_r2[] = { 171 6629 zf162725 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 172 6629 zf162725 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 173 6629 zf162725 }; 174 6629 zf162725 175 6629 zf162725 static const uint32_t ural_rf2526_r2[] = { 176 6629 zf162725 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 177 6629 zf162725 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 178 6629 zf162725 }; 179 6629 zf162725 180 6629 zf162725 /* 181 6629 zf162725 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 182 6629 zf162725 * values taken from the reference driver. 183 6629 zf162725 */ 184 6629 zf162725 static const struct { 185 6629 zf162725 uint8_t chan; 186 6629 zf162725 uint32_t r1; 187 6629 zf162725 uint32_t r2; 188 6629 zf162725 uint32_t r4; 189 6629 zf162725 } ural_rf5222[] = { 190 6629 zf162725 { 1, 0x08808, 0x0044d, 0x00282 }, 191 6629 zf162725 { 2, 0x08808, 0x0044e, 0x00282 }, 192 6629 zf162725 { 3, 0x08808, 0x0044f, 0x00282 }, 193 6629 zf162725 { 4, 0x08808, 0x00460, 0x00282 }, 194 6629 zf162725 { 5, 0x08808, 0x00461, 0x00282 }, 195 6629 zf162725 { 6, 0x08808, 0x00462, 0x00282 }, 196 6629 zf162725 { 7, 0x08808, 0x00463, 0x00282 }, 197 6629 zf162725 { 8, 0x08808, 0x00464, 0x00282 }, 198 6629 zf162725 { 9, 0x08808, 0x00465, 0x00282 }, 199 6629 zf162725 { 10, 0x08808, 0x00466, 0x00282 }, 200 6629 zf162725 { 11, 0x08808, 0x00467, 0x00282 }, 201 6629 zf162725 { 12, 0x08808, 0x00468, 0x00282 }, 202 6629 zf162725 { 13, 0x08808, 0x00469, 0x00282 }, 203 6629 zf162725 { 14, 0x08808, 0x0046b, 0x00286 }, 204 6629 zf162725 205 6629 zf162725 { 36, 0x08804, 0x06225, 0x00287 }, 206 6629 zf162725 { 40, 0x08804, 0x06226, 0x00287 }, 207 6629 zf162725 { 44, 0x08804, 0x06227, 0x00287 }, 208 6629 zf162725 { 48, 0x08804, 0x06228, 0x00287 }, 209 6629 zf162725 { 52, 0x08804, 0x06229, 0x00287 }, 210 6629 zf162725 { 56, 0x08804, 0x0622a, 0x00287 }, 211 6629 zf162725 { 60, 0x08804, 0x0622b, 0x00287 }, 212 6629 zf162725 { 64, 0x08804, 0x0622c, 0x00287 }, 213 6629 zf162725 214 6629 zf162725 { 100, 0x08804, 0x02200, 0x00283 }, 215 6629 zf162725 { 104, 0x08804, 0x02201, 0x00283 }, 216 6629 zf162725 { 108, 0x08804, 0x02202, 0x00283 }, 217 6629 zf162725 { 112, 0x08804, 0x02203, 0x00283 }, 218 6629 zf162725 { 116, 0x08804, 0x02204, 0x00283 }, 219 6629 zf162725 { 120, 0x08804, 0x02205, 0x00283 }, 220 6629 zf162725 { 124, 0x08804, 0x02206, 0x00283 }, 221 6629 zf162725 { 128, 0x08804, 0x02207, 0x00283 }, 222 6629 zf162725 { 132, 0x08804, 0x02208, 0x00283 }, 223 6629 zf162725 { 136, 0x08804, 0x02209, 0x00283 }, 224 6629 zf162725 { 140, 0x08804, 0x0220a, 0x00283 }, 225 6629 zf162725 226 6629 zf162725 { 149, 0x08808, 0x02429, 0x00281 }, 227 6629 zf162725 { 153, 0x08808, 0x0242b, 0x00281 }, 228 6629 zf162725 { 157, 0x08808, 0x0242d, 0x00281 }, 229 6629 zf162725 { 161, 0x08808, 0x0242f, 0x00281 } 230 6629 zf162725 }; 231 6629 zf162725 232 6629 zf162725 /* 233 6629 zf162725 * device operations 234 6629 zf162725 */ 235 6629 zf162725 static int ural_attach(dev_info_t *, ddi_attach_cmd_t); 236 6629 zf162725 static int ural_detach(dev_info_t *, ddi_detach_cmd_t); 237 6629 zf162725 238 6629 zf162725 /* 239 6629 zf162725 * Module Loading Data & Entry Points 240 6629 zf162725 */ 241 6629 zf162725 DDI_DEFINE_STREAM_OPS(ural_dev_ops, nulldev, nulldev, ural_attach, 242 8099 Quaker ural_detach, nodev, NULL, D_MP, NULL, ddi_quiesce_not_needed); 243 6629 zf162725 244 6629 zf162725 static struct modldrv ural_modldrv = { 245 6629 zf162725 &mod_driverops, /* Type of module. This one is a driver */ 246 9345 Quaker "ural driver v1.4", /* short description */ 247 6629 zf162725 &ural_dev_ops /* driver specific ops */ 248 6629 zf162725 }; 249 6629 zf162725 250 6629 zf162725 static struct modlinkage modlinkage = { 251 6629 zf162725 MODREV_1, 252 6629 zf162725 (void *)&ural_modldrv, 253 6629 zf162725 NULL 254 6629 zf162725 }; 255 6629 zf162725 256 6629 zf162725 static int ural_m_stat(void *, uint_t, uint64_t *); 257 6629 zf162725 static int ural_m_start(void *); 258 6629 zf162725 static void ural_m_stop(void *); 259 6629 zf162725 static int ural_m_promisc(void *, boolean_t); 260 6629 zf162725 static int ural_m_multicst(void *, boolean_t, const uint8_t *); 261 6629 zf162725 static int ural_m_unicst(void *, const uint8_t *); 262 6629 zf162725 static mblk_t *ural_m_tx(void *, mblk_t *); 263 6629 zf162725 static void ural_m_ioctl(void *, queue_t *, mblk_t *); 264 8099 Quaker static int ural_m_setprop(void *, const char *, mac_prop_id_t, 265 8099 Quaker uint_t, const void *); 266 8099 Quaker static int ural_m_getprop(void *, const char *, mac_prop_id_t, 267 8118 Vasumathi uint_t, uint_t, void *, uint_t *); 268 6629 zf162725 269 6629 zf162725 static mac_callbacks_t ural_m_callbacks = { 270 8099 Quaker MC_IOCTL | MC_SETPROP | MC_GETPROP, 271 6629 zf162725 ural_m_stat, 272 6629 zf162725 ural_m_start, 273 6629 zf162725 ural_m_stop, 274 6629 zf162725 ural_m_promisc, 275 6629 zf162725 ural_m_multicst, 276 6629 zf162725 ural_m_unicst, 277 6629 zf162725 ural_m_tx, 278 6629 zf162725 ural_m_ioctl, 279 8099 Quaker NULL, /* mc_getcapab */ 280 8099 Quaker NULL, 281 8099 Quaker NULL, 282 8099 Quaker ural_m_setprop, 283 8099 Quaker ural_m_getprop 284 6629 zf162725 }; 285 6629 zf162725 286 6629 zf162725 static void ural_amrr_start(struct ural_softc *, struct ieee80211_node *); 287 6629 zf162725 static int ural_tx_trigger(struct ural_softc *, mblk_t *); 288 6629 zf162725 static int ural_rx_trigger(struct ural_softc *); 289 6629 zf162725 290 6629 zf162725 uint32_t ural_dbg_flags = 0; 291 6629 zf162725 292 6629 zf162725 void 293 6629 zf162725 ral_debug(uint32_t dbg_flags, const int8_t *fmt, ...) 294 6629 zf162725 { 295 6629 zf162725 va_list args; 296 6629 zf162725 297 6629 zf162725 if (dbg_flags & ural_dbg_flags) { 298 6629 zf162725 va_start(args, fmt); 299 6629 zf162725 vcmn_err(CE_CONT, fmt, args); 300 6629 zf162725 va_end(args); 301 6629 zf162725 } 302 6629 zf162725 } 303 6629 zf162725 304 6629 zf162725 static uint16_t 305 6629 zf162725 ural_read(struct ural_softc *sc, uint16_t reg) 306 6629 zf162725 { 307 6629 zf162725 usb_ctrl_setup_t req; 308 6629 zf162725 usb_cr_t cr; 309 6629 zf162725 usb_cb_flags_t cf; 310 6629 zf162725 mblk_t *mp; 311 6629 zf162725 int err; 312 6629 zf162725 uint16_t val; 313 6629 zf162725 314 6629 zf162725 bzero(&req, sizeof (req)); 315 6629 zf162725 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_DEV_TO_HOST; 316 6629 zf162725 req.bRequest = RAL_READ_MAC; 317 6629 zf162725 req.wValue = 0; 318 6629 zf162725 req.wIndex = reg; 319 6629 zf162725 req.wLength = sizeof (uint16_t); 320 6629 zf162725 321 6629 zf162725 mp = NULL; 322 6629 zf162725 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp, 323 6629 zf162725 &cr, &cf, 0); 324 6629 zf162725 325 6629 zf162725 if (err != USB_SUCCESS) { 326 9345 Quaker ral_debug(RAL_DBG_ERR, 327 6629 zf162725 "ural_read(): could not read MAC register:" 328 6629 zf162725 " cr:%s(%d), cf:(%x)\n", 329 6629 zf162725 usb_str_cr(cr), cr, cf); 330 6629 zf162725 return (0); 331 6629 zf162725 } 332 6629 zf162725 333 6629 zf162725 bcopy(mp->b_rptr, &val, sizeof (uint16_t)); 334 6629 zf162725 335 6629 zf162725 if (mp) 336 6629 zf162725 freemsg(mp); 337 6629 zf162725 338 6629 zf162725 return (LE_16(val)); 339 6629 zf162725 } 340 6629 zf162725 341 6629 zf162725 static void 342 6629 zf162725 ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 343 6629 zf162725 { 344 6629 zf162725 usb_ctrl_setup_t req; 345 6629 zf162725 usb_cr_t cr; 346 6629 zf162725 usb_cb_flags_t cf; 347 6629 zf162725 mblk_t *mp; 348 6629 zf162725 int err; 349 6629 zf162725 350 6629 zf162725 bzero(&req, sizeof (req)); 351 6629 zf162725 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_DEV_TO_HOST; 352 6629 zf162725 req.bRequest = RAL_READ_MULTI_MAC; 353 6629 zf162725 req.wValue = 0; 354 6629 zf162725 req.wIndex = reg; 355 6629 zf162725 req.wLength = (uint16_t)len; 356 6629 zf162725 req.attrs = USB_ATTRS_AUTOCLEARING; 357 6629 zf162725 358 6629 zf162725 mp = NULL; 359 6629 zf162725 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp, 360 6629 zf162725 &cr, &cf, 0); 361 6629 zf162725 362 6629 zf162725 if (err != USB_SUCCESS) { 363 9345 Quaker ral_debug(RAL_DBG_ERR, 364 6629 zf162725 "ural_read_multi(): could not read MAC register:" 365 6629 zf162725 "cr:%s(%d), cf:(%x)\n", 366 6629 zf162725 usb_str_cr(cr), cr, cf); 367 6629 zf162725 return; 368 6629 zf162725 } 369 6629 zf162725 370 6629 zf162725 bcopy(mp->b_rptr, buf, len); 371 6629 zf162725 372 6629 zf162725 if (mp) 373 6629 zf162725 freemsg(mp); 374 6629 zf162725 } 375 6629 zf162725 376 6629 zf162725 static void 377 6629 zf162725 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 378 6629 zf162725 { 379 6629 zf162725 usb_ctrl_setup_t req; 380 6629 zf162725 usb_cr_t cr; 381 6629 zf162725 usb_cb_flags_t cf; 382 6629 zf162725 int err; 383 6629 zf162725 384 6629 zf162725 bzero(&req, sizeof (req)); 385 6629 zf162725 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_HOST_TO_DEV; 386 6629 zf162725 req.bRequest = RAL_WRITE_MAC; 387 6629 zf162725 req.wValue = val; 388 6629 zf162725 req.wIndex = reg; 389 6629 zf162725 req.wLength = 0; 390 6629 zf162725 req.attrs = USB_ATTRS_NONE; 391 6629 zf162725 392 6629 zf162725 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, NULL, 393 6629 zf162725 &cr, &cf, 0); 394 6629 zf162725 395 6629 zf162725 if (err != USB_SUCCESS) { 396 9345 Quaker ral_debug(RAL_DBG_ERR, 397 6629 zf162725 "ural_write(): could not write MAC register:" 398 6629 zf162725 "cr:%s(%d), cf:(%x)\n", 399 6629 zf162725 usb_str_cr(cr), cr, cf); 400 6629 zf162725 } 401 6629 zf162725 } 402 6629 zf162725 403 6629 zf162725 /* ARGSUSED */ 404 6629 zf162725 static void 405 6629 zf162725 ural_txeof(usb_pipe_handle_t pipe, usb_bulk_req_t *req) 406 6629 zf162725 { 407 6629 zf162725 struct ural_softc *sc = (struct ural_softc *)req->bulk_client_private; 408 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 409 6629 zf162725 410 9345 Quaker ral_debug(RAL_DBG_TX, 411 6629 zf162725 "ural_txeof(): cr:%s(%d), flags:0x%x, tx_queued:%d", 412 6629 zf162725 usb_str_cr(req->bulk_completion_reason), 413 6629 zf162725 req->bulk_completion_reason, 414 6629 zf162725 req->bulk_cb_flags, 415 6629 zf162725 sc->tx_queued); 416 6629 zf162725 417 6629 zf162725 if (req->bulk_completion_reason != USB_CR_OK) 418 6629 zf162725 sc->sc_tx_err++; 419 6629 zf162725 420 6629 zf162725 mutex_enter(&sc->tx_lock); 421 6629 zf162725 422 6629 zf162725 sc->tx_queued--; 423 6629 zf162725 sc->sc_tx_timer = 0; 424 6629 zf162725 425 6629 zf162725 if (sc->sc_need_sched) { 426 6629 zf162725 sc->sc_need_sched = 0; 427 6629 zf162725 mac_tx_update(ic->ic_mach); 428 6629 zf162725 } 429 6629 zf162725 430 6629 zf162725 mutex_exit(&sc->tx_lock); 431 6629 zf162725 usb_free_bulk_req(req); 432 6629 zf162725 } 433 6629 zf162725 434 6629 zf162725 /* ARGSUSED */ 435 6629 zf162725 static void 436 6629 zf162725 ural_rxeof(usb_pipe_handle_t pipe, usb_bulk_req_t *req) 437 6629 zf162725 { 438 6629 zf162725 struct ural_softc *sc = (struct ural_softc *)req->bulk_client_private; 439 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 440 6629 zf162725 441 6629 zf162725 struct ural_rx_desc *desc; 442 6629 zf162725 struct ieee80211_frame *wh; 443 6629 zf162725 struct ieee80211_node *ni; 444 6629 zf162725 445 6629 zf162725 mblk_t *m, *mp; 446 6629 zf162725 int len, pktlen; 447 6629 zf162725 char *rxbuf; 448 6629 zf162725 449 6629 zf162725 mp = req->bulk_data; 450 6629 zf162725 req->bulk_data = NULL; 451 6629 zf162725 452 9345 Quaker ral_debug(RAL_DBG_RX, 453 6629 zf162725 "ural_rxeof(): cr:%s(%d), flags:0x%x, rx_queued:%d", 454 6629 zf162725 usb_str_cr(req->bulk_completion_reason), 455 6629 zf162725 req->bulk_completion_reason, 456 6629 zf162725 req->bulk_cb_flags, 457 6629 zf162725 sc->rx_queued); 458 6629 zf162725 459 6629 zf162725 if (req->bulk_completion_reason != USB_CR_OK) { 460 6629 zf162725 sc->sc_rx_err++; 461 6629 zf162725 goto fail; 462 6629 zf162725 } 463 6629 zf162725 464 6629 zf162725 len = (uintptr_t)mp->b_wptr - (uintptr_t)mp->b_rptr; 465 6629 zf162725 rxbuf = (char *)mp->b_rptr; 466 6629 zf162725 467 6629 zf162725 if (len < RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN) { 468 9345 Quaker ral_debug(RAL_DBG_ERR, 469 6629 zf162725 "ural_rxeof(): xfer too short %d\n", len); 470 6629 zf162725 sc->sc_rx_err++; 471 6629 zf162725 goto fail; 472 6629 zf162725 } 473 6629 zf162725 474 6629 zf162725 /* rx descriptor is located at the end */ 475 6629 zf162725 desc = (struct ural_rx_desc *)(rxbuf + len - RAL_RX_DESC_SIZE); 476 6629 zf162725 477 6629 zf162725 if ((LE_32(desc->flags) & RAL_RX_PHY_ERROR) || 478 6629 zf162725 (LE_32(desc->flags) & RAL_RX_CRC_ERROR)) { 479 6629 zf162725 /* 480 6629 zf162725 * This should not happen since we did not request to receive 481 6629 zf162725 * those frames when we filled RAL_TXRX_CSR2. 482 6629 zf162725 */ 483 9345 Quaker ral_debug(RAL_DBG_ERR, "PHY or CRC error\n"); 484 6629 zf162725 sc->sc_rx_err++; 485 6629 zf162725 goto fail; 486 6629 zf162725 } 487 6629 zf162725 488 6629 zf162725 pktlen = (LE_32(desc->flags) >> 16) & 0xfff; 489 6629 zf162725 490 6629 zf162725 if (pktlen > (len - RAL_RX_DESC_SIZE)) { 491 9345 Quaker ral_debug(RAL_DBG_ERR, 492 6629 zf162725 "ural_rxeof(): pktlen mismatch <%d, %d>.\n", pktlen, len); 493 6629 zf162725 goto fail; 494 6629 zf162725 } 495 6629 zf162725 496 6629 zf162725 /* Strip trailing 802.11 MAC FCS. */ 497 6629 zf162725 pktlen -= IEEE80211_CRC_LEN; 498 6629 zf162725 499 6629 zf162725 if ((m = allocb(pktlen, BPRI_MED)) == NULL) { 500 9345 Quaker ral_debug(RAL_DBG_ERR, 501 6629 zf162725 "ural_rxeof(): allocate mblk failed.\n"); 502 6629 zf162725 sc->sc_rx_nobuf++; 503 6629 zf162725 goto fail; 504 6629 zf162725 } 505 6629 zf162725 506 6629 zf162725 bcopy(rxbuf, m->b_rptr, pktlen); 507 6629 zf162725 m->b_wptr += pktlen; 508 6629 zf162725 509 6629 zf162725 wh = (struct ieee80211_frame *)m->b_rptr; 510 6629 zf162725 ni = ieee80211_find_rxnode(ic, wh); 511 6629 zf162725 512 6629 zf162725 /* send the frame to the 802.11 layer */ 513 6629 zf162725 (void) ieee80211_input(ic, m, ni, desc->rssi, 0); 514 6629 zf162725 515 6629 zf162725 /* node is no longer needed */ 516 6629 zf162725 ieee80211_free_node(ni); 517 6629 zf162725 fail: 518 6629 zf162725 mutex_enter(&sc->rx_lock); 519 6629 zf162725 sc->rx_queued--; 520 6629 zf162725 mutex_exit(&sc->rx_lock); 521 6629 zf162725 522 6629 zf162725 freemsg(mp); 523 6629 zf162725 usb_free_bulk_req(req); 524 6629 zf162725 525 6629 zf162725 if (RAL_IS_RUNNING(sc)) 526 6629 zf162725 (void) ural_rx_trigger(sc); 527 6629 zf162725 } 528 6629 zf162725 529 6629 zf162725 /* 530 6629 zf162725 * Return the expected ack rate for a frame transmitted at rate `rate'. 531 6629 zf162725 * this should depend on the destination node basic rate set. 532 6629 zf162725 */ 533 6629 zf162725 static int 534 6629 zf162725 ural_ack_rate(struct ieee80211com *ic, int rate) 535 6629 zf162725 { 536 6629 zf162725 switch (rate) { 537 6629 zf162725 /* CCK rates */ 538 6629 zf162725 case 2: 539 6629 zf162725 return (2); 540 6629 zf162725 case 4: 541 6629 zf162725 case 11: 542 6629 zf162725 case 22: 543 6629 zf162725 return ((ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate); 544 6629 zf162725 545 6629 zf162725 /* OFDM rates */ 546 6629 zf162725 case 12: 547 6629 zf162725 case 18: 548 6629 zf162725 return (12); 549 6629 zf162725 case 24: 550 6629 zf162725 case 36: 551 6629 zf162725 return (24); 552 6629 zf162725 case 48: 553 6629 zf162725 case 72: 554 6629 zf162725 case 96: 555 6629 zf162725 case 108: 556 6629 zf162725 return (48); 557 6629 zf162725 } 558 6629 zf162725 559 6629 zf162725 /* default to 1Mbps */ 560 6629 zf162725 return (2); 561 6629 zf162725 } 562 6629 zf162725 563 6629 zf162725 /* 564 6629 zf162725 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 565 6629 zf162725 * The function automatically determines the operating mode depending on the 566 6629 zf162725 * given rate. `flags' indicates whether short preamble is in use or not. 567 6629 zf162725 */ 568 6629 zf162725 static uint16_t 569 6629 zf162725 ural_txtime(int len, int rate, uint32_t flags) 570 6629 zf162725 { 571 6629 zf162725 uint16_t txtime; 572 6629 zf162725 573 6629 zf162725 if (RAL_RATE_IS_OFDM(rate)) { 574 6629 zf162725 /* IEEE Std 802.11a-1999, pp. 37 */ 575 6629 zf162725 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 576 6629 zf162725 txtime = 16 + 4 + 4 * txtime + 6; 577 6629 zf162725 } else { 578 6629 zf162725 /* IEEE Std 802.11b-1999, pp. 28 */ 579 6629 zf162725 txtime = (16 * len + rate - 1) / rate; 580 6629 zf162725 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 581 6629 zf162725 txtime += 72 + 24; 582 6629 zf162725 else 583 6629 zf162725 txtime += 144 + 48; 584 6629 zf162725 } 585 6629 zf162725 return (txtime); 586 6629 zf162725 } 587 6629 zf162725 588 6629 zf162725 static uint8_t 589 6629 zf162725 ural_plcp_signal(int rate) 590 6629 zf162725 { 591 6629 zf162725 switch (rate) { 592 6629 zf162725 /* CCK rates (returned values are device-dependent) */ 593 6629 zf162725 case 2: return (0x0); 594 6629 zf162725 case 4: return (0x1); 595 6629 zf162725 case 11: return (0x2); 596 6629 zf162725 case 22: return (0x3); 597 6629 zf162725 598 6629 zf162725 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 599 6629 zf162725 case 12: return (0xb); 600 6629 zf162725 case 18: return (0xf); 601 6629 zf162725 case 24: return (0xa); 602 6629 zf162725 case 36: return (0xe); 603 6629 zf162725 case 48: return (0x9); 604 6629 zf162725 case 72: return (0xd); 605 6629 zf162725 case 96: return (0x8); 606 6629 zf162725 case 108: return (0xc); 607 6629 zf162725 608 6629 zf162725 /* unsupported rates (should not get there) */ 609 6629 zf162725 default: return (0xff); 610 6629 zf162725 } 611 6629 zf162725 } 612 6629 zf162725 613 6629 zf162725 static void 614 6629 zf162725 ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 615 6629 zf162725 uint32_t flags, int len, int rate) 616 6629 zf162725 { 617 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 618 6629 zf162725 uint16_t plcp_length; 619 6629 zf162725 int remainder; 620 6629 zf162725 621 6629 zf162725 desc->flags = LE_32(flags); 622 6629 zf162725 desc->flags |= LE_32(RAL_TX_NEWSEQ); 623 6629 zf162725 desc->flags |= LE_32(len << 16); 624 6629 zf162725 625 6629 zf162725 desc->wme = LE_16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 626 6629 zf162725 desc->wme |= LE_16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 627 6629 zf162725 628 6629 zf162725 /* setup PLCP fields */ 629 6629 zf162725 desc->plcp_signal = ural_plcp_signal(rate); 630 6629 zf162725 desc->plcp_service = 4; 631 6629 zf162725 632 6629 zf162725 len += IEEE80211_CRC_LEN; 633 6629 zf162725 if (RAL_RATE_IS_OFDM(rate)) { 634 6629 zf162725 desc->flags |= LE_32(RAL_TX_OFDM); 635 6629 zf162725 636 6629 zf162725 plcp_length = len & 0xfff; 637 6629 zf162725 desc->plcp_length_hi = plcp_length >> 6; 638 6629 zf162725 desc->plcp_length_lo = plcp_length & 0x3f; 639 6629 zf162725 } else { 640 6629 zf162725 plcp_length = (16 * len + rate - 1) / rate; 641 6629 zf162725 if (rate == 22) { 642 6629 zf162725 remainder = (16 * len) % 22; 643 6629 zf162725 if (remainder != 0 && remainder < 7) 644 6629 zf162725 desc->plcp_service |= RAL_PLCP_LENGEXT; 645 6629 zf162725 } 646 6629 zf162725 desc->plcp_length_hi = plcp_length >> 8; 647 6629 zf162725 desc->plcp_length_lo = plcp_length & 0xff; 648 6629 zf162725 649 6629 zf162725 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 650 6629 zf162725 desc->plcp_signal |= 0x08; 651 6629 zf162725 } 652 6629 zf162725 653 6629 zf162725 desc->iv = 0; 654 6629 zf162725 desc->eiv = 0; 655 6629 zf162725 } 656 6629 zf162725 657 6629 zf162725 #define RAL_TX_TIMEOUT 5 658 6629 zf162725 659 6629 zf162725 static int 660 6629 zf162725 ural_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type) 661 6629 zf162725 { 662 6629 zf162725 struct ural_softc *sc = (struct ural_softc *)ic; 663 6629 zf162725 struct ural_tx_desc *desc; 664 6629 zf162725 665 6629 zf162725 struct ieee80211_frame *wh; 666 6629 zf162725 struct ieee80211_key *k; 667 6629 zf162725 668 6629 zf162725 uint16_t dur; 669 6629 zf162725 uint32_t flags = 0; 670 6629 zf162725 int rate, err = DDI_SUCCESS; 671 6629 zf162725 672 6629 zf162725 struct ieee80211_node *ni = NULL; 673 6629 zf162725 mblk_t *m, *m0; 674 6629 zf162725 int off, mblen, pktlen, xferlen; 675 6629 zf162725 676 9345 Quaker /* discard packets while suspending or not inited */ 677 9345 Quaker if (!RAL_IS_RUNNING(sc)) { 678 9345 Quaker freemsg(mp); 679 9345 Quaker return (ENXIO); 680 9345 Quaker } 681 9345 Quaker 682 6629 zf162725 mutex_enter(&sc->tx_lock); 683 6629 zf162725 684 6629 zf162725 if (sc->tx_queued > RAL_TX_LIST_COUNT) { 685 9345 Quaker ral_debug(RAL_DBG_TX, "ural_send(): " 686 6629 zf162725 "no TX buffer available!\n"); 687 6629 zf162725 if ((type & IEEE80211_FC0_TYPE_MASK) == 688 6629 zf162725 IEEE80211_FC0_TYPE_DATA) { 689 6629 zf162725 sc->sc_need_sched = 1; 690 6629 zf162725 } 691 6629 zf162725 sc->sc_tx_nobuf++; 692 6629 zf162725 err = ENOMEM; 693 6629 zf162725 goto fail; 694 6629 zf162725 } 695 6629 zf162725 696 6629 zf162725 m = allocb(RAL_TXBUF_SIZE + RAL_TX_DESC_SIZE, BPRI_MED); 697 6629 zf162725 if (m == NULL) { 698 9345 Quaker ral_debug(RAL_DBG_ERR, "ural_send(): can't alloc mblk.\n"); 699 6629 zf162725 err = DDI_FAILURE; 700 6629 zf162725 goto fail; 701 6629 zf162725 } 702 6629 zf162725 703 6629 zf162725 m->b_rptr += RAL_TX_DESC_SIZE; /* skip TX descriptor */ 704 6629 zf162725 m->b_wptr += RAL_TX_DESC_SIZE; 705 6629 zf162725 706 6629 zf162725 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) { 707 6629 zf162725 mblen = (uintptr_t)m0->b_wptr - (uintptr_t)m0->b_rptr; 708 6629 zf162725 (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen); 709 6629 zf162725 off += mblen; 710 6629 zf162725 } 711 6629 zf162725 m->b_wptr += off; 712 6629 zf162725 713 6629 zf162725 wh = (struct ieee80211_frame *)m->b_rptr; 714 6629 zf162725 715 6629 zf162725 ni = ieee80211_find_txnode(ic, wh->i_addr1); 716 6629 zf162725 if (ni == NULL) { 717 6629 zf162725 err = DDI_FAILURE; 718 6629 zf162725 sc->sc_tx_err++; 719 6629 zf162725 freemsg(m); 720 6629 zf162725 goto fail; 721 6629 zf162725 } 722 6629 zf162725 723 6629 zf162725 if ((type & IEEE80211_FC0_TYPE_MASK) == 724 6629 zf162725 IEEE80211_FC0_TYPE_DATA) { 725 6629 zf162725 (void) ieee80211_encap(ic, m, ni); 726 6629 zf162725 } 727 6629 zf162725 728 6629 zf162725 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 729 6629 zf162725 k = ieee80211_crypto_encap(ic, m); 730 6629 zf162725 if (k == NULL) { 731 6629 zf162725 sc->sc_tx_err++; 732 6629 zf162725 freemsg(m); 733 6629 zf162725 err = DDI_FAILURE; 734 6629 zf162725 goto fail; 735 6629 zf162725 } 736 6629 zf162725 /* packet header may have moved, reset our local pointer */ 737 6629 zf162725 wh = (struct ieee80211_frame *)m->b_rptr; 738 6629 zf162725 } 739 6629 zf162725 740 6629 zf162725 m->b_rptr -= RAL_TX_DESC_SIZE; /* restore */ 741 6629 zf162725 desc = (struct ural_tx_desc *)m->b_rptr; 742 6629 zf162725 743 6629 zf162725 if ((type & IEEE80211_FC0_TYPE_MASK) == 744 6629 zf162725 IEEE80211_FC0_TYPE_DATA) { /* DATA */ 745 6629 zf162725 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) 746 6629 zf162725 rate = ic->ic_bss->in_rates.ir_rates[ic->ic_fixed_rate]; 747 6629 zf162725 else 748 6629 zf162725 rate = ni->in_rates.ir_rates[ni->in_txrate]; 749 6629 zf162725 750 6629 zf162725 rate &= IEEE80211_RATE_VAL; 751 6629 zf162725 if (rate <= 0) { 752 6629 zf162725 rate = 2; /* basic rate */ 753 6629 zf162725 } 754 6629 zf162725 755 6629 zf162725 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 756 6629 zf162725 flags |= RAL_TX_ACK; 757 6629 zf162725 flags |= RAL_TX_RETRY(7); 758 6629 zf162725 759 6629 zf162725 dur = ural_txtime(RAL_ACK_SIZE, ural_ack_rate(ic, rate), 760 6629 zf162725 ic->ic_flags) + RAL_SIFS; 761 6629 zf162725 *(uint16_t *)(uintptr_t)wh->i_dur = LE_16(dur); 762 6629 zf162725 } 763 6629 zf162725 } else { /* MGMT */ 764 6629 zf162725 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 765 6629 zf162725 766 6629 zf162725 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 767 6629 zf162725 flags |= RAL_TX_ACK; 768 6629 zf162725 769 6629 zf162725 dur = ural_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) 770 6629 zf162725 + RAL_SIFS; 771 6629 zf162725 *(uint16_t *)(uintptr_t)wh->i_dur = LE_16(dur); 772 6629 zf162725 773 6629 zf162725 /* tell hardware to add timestamp for probe responses */ 774 6629 zf162725 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 775 6629 zf162725 IEEE80211_FC0_TYPE_MGT && 776 6629 zf162725 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 777 6629 zf162725 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 778 6629 zf162725 flags |= RAL_TX_TIMESTAMP; 779 6629 zf162725 } 780 6629 zf162725 } 781 6629 zf162725 782 6629 zf162725 pktlen = (uintptr_t)m->b_wptr - (uintptr_t)m->b_rptr - RAL_TX_DESC_SIZE; 783 6629 zf162725 ural_setup_tx_desc(sc, desc, flags, pktlen, rate); 784 6629 zf162725 785 6629 zf162725 /* align end on a 2-bytes boundary */ 786 6629 zf162725 xferlen = (RAL_TX_DESC_SIZE + pktlen + 1) & ~1; 787 6629 zf162725 788 6629 zf162725 /* 789 6629 zf162725 * No space left in the last URB to store the extra 2 bytes, force 790 6629 zf162725 * sending of another URB. 791 6629 zf162725 */ 792 6629 zf162725 if ((xferlen % 64) == 0) 793 6629 zf162725 xferlen += 2; 794 6629 zf162725 795 6629 zf162725 m->b_wptr = m->b_rptr + xferlen; 796 6629 zf162725 797 9345 Quaker ral_debug(RAL_DBG_TX, "sending data frame len=%u rate=%u xfer len=%u\n", 798 6629 zf162725 pktlen, rate, xferlen); 799 6629 zf162725 800 6629 zf162725 (void) ural_tx_trigger(sc, m); 801 6629 zf162725 802 6629 zf162725 ic->ic_stats.is_tx_frags++; 803 6629 zf162725 ic->ic_stats.is_tx_bytes += pktlen; 804 6629 zf162725 805 6629 zf162725 fail: 806 6629 zf162725 if (ni != NULL) 807 6629 zf162725 ieee80211_free_node(ni); 808 6629 zf162725 809 6629 zf162725 if ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA || 810 6629 zf162725 err == 0) { 811 6629 zf162725 freemsg(mp); 812 6629 zf162725 } 813 6629 zf162725 814 6629 zf162725 mutex_exit(&sc->tx_lock); 815 6629 zf162725 816 6629 zf162725 return (err); 817 6629 zf162725 } 818 6629 zf162725 819 6629 zf162725 static mblk_t * 820 6629 zf162725 ural_m_tx(void *arg, mblk_t *mp) 821 6629 zf162725 { 822 6629 zf162725 struct ural_softc *sc = (struct ural_softc *)arg; 823 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 824 6629 zf162725 mblk_t *next; 825 6629 zf162725 826 6629 zf162725 /* 827 6629 zf162725 * No data frames go out unless we're associated; this 828 6629 zf162725 * should not happen as the 802.11 layer does not enable 829 6629 zf162725 * the xmit queue until we enter the RUN state. 830 6629 zf162725 */ 831 6629 zf162725 if (ic->ic_state != IEEE80211_S_RUN) { 832 9345 Quaker ral_debug(RAL_DBG_ERR, "ural_m_tx(): " 833 6629 zf162725 "discard, state %u\n", ic->ic_state); 834 6629 zf162725 freemsgchain(mp); 835 6629 zf162725 return (NULL); 836 6629 zf162725 } 837 6629 zf162725 838 6629 zf162725 while (mp != NULL) { 839 6629 zf162725 next = mp->b_next; 840 6629 zf162725 mp->b_next = NULL; 841 6629 zf162725 if (ural_send(ic, mp, IEEE80211_FC0_TYPE_DATA) != DDI_SUCCESS) { 842 6629 zf162725 mp->b_next = next; 843 6629 zf162725 freemsgchain(mp); 844 6629 zf162725 return (NULL); 845 6629 zf162725 } 846 6629 zf162725 mp = next; 847 6629 zf162725 } 848 6629 zf162725 return (mp); 849 6629 zf162725 } 850 6629 zf162725 851 6629 zf162725 static void 852 6629 zf162725 ural_set_testmode(struct ural_softc *sc) 853 6629 zf162725 { 854 6629 zf162725 usb_ctrl_setup_t req; 855 6629 zf162725 usb_cr_t cr; 856 6629 zf162725 usb_cb_flags_t cf; 857 6629 zf162725 int err; 858 6629 zf162725 859 6629 zf162725 bzero(&req, sizeof (req)); 860 6629 zf162725 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_HOST_TO_DEV; 861 6629 zf162725 req.bRequest = RAL_VENDOR_REQUEST; 862 6629 zf162725 req.wValue = 4; 863 6629 zf162725 req.wIndex = 1; 864 6629 zf162725 req.wLength = 0; 865 6629 zf162725 req.attrs = USB_ATTRS_NONE; 866 6629 zf162725 867 6629 zf162725 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, NULL, 868 6629 zf162725 &cr, &cf, 0); 869 6629 zf162725 870 6629 zf162725 if (err != USB_SUCCESS) { 871 9345 Quaker ral_debug(RAL_DBG_USB, 872 6629 zf162725 "ural_set_testmode(): could not set test mode:" 873 6629 zf162725 "cr:%s(%d), cf:%(x)\n", 874 6629 zf162725 usb_str_cr(cr), cr, cf); 875 6629 zf162725 } 876 6629 zf162725 } 877 6629 zf162725 878 6629 zf162725 static void 879 6629 zf162725 ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 880 6629 zf162725 { 881 6629 zf162725 usb_ctrl_setup_t req; 882 6629 zf162725 usb_cr_t cr; 883 6629 zf162725 usb_cb_flags_t cf; 884 6629 zf162725 mblk_t *mp; 885 6629 zf162725 int err; 886 6629 zf162725 887 6629 zf162725 bzero(&req, sizeof (req)); 888 6629 zf162725 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_DEV_TO_HOST; 889 6629 zf162725 req.bRequest = RAL_READ_EEPROM; 890 6629 zf162725 req.wValue = 0; 891 6629 zf162725 req.wIndex = addr; 892 6629 zf162725 req.wLength = (uint16_t)len; 893 6629 zf162725 894 6629 zf162725 mp = NULL; 895 6629 zf162725 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp, 896 6629 zf162725 &cr, &cf, 0); 897 6629 zf162725 898 6629 zf162725 if (err != USB_SUCCESS) { 899 9345 Quaker ral_debug(RAL_DBG_USB, 900 6629 zf162725 "ural_eeprom_read(): could not read EEPROM:" 901 6629 zf162725 "cr:%s(%d), cf:(%x)\n", 902 6629 zf162725 usb_str_cr(cr), cr, cf); 903 6629 zf162725 return; 904 6629 zf162725 } 905 6629 zf162725 906 6629 zf162725 bcopy(mp->b_rptr, buf, len); 907 6629 zf162725 908 6629 zf162725 if (mp) 909 6629 zf162725 freemsg(mp); 910 6629 zf162725 } 911 6629 zf162725 912 6629 zf162725 static void 913 6629 zf162725 ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 914 6629 zf162725 { 915 6629 zf162725 uint16_t tmp; 916 6629 zf162725 int ntries; 917 6629 zf162725 918 6629 zf162725 for (ntries = 0; ntries < 5; ntries++) { 919 6629 zf162725 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 920 6629 zf162725 break; 921 6629 zf162725 } 922 6629 zf162725 if (ntries == 5) { 923 9345 Quaker ral_debug(RAL_DBG_ERR, 924 6629 zf162725 "ural_bbp_write(): could not write to BBP\n"); 925 6629 zf162725 return; 926 6629 zf162725 } 927 6629 zf162725 928 6629 zf162725 tmp = reg << 8 | val; 929 6629 zf162725 ural_write(sc, RAL_PHY_CSR7, tmp); 930 6629 zf162725 } 931 6629 zf162725 932 6629 zf162725 static uint8_t 933 6629 zf162725 ural_bbp_read(struct ural_softc *sc, uint8_t reg) 934 6629 zf162725 { 935 6629 zf162725 uint16_t val; 936 6629 zf162725 int ntries; 937 6629 zf162725 938 6629 zf162725 val = RAL_BBP_WRITE | reg << 8; 939 6629 zf162725 ural_write(sc, RAL_PHY_CSR7, val); 940 6629 zf162725 941 6629 zf162725 for (ntries = 0; ntries < 5; ntries++) { 942 6629 zf162725 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 943 6629 zf162725 break; 944 6629 zf162725 } 945 6629 zf162725 if (ntries == 5) { 946 9345 Quaker ral_debug(RAL_DBG_ERR, "ural_bbp_read(): could not read BBP\n"); 947 6629 zf162725 return (0); 948 6629 zf162725 } 949 6629 zf162725 950 6629 zf162725 return (ural_read(sc, RAL_PHY_CSR7) & 0xff); 951 6629 zf162725 } 952 6629 zf162725 953 6629 zf162725 static void 954 6629 zf162725 ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 955 6629 zf162725 { 956 6629 zf162725 uint32_t tmp; 957 6629 zf162725 int ntries; 958 6629 zf162725 959 6629 zf162725 for (ntries = 0; ntries < 5; ntries++) { 960 6629 zf162725 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 961 6629 zf162725 break; 962 6629 zf162725 } 963 6629 zf162725 if (ntries == 5) { 964 9345 Quaker ral_debug(RAL_DBG_ERR, 965 6629 zf162725 "ural_rf_write(): could not write to RF\n"); 966 6629 zf162725 return; 967 6629 zf162725 } 968 6629 zf162725 969 6629 zf162725 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xffff) << 2 | (reg & 0x3); 970 6629 zf162725 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 971 6629 zf162725 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 972 6629 zf162725 973 6629 zf162725 /* remember last written value in sc */ 974 6629 zf162725 sc->rf_regs[reg] = val; 975 6629 zf162725 976 9345 Quaker ral_debug(RAL_DBG_HW, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 977 6629 zf162725 } 978 6629 zf162725 979 6629 zf162725 /* 980 6629 zf162725 * Disable RF auto-tuning. 981 6629 zf162725 */ 982 6629 zf162725 static void 983 6629 zf162725 ural_disable_rf_tune(struct ural_softc *sc) 984 6629 zf162725 { 985 6629 zf162725 uint32_t tmp; 986 6629 zf162725 987 6629 zf162725 if (sc->rf_rev != RAL_RF_2523) { 988 6629 zf162725 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 989 6629 zf162725 ural_rf_write(sc, RAL_RF1, tmp); 990 6629 zf162725 } 991 6629 zf162725 992 6629 zf162725 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 993 6629 zf162725 ural_rf_write(sc, RAL_RF3, tmp); 994 6629 zf162725 995 9345 Quaker ral_debug(RAL_DBG_HW, "disabling RF autotune\n"); 996 6629 zf162725 } 997 6629 zf162725 998 6629 zf162725 999 6629 zf162725 static void 1000 6629 zf162725 ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1001 6629 zf162725 { 1002 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 1003 6629 zf162725 uint8_t power, tmp; 1004 6629 zf162725 uint_t i, chan; 1005 6629 zf162725 1006 6629 zf162725 chan = ieee80211_chan2ieee(ic, c); 1007 6629 zf162725 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1008 6629 zf162725 return; 1009 6629 zf162725 1010 6629 zf162725 if (IEEE80211_IS_CHAN_2GHZ(c)) 1011 6629 zf162725 power = min(sc->txpow[chan - 1], 31); 1012 6629 zf162725 else 1013 6629 zf162725 power = 31; 1014 6629 zf162725 1015 6629 zf162725 /* adjust txpower using ifconfig settings */ 1016 6629 zf162725 power -= (100 - ic->ic_txpowlimit) / 8; 1017 6629 zf162725 1018 9345 Quaker ral_debug(RAL_DBG_HW, "setting channel to %u, txpower to %u\n", 1019 6629 zf162725 chan, power); 1020 6629 zf162725 1021 6629 zf162725 switch (sc->rf_rev) { 1022 6629 zf162725 case RAL_RF_2522: 1023 6629 zf162725 ural_rf_write(sc, RAL_RF1, 0x00814); 1024 6629 zf162725 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1025 6629 zf162725 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1026 6629 zf162725 break; 1027 6629 zf162725 1028 6629 zf162725 case RAL_RF_2523: 1029 6629 zf162725 ural_rf_write(sc, RAL_RF1, 0x08804); 1030 6629 zf162725 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1031 6629 zf162725 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1032 6629 zf162725 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1033 6629 zf162725 break; 1034 6629 zf162725 1035 6629 zf162725 case RAL_RF_2524: 1036 6629 zf162725 ural_rf_write(sc, RAL_RF1, 0x0c808); 1037 6629 zf162725 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1038 6629 zf162725 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1039 6629 zf162725 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1040 6629 zf162725 break; 1041 6629 zf162725 1042 6629 zf162725 case RAL_RF_2525: 1043 6629 zf162725 ural_rf_write(sc, RAL_RF1, 0x08808); 1044 6629 zf162725 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1045 6629 zf162725 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1046 6629 zf162725 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1047 6629 zf162725 1048 6629 zf162725 ural_rf_write(sc, RAL_RF1, 0x08808); 1049 6629 zf162725 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1050 6629 zf162725 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1051 6629 zf162725 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1052 6629 zf162725 break; 1053 6629 zf162725 1054 6629 zf162725 case RAL_RF_2525E: 1055 6629 zf162725 ural_rf_write(sc, RAL_RF1, 0x08808); 1056 6629 zf162725 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1057 6629 zf162725 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1058 6629 zf162725 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1059 6629 zf162725 break; 1060 6629 zf162725 1061 6629 zf162725 case RAL_RF_2526: 1062 6629 zf162725 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1063 6629 zf162725 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1064 6629 zf162725 ural_rf_write(sc, RAL_RF1, 0x08804); 1065 6629 zf162725 1066 6629 zf162725 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1067 6629 zf162725 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1068 6629 zf162725 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1069 6629 zf162725 break; 1070 6629 zf162725 1071 6629 zf162725 /* dual-band RF */ 1072 6629 zf162725 case RAL_RF_5222: 1073 6629 zf162725 for (i = 0; ural_rf5222[i].chan != chan; i++) { 1074 6629 zf162725 if (i > URAL_N(ural_rf5222)) break; 1075 6629 zf162725 } 1076 6629 zf162725 1077 6629 zf162725 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1078 6629 zf162725 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1079 6629 zf162725 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1080 6629 zf162725 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1081 6629 zf162725 break; 1082 6629 zf162725 } 1083 6629 zf162725 1084 6629 zf162725 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1085 6629 zf162725 ic->ic_state != IEEE80211_S_SCAN) { 1086 6629 zf162725 /* set Japan filter bit for channel 14 */ 1087 6629 zf162725 tmp = ural_bbp_read(sc, 70); 1088 6629 zf162725 1089 6629 zf162725 tmp &= ~RAL_JAPAN_FILTER; 1090 6629 zf162725 if (chan == 14) 1091 6629 zf162725 tmp |= RAL_JAPAN_FILTER; 1092 6629 zf162725 1093 6629 zf162725 ural_bbp_write(sc, 70, tmp); 1094 6629 zf162725 1095 6629 zf162725 /* clear CRC errs */ 1096 6629 zf162725 (void) ural_read(sc, RAL_STA_CSR0); 1097 6629 zf162725 1098 6629 zf162725 drv_usecwait(10000); 1099 6629 zf162725 ural_disable_rf_tune(sc); 1100 6629 zf162725 } 1101 6629 zf162725 } 1102 6629 zf162725 1103 6629 zf162725 /* 1104 6629 zf162725 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1105 6629 zf162725 * synchronization. 1106 6629 zf162725 */ 1107 6629 zf162725 static void 1108 6629 zf162725 ural_enable_tsf_sync(struct ural_softc *sc) 1109 6629 zf162725 { 1110 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 1111 6629 zf162725 uint16_t logcwmin, preload, tmp; 1112 6629 zf162725 1113 6629 zf162725 /* first, disable TSF synchronization */ 1114 6629 zf162725 ural_write(sc, RAL_TXRX_CSR19, 0); 1115 6629 zf162725 1116 6629 zf162725 tmp = (16 * ic->ic_bss->in_intval) << 4; 1117 6629 zf162725 ural_write(sc, RAL_TXRX_CSR18, tmp); 1118 6629 zf162725 1119 6629 zf162725 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1120 6629 zf162725 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1121 6629 zf162725 tmp = logcwmin << 12 | preload; 1122 6629 zf162725 ural_write(sc, RAL_TXRX_CSR20, tmp); 1123 6629 zf162725 1124 6629 zf162725 /* finally, enable TSF synchronization */ 1125 6629 zf162725 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1126 6629 zf162725 if (ic->ic_opmode == IEEE80211_M_STA) 1127 6629 zf162725 tmp |= RAL_ENABLE_TSF_SYNC(1); 1128 6629 zf162725 else 1129 6629 zf162725 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1130 6629 zf162725 ural_write(sc, RAL_TXRX_CSR19, tmp); 1131 6629 zf162725 1132 9345 Quaker ral_debug(RAL_DBG_HW, "enabling TSF synchronization\n"); 1133 6629 zf162725 } 1134 6629 zf162725 1135 6629 zf162725 /* 1136 6629 zf162725 * This function can be called by ieee80211_set_shortslottime(). Refer to 1137 6629 zf162725 * IEEE Std 802.11-1999 pp. 85 to know how these values are computed. 1138 6629 zf162725 */ 1139 6629 zf162725 /* ARGSUSED */ 1140 6629 zf162725 static void 1141 6629 zf162725 ural_update_slot(struct ieee80211com *ic, int onoff) 1142 6629 zf162725 { 1143 6629 zf162725 struct ural_softc *sc = (struct ural_softc *)ic; 1144 6629 zf162725 uint16_t slottime, sifs, eifs; 1145 6629 zf162725 1146 6629 zf162725 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1147 6629 zf162725 /* slottime = (onoff ? 9 : 20); */ 1148 6629 zf162725 1149 6629 zf162725 /* 1150 6629 zf162725 * These settings may sound a bit inconsistent but this is what the 1151 6629 zf162725 * reference driver does. 1152 6629 zf162725 */ 1153 6629 zf162725 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1154 6629 zf162725 sifs = 16 - RAL_RXTX_TURNAROUND; 1155 6629 zf162725 eifs = 364; 1156 6629 zf162725 } else { 1157 6629 zf162725 sifs = 10 - RAL_RXTX_TURNAROUND; 1158 6629 zf162725 eifs = 64; 1159 6629 zf162725 } 1160 6629 zf162725 1161 6629 zf162725 ural_write(sc, RAL_MAC_CSR10, slottime); 1162 6629 zf162725 ural_write(sc, RAL_MAC_CSR11, sifs); 1163 6629 zf162725 ural_write(sc, RAL_MAC_CSR12, eifs); 1164 6629 zf162725 } 1165 6629 zf162725 1166 6629 zf162725 static void 1167 6629 zf162725 ural_set_txpreamble(struct ural_softc *sc) 1168 6629 zf162725 { 1169 6629 zf162725 uint16_t tmp; 1170 6629 zf162725 1171 6629 zf162725 tmp = ural_read(sc, RAL_TXRX_CSR10); 1172 6629 zf162725 1173 6629 zf162725 tmp &= ~RAL_SHORT_PREAMBLE; 1174 6629 zf162725 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 1175 6629 zf162725 tmp |= RAL_SHORT_PREAMBLE; 1176 6629 zf162725 1177 6629 zf162725 ural_write(sc, RAL_TXRX_CSR10, tmp); 1178 6629 zf162725 } 1179 6629 zf162725 1180 6629 zf162725 static void 1181 6629 zf162725 ural_set_basicrates(struct ural_softc *sc) 1182 6629 zf162725 { 1183 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 1184 6629 zf162725 1185 6629 zf162725 /* update basic rate set */ 1186 6629 zf162725 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1187 6629 zf162725 /* 11b basic rates: 1, 2Mbps */ 1188 6629 zf162725 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1189 6629 zf162725 } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->in_chan)) { 1190 6629 zf162725 /* 11a basic rates: 6, 12, 24Mbps */ 1191 6629 zf162725 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1192 6629 zf162725 } else { 1193 6629 zf162725 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1194 6629 zf162725 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1195 6629 zf162725 } 1196 6629 zf162725 } 1197 6629 zf162725 1198 6629 zf162725 static void 1199 6629 zf162725 ural_set_bssid(struct ural_softc *sc, uint8_t *bssid) 1200 6629 zf162725 { 1201 6629 zf162725 uint16_t tmp; 1202 6629 zf162725 1203 6629 zf162725 tmp = bssid[0] | bssid[1] << 8; 1204 6629 zf162725 ural_write(sc, RAL_MAC_CSR5, tmp); 1205 6629 zf162725 1206 6629 zf162725 tmp = bssid[2] | bssid[3] << 8; 1207 6629 zf162725 ural_write(sc, RAL_MAC_CSR6, tmp); 1208 6629 zf162725 1209 6629 zf162725 tmp = bssid[4] | bssid[5] << 8; 1210 6629 zf162725 ural_write(sc, RAL_MAC_CSR7, tmp); 1211 6629 zf162725 1212 9345 Quaker ral_debug(RAL_DBG_HW, "setting BSSID to " MACSTR "\n", MAC2STR(bssid)); 1213 6629 zf162725 } 1214 6629 zf162725 1215 6629 zf162725 static void 1216 6629 zf162725 ural_set_macaddr(struct ural_softc *sc, uint8_t *addr) 1217 6629 zf162725 { 1218 6629 zf162725 uint16_t tmp; 1219 6629 zf162725 1220 6629 zf162725 tmp = addr[0] | addr[1] << 8; 1221 6629 zf162725 ural_write(sc, RAL_MAC_CSR2, tmp); 1222 6629 zf162725 1223 6629 zf162725 tmp = addr[2] | addr[3] << 8; 1224 6629 zf162725 ural_write(sc, RAL_MAC_CSR3, tmp); 1225 6629 zf162725 1226 6629 zf162725 tmp = addr[4] | addr[5] << 8; 1227 6629 zf162725 ural_write(sc, RAL_MAC_CSR4, tmp); 1228 6629 zf162725 1229 9345 Quaker ral_debug(RAL_DBG_HW, 1230 6629 zf162725 "setting MAC address to " MACSTR "\n", MAC2STR(addr)); 1231 6629 zf162725 } 1232 6629 zf162725 1233 6629 zf162725 static void 1234 6629 zf162725 ural_update_promisc(struct ural_softc *sc) 1235 6629 zf162725 { 1236 6629 zf162725 uint32_t tmp; 1237 6629 zf162725 1238 6629 zf162725 tmp = ural_read(sc, RAL_TXRX_CSR2); 1239 6629 zf162725 1240 6629 zf162725 tmp &= ~RAL_DROP_NOT_TO_ME; 1241 6629 zf162725 if (!(sc->sc_rcr & RAL_RCR_PROMISC)) 1242 6629 zf162725 tmp |= RAL_DROP_NOT_TO_ME; 1243 6629 zf162725 1244 6629 zf162725 ural_write(sc, RAL_TXRX_CSR2, tmp); 1245 6629 zf162725 1246 9345 Quaker ral_debug(RAL_DBG_HW, "%s promiscuous mode\n", 1247 6629 zf162725 (sc->sc_rcr & RAL_RCR_PROMISC) ? "entering" : "leaving"); 1248 6629 zf162725 } 1249 6629 zf162725 1250 6629 zf162725 static const char * 1251 6629 zf162725 ural_get_rf(int rev) 1252 6629 zf162725 { 1253 6629 zf162725 switch (rev) { 1254 6629 zf162725 case RAL_RF_2522: return ("RT2522"); 1255 6629 zf162725 case RAL_RF_2523: return ("RT2523"); 1256 6629 zf162725 case RAL_RF_2524: return ("RT2524"); 1257 6629 zf162725 case RAL_RF_2525: return ("RT2525"); 1258 6629 zf162725 case RAL_RF_2525E: return ("RT2525e"); 1259 6629 zf162725 case RAL_RF_2526: return ("RT2526"); 1260 6629 zf162725 case RAL_RF_5222: return ("RT5222"); 1261 6629 zf162725 default: return ("unknown"); 1262 6629 zf162725 } 1263 6629 zf162725 } 1264 6629 zf162725 1265 6629 zf162725 static void 1266 6629 zf162725 ural_read_eeprom(struct ural_softc *sc) 1267 6629 zf162725 { 1268 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 1269 6629 zf162725 uint16_t val; 1270 6629 zf162725 1271 6629 zf162725 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 1272 6629 zf162725 val = LE_16(val); 1273 6629 zf162725 sc->rf_rev = (val >> 11) & 0x7; 1274 6629 zf162725 sc->hw_radio = (val >> 10) & 0x1; 1275 6629 zf162725 sc->led_mode = (val >> 6) & 0x7; 1276 6629 zf162725 sc->rx_ant = (val >> 4) & 0x3; 1277 6629 zf162725 sc->tx_ant = (val >> 2) & 0x3; 1278 6629 zf162725 sc->nb_ant = val & 0x3; 1279 6629 zf162725 1280 6629 zf162725 /* read MAC address */ 1281 6629 zf162725 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, ic->ic_macaddr, 6); 1282 6629 zf162725 1283 6629 zf162725 /* read default values for BBP registers */ 1284 6629 zf162725 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 1285 6629 zf162725 1286 6629 zf162725 /* read Tx power for all b/g channels */ 1287 6629 zf162725 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 1288 6629 zf162725 } 1289 6629 zf162725 1290 6629 zf162725 static int 1291 6629 zf162725 ural_bbp_init(struct ural_softc *sc) 1292 6629 zf162725 { 1293 6629 zf162725 int i, ntries; 1294 6629 zf162725 1295 6629 zf162725 /* wait for BBP to be ready */ 1296 6629 zf162725 for (ntries = 0; ntries < 100; ntries++) { 1297 6629 zf162725 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 1298 6629 zf162725 break; 1299 6629 zf162725 drv_usecwait(1000); 1300 6629 zf162725 } 1301 6629 zf162725 if (ntries == 100) { 1302 9345 Quaker ral_debug(RAL_DBG_ERR, "timeout waiting for BBP\n"); 1303 6629 zf162725 return (EIO); 1304 6629 zf162725 } 1305 6629 zf162725 1306 6629 zf162725 /* initialize BBP registers to default values */ 1307 6629 zf162725 for (i = 0; i < URAL_N(ural_def_bbp); i++) 1308 6629 zf162725 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 1309 6629 zf162725 1310 6629 zf162725 return (0); 1311 6629 zf162725 } 1312 6629 zf162725 1313 6629 zf162725 static void 1314 6629 zf162725 ural_set_txantenna(struct ural_softc *sc, int antenna) 1315 6629 zf162725 { 1316 6629 zf162725 uint16_t tmp; 1317 6629 zf162725 uint8_t tx; 1318 6629 zf162725 1319 6629 zf162725 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 1320 6629 zf162725 if (antenna == 1) 1321 6629 zf162725 tx |= RAL_BBP_ANTA; 1322 6629 zf162725 else if (antenna == 2) 1323 6629 zf162725 tx |= RAL_BBP_ANTB; 1324 6629 zf162725 else 1325 6629 zf162725 tx |= RAL_BBP_DIVERSITY; 1326 6629 zf162725 1327 6629 zf162725 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 1328 6629 zf162725 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 1329 6629 zf162725 sc->rf_rev == RAL_RF_5222) 1330 6629 zf162725 tx |= RAL_BBP_FLIPIQ; 1331 6629 zf162725 1332 6629 zf162725 ural_bbp_write(sc, RAL_BBP_TX, tx); 1333 6629 zf162725 1334 6629 zf162725 /* update values in PHY_CSR5 and PHY_CSR6 */ 1335 6629 zf162725 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 1336 6629 zf162725 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 1337 6629 zf162725 1338 6629 zf162725 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 1339 6629 zf162725 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 1340 6629 zf162725 } 1341 6629 zf162725 1342 6629 zf162725 static void 1343 6629 zf162725 ural_set_rxantenna(struct ural_softc *sc, int antenna) 1344 6629 zf162725 { 1345 6629 zf162725 uint8_t rx; 1346 6629 zf162725 1347 6629 zf162725 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 1348 6629 zf162725 if (antenna == 1) 1349 6629 zf162725 rx |= RAL_BBP_ANTA; 1350 6629 zf162725 else if (antenna == 2) 1351 6629 zf162725 rx |= RAL_BBP_ANTB; 1352 6629 zf162725 else 1353 6629 zf162725 rx |= RAL_BBP_DIVERSITY; 1354 6629 zf162725 1355 6629 zf162725 /* need to force no I/Q flip for RF 2525e and 2526 */ 1356 6629 zf162725 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 1357 6629 zf162725 rx &= ~RAL_BBP_FLIPIQ; 1358 6629 zf162725 1359 6629 zf162725 ural_bbp_write(sc, RAL_BBP_RX, rx); 1360 6629 zf162725 } 1361 6629 zf162725 1362 6629 zf162725 /* 1363 6629 zf162725 * This function is called periodically (every 200ms) during scanning to 1364 6629 zf162725 * switch from one channel to another. 1365 6629 zf162725 */ 1366 6629 zf162725 static void 1367 6629 zf162725 ural_next_scan(void *arg) 1368 6629 zf162725 { 1369 6629 zf162725 struct ural_softc *sc = arg; 1370 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 1371 6629 zf162725 1372 6629 zf162725 if (ic->ic_state == IEEE80211_S_SCAN) 1373 6629 zf162725 ieee80211_next_scan(ic); 1374 6629 zf162725 } 1375 6629 zf162725 1376 6629 zf162725 static int 1377 6629 zf162725 ural_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1378 6629 zf162725 { 1379 6629 zf162725 struct ural_softc *sc = (struct ural_softc *)ic; 1380 6629 zf162725 enum ieee80211_state ostate; 1381 6629 zf162725 struct ieee80211_node *ni; 1382 6629 zf162725 int err; 1383 6629 zf162725 1384 6629 zf162725 RAL_LOCK(sc); 1385 6629 zf162725 1386 6629 zf162725 ostate = ic->ic_state; 1387 6629 zf162725 1388 6629 zf162725 if (sc->sc_scan_id != 0) { 1389 6629 zf162725 (void) untimeout(sc->sc_scan_id); 1390 6629 zf162725 sc->sc_scan_id = 0; 1391 6629 zf162725 } 1392 6629 zf162725 1393 6629 zf162725 if (sc->sc_amrr_id != 0) { 1394 6629 zf162725 (void) untimeout(sc->sc_amrr_id); 1395 6629 zf162725 sc->sc_amrr_id = 0; 1396 6629 zf162725 } 1397 6629 zf162725 1398 6629 zf162725 switch (nstate) { 1399 6629 zf162725 case IEEE80211_S_INIT: 1400 6629 zf162725 if (ostate == IEEE80211_S_RUN) { 1401 6629 zf162725 /* abort TSF synchronization */ 1402 6629 zf162725 ural_write(sc, RAL_TXRX_CSR19, 0); 1403 6629 zf162725 /* force tx led to stop blinking */ 1404 6629 zf162725 ural_write(sc, RAL_MAC_CSR20, 0); 1405 6629 zf162725 } 1406 6629 zf162725 break; 1407 6629 zf162725 1408 6629 zf162725 case IEEE80211_S_SCAN: 1409 6629 zf162725 ural_set_chan(sc, ic->ic_curchan); 1410 6629 zf162725 sc->sc_scan_id = timeout(ural_next_scan, (void *)sc, 1411 6629 zf162725 drv_usectohz(sc->dwelltime * 1000)); 1412 6629 zf162725 break; 1413 6629 zf162725 1414 6629 zf162725 case IEEE80211_S_AUTH: 1415 6629 zf162725 ural_set_chan(sc, ic->ic_curchan); 1416 6629 zf162725 break; 1417 6629 zf162725 1418 6629 zf162725 case IEEE80211_S_ASSOC: 1419 6629 zf162725 ural_set_chan(sc, ic->ic_curchan); 1420 6629 zf162725 break; 1421 6629 zf162725 1422 6629 zf162725 case IEEE80211_S_RUN: 1423 6629 zf162725 ural_set_chan(sc, ic->ic_curchan); 1424 6629 zf162725 1425 6629 zf162725 ni = ic->ic_bss; 1426 6629 zf162725 1427 6629 zf162725 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1428 6629 zf162725 ural_update_slot(ic, 1); 1429 6629 zf162725 ural_set_txpreamble(sc); 1430 6629 zf162725 ural_set_basicrates(sc); 1431 6629 zf162725 ural_set_bssid(sc, ni->in_bssid); 1432 6629 zf162725 } 1433 6629 zf162725 1434 6629 zf162725 1435 6629 zf162725 /* make tx led blink on tx (controlled by ASIC) */ 1436 6629 zf162725 ural_write(sc, RAL_MAC_CSR20, 1); 1437 6629 zf162725 1438 6629 zf162725 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1439 6629 zf162725 ural_enable_tsf_sync(sc); 1440 6629 zf162725 1441 6629 zf162725 /* enable automatic rate adaptation in STA mode */ 1442 6629 zf162725 if (ic->ic_opmode == IEEE80211_M_STA && 1443 6629 zf162725 ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) 1444 6629 zf162725 ural_amrr_start(sc, ni); 1445 6629 zf162725 1446 6629 zf162725 break; 1447 6629 zf162725 } 1448 6629 zf162725 1449 6629 zf162725 RAL_UNLOCK(sc); 1450 6629 zf162725 1451 6629 zf162725 err = sc->sc_newstate(ic, nstate, arg); 1452 6629 zf162725 /* 1453 6629 zf162725 * Finally, start any timers. 1454 6629 zf162725 */ 1455 6629 zf162725 if (nstate == IEEE80211_S_RUN) 1456 6629 zf162725 ieee80211_start_watchdog(ic, 1); 1457 6629 zf162725 1458 6629 zf162725 return (err); 1459 6629 zf162725 } 1460 6629 zf162725 1461 6629 zf162725 1462 6629 zf162725 1463 6629 zf162725 static void 1464 6629 zf162725 ural_close_pipes(struct ural_softc *sc) 1465 6629 zf162725 { 1466 6629 zf162725 usb_flags_t flags = USB_FLAGS_SLEEP; 1467 6629 zf162725 1468 6629 zf162725 if (sc->sc_rx_pipeh != NULL) { 1469 6629 zf162725 usb_pipe_reset(sc->sc_dev, sc->sc_rx_pipeh, flags, NULL, 0); 1470 6629 zf162725 usb_pipe_close(sc->sc_dev, sc->sc_rx_pipeh, flags, NULL, 0); 1471 6629 zf162725 sc->sc_rx_pipeh = NULL; 1472 6629 zf162725 } 1473 6629 zf162725 1474 6629 zf162725 if (sc->sc_tx_pipeh != NULL) { 1475 6629 zf162725 usb_pipe_reset(sc->sc_dev, sc->sc_tx_pipeh, flags, NULL, 0); 1476 6629 zf162725 usb_pipe_close(sc->sc_dev, sc->sc_tx_pipeh, flags, NULL, 0); 1477 6629 zf162725 sc->sc_tx_pipeh = NULL; 1478 6629 zf162725 } 1479 6629 zf162725 } 1480 6629 zf162725 1481 6629 zf162725 static int 1482 6629 zf162725 ural_open_pipes(struct ural_softc *sc) 1483 6629 zf162725 { 1484 6629 zf162725 usb_ep_data_t *ep_node; 1485 6629 zf162725 usb_pipe_policy_t policy; 1486 6629 zf162725 int err; 1487 6629 zf162725 1488 6629 zf162725 ep_node = usb_lookup_ep_data(sc->sc_dev, sc->sc_udev, 0, 0, 0, 1489 6629 zf162725 USB_EP_ATTR_BULK, USB_EP_DIR_OUT); 1490 6629 zf162725 1491 6629 zf162725 bzero(&policy, sizeof (usb_pipe_policy_t)); 1492 6629 zf162725 policy.pp_max_async_reqs = RAL_TX_LIST_COUNT; 1493 6629 zf162725 1494 6629 zf162725 if ((err = usb_pipe_open(sc->sc_dev, 1495 6629 zf162725 &ep_node->ep_descr, &policy, USB_FLAGS_SLEEP, 1496 6629 zf162725 &sc->sc_tx_pipeh)) != USB_SUCCESS) { 1497 9345 Quaker ral_debug(RAL_DBG_ERR, 1498 6629 zf162725 "ural_open_pipes(): %x failed to open tx pipe\n", err); 1499 6629 zf162725 goto fail; 1500 6629 zf162725 } 1501 6629 zf162725 1502 6629 zf162725 ep_node = usb_lookup_ep_data(sc->sc_dev, sc->sc_udev, 0, 0, 0, 1503 6629 zf162725 USB_EP_ATTR_BULK, USB_EP_DIR_IN); 1504 6629 zf162725 1505 6629 zf162725 bzero(&policy, sizeof (usb_pipe_policy_t)); 1506 6629 zf162725 policy.pp_max_async_reqs = RAL_RX_LIST_COUNT + 32; 1507 6629 zf162725 1508 6629 zf162725 if ((err = usb_pipe_open(sc->sc_dev, 1509 6629 zf162725 &ep_node->ep_descr, &policy, USB_FLAGS_SLEEP, 1510 6629 zf162725 &sc->sc_rx_pipeh)) != USB_SUCCESS) { 1511 9345 Quaker ral_debug(RAL_DBG_ERR, 1512 6629 zf162725 "ural_open_pipes(): %x failed to open rx pipe\n", err); 1513 6629 zf162725 goto fail; 1514 6629 zf162725 } 1515 6629 zf162725 1516 6629 zf162725 return (USB_SUCCESS); 1517 6629 zf162725 1518 6629 zf162725 fail: 1519 6629 zf162725 if (sc->sc_rx_pipeh != NULL) { 1520 6629 zf162725 usb_pipe_close(sc->sc_dev, sc->sc_rx_pipeh, 1521 6629 zf162725 USB_FLAGS_SLEEP, NULL, 0); 1522 6629 zf162725 sc->sc_rx_pipeh = NULL; 1523 6629 zf162725 } 1524 6629 zf162725 1525 6629 zf162725 if (sc->sc_tx_pipeh != NULL) { 1526 6629 zf162725 usb_pipe_close(sc->sc_dev, sc->sc_tx_pipeh, 1527 6629 zf162725 USB_FLAGS_SLEEP, NULL, 0); 1528 6629 zf162725 sc->sc_tx_pipeh = NULL; 1529 6629 zf162725 } 1530 6629 zf162725 1531 6629 zf162725 return (USB_FAILURE); 1532 6629 zf162725 } 1533 6629 zf162725 1534 6629 zf162725 static int 1535 6629 zf162725 ural_tx_trigger(struct ural_softc *sc, mblk_t *mp) 1536 6629 zf162725 { 1537 6629 zf162725 usb_bulk_req_t *req; 1538 6629 zf162725 int err; 1539 6629 zf162725 1540 6629 zf162725 sc->sc_tx_timer = RAL_TX_TIMEOUT; 1541 6629 zf162725 1542 6629 zf162725 req = usb_alloc_bulk_req(sc->sc_dev, 0, USB_FLAGS_SLEEP); 1543 6629 zf162725 if (req == NULL) { 1544 9345 Quaker ral_debug(RAL_DBG_ERR, 1545 6629 zf162725 "ural_tx_trigger(): failed to allocate req"); 1546 6629 zf162725 freemsg(mp); 1547 6629 zf162725 return (-1); 1548 6629 zf162725 } 1549 6629 zf162725 1550 6629 zf162725 req->bulk_len = (uintptr_t)mp->b_wptr - (uintptr_t)mp->b_rptr; 1551 6629 zf162725 req->bulk_data = mp; 1552 6629 zf162725 req->bulk_client_private = (usb_opaque_t)sc; 1553 6629 zf162725 req->bulk_timeout = RAL_TX_TIMEOUT; 1554 6629 zf162725 req->bulk_attributes = USB_ATTRS_AUTOCLEARING; 1555 6629 zf162725 req->bulk_cb = ural_txeof; 1556 6629 zf162725 req->bulk_exc_cb = ural_txeof; 1557 6629 zf162725 req->bulk_completion_reason = 0; 1558 6629 zf162725 req->bulk_cb_flags = 0; 1559 6629 zf162725 1560 6629 zf162725 if ((err = usb_pipe_bulk_xfer(sc->sc_tx_pipeh, req, 0)) 1561 6629 zf162725 != USB_SUCCESS) { 1562 6629 zf162725 1563 9345 Quaker ral_debug(RAL_DBG_ERR, "ural_tx_trigger(): " 1564 6629 zf162725 "failed to do tx xfer, %d", err); 1565 6629 zf162725 usb_free_bulk_req(req); 1566 6629 zf162725 return (-1); 1567 6629 zf162725 } 1568 6629 zf162725 1569 6629 zf162725 sc->tx_queued++; 1570 6629 zf162725 1571 6629 zf162725 return (0); 1572 6629 zf162725 } 1573 6629 zf162725 1574 6629 zf162725 static int 1575 6629 zf162725 ural_rx_trigger(struct ural_softc *sc) 1576 6629 zf162725 { 1577 6629 zf162725 usb_bulk_req_t *req; 1578 6629 zf162725 int err; 1579 6629 zf162725 1580 6629 zf162725 req = usb_alloc_bulk_req(sc->sc_dev, RAL_RXBUF_SIZE, USB_FLAGS_SLEEP); 1581 6629 zf162725 if (req == NULL) { 1582 9345 Quaker ral_debug(RAL_DBG_ERR, 1583 6629 zf162725 "ural_rx_trigger(): failed to allocate req"); 1584 6629 zf162725 return (-1); 1585 6629 zf162725 } 1586 6629 zf162725 1587 6629 zf162725 req->bulk_len = RAL_RXBUF_SIZE; 1588 6629 zf162725 req->bulk_client_private = (usb_opaque_t)sc; 1589 6629 zf162725 req->bulk_timeout = 0; 1590 6629 zf162725 req->bulk_attributes = USB_ATTRS_SHORT_XFER_OK 1591 6629 zf162725 | USB_ATTRS_AUTOCLEARING; 1592 6629 zf162725 req->bulk_cb = ural_rxeof; 1593 6629 zf162725 req->bulk_exc_cb = ural_rxeof; 1594 6629 zf162725 req->bulk_completion_reason = 0; 1595 6629 zf162725 req->bulk_cb_flags = 0; 1596 6629 zf162725 1597 6629 zf162725 err = usb_pipe_bulk_xfer(sc->sc_rx_pipeh, req, 0); 1598 6629 zf162725 1599 6629 zf162725 if (err != USB_SUCCESS) { 1600 9345 Quaker ral_debug(RAL_DBG_ERR, "ural_rx_trigger(): " 1601 6629 zf162725 "failed to do rx xfer, %d", err); 1602 6629 zf162725 usb_free_bulk_req(req); 1603 6629 zf162725 1604 6629 zf162725 return (-1); 1605 6629 zf162725 } 1606 6629 zf162725 1607 6629 zf162725 mutex_enter(&sc->rx_lock); 1608 6629 zf162725 sc->rx_queued++; 1609 6629 zf162725 mutex_exit(&sc->rx_lock); 1610 6629 zf162725 1611 6629 zf162725 return (0); 1612 6629 zf162725 } 1613 6629 zf162725 1614 6629 zf162725 static void 1615 6629 zf162725 ural_init_tx_queue(struct ural_softc *sc) 1616 6629 zf162725 { 1617 6629 zf162725 sc->tx_queued = 0; 1618 6629 zf162725 } 1619 6629 zf162725 1620 6629 zf162725 static int 1621 6629 zf162725 ural_init_rx_queue(struct ural_softc *sc) 1622 6629 zf162725 { 1623 6629 zf162725 int i; 1624 6629 zf162725 1625 6629 zf162725 sc->rx_queued = 0; 1626 6629 zf162725 1627 6629 zf162725 for (i = 0; i < RAL_RX_LIST_COUNT; i++) { 1628 6629 zf162725 if (ural_rx_trigger(sc) != 0) { 1629 6629 zf162725 return (USB_FAILURE); 1630 6629 zf162725 } 1631 6629 zf162725 } 1632 6629 zf162725 1633 6629 zf162725 return (USB_SUCCESS); 1634 6629 zf162725 } 1635 6629 zf162725 1636 6629 zf162725 static void 1637 6629 zf162725 ural_stop(struct ural_softc *sc) 1638 6629 zf162725 { 1639 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 1640 6629 zf162725 1641 6629 zf162725 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1642 6629 zf162725 ieee80211_stop_watchdog(ic); /* stop the watchdog */ 1643 6629 zf162725 1644 6629 zf162725 RAL_LOCK(sc); 1645 6629 zf162725 1646 6629 zf162725 sc->sc_tx_timer = 0; 1647 6629 zf162725 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */ 1648 6629 zf162725 1649 6629 zf162725 /* disable Rx */ 1650 6629 zf162725 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 1651 6629 zf162725 1652 6629 zf162725 /* reset ASIC and BBP (but won't reset MAC registers!) */ 1653 6629 zf162725 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 1654 6629 zf162725 ural_write(sc, RAL_MAC_CSR1, 0); 1655 6629 zf162725 1656 6629 zf162725 ural_close_pipes(sc); 1657 6629 zf162725 1658 6629 zf162725 RAL_UNLOCK(sc); 1659 6629 zf162725 } 1660 6629 zf162725 1661 6629 zf162725 static int 1662 6629 zf162725 ural_init(struct ural_softc *sc) 1663 6629 zf162725 { 1664 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 1665 6629 zf162725 uint16_t tmp; 1666 6629 zf162725 int i, ntries; 1667 6629 zf162725 1668 6629 zf162725 ural_set_testmode(sc); 1669 6629 zf162725 ural_write(sc, 0x308, 0x00f0); /* magic */ 1670 6629 zf162725 1671 6629 zf162725 ural_stop(sc); 1672 6629 zf162725 1673 6629 zf162725 /* initialize MAC registers to default values */ 1674 6629 zf162725 for (i = 0; i < URAL_N(ural_def_mac); i++) 1675 6629 zf162725 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 1676 6629 zf162725 1677 6629 zf162725 /* wait for BBP and RF to wake up (this can take a long time!) */ 1678 6629 zf162725 for (ntries = 0; ntries < 100; ntries++) { 1679 6629 zf162725 tmp = ural_read(sc, RAL_MAC_CSR17); 1680 6629 zf162725 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 1681 6629 zf162725 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 1682 6629 zf162725 break; 1683 6629 zf162725 drv_usecwait(1000); 1684 6629 zf162725 } 1685 6629 zf162725 if (ntries == 100) { 1686 9345 Quaker ral_debug(RAL_DBG_ERR, 1687 6629 zf162725 "ural_init(): timeout waiting for BBP/RF to wakeup\n"); 1688 6629 zf162725 goto fail; 1689 6629 zf162725 } 1690 6629 zf162725 1691 6629 zf162725 /* we're ready! */ 1692 6629 zf162725 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 1693 6629 zf162725 1694 6629 zf162725 /* set basic rate set (will be updated later) */ 1695 6629 zf162725 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1696 6629 zf162725 1697 6629 zf162725 if (ural_bbp_init(sc) != 0) 1698 6629 zf162725 goto fail; 1699 6629 zf162725 1700 6629 zf162725 /* set default BSS channel */ 1701 6629 zf162725 ural_set_chan(sc, ic->ic_curchan); 1702 6629 zf162725 1703 6629 zf162725 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 1704 6629 zf162725 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof (sc->sta)); 1705 6629 zf162725 1706 6629 zf162725 ural_set_txantenna(sc, sc->tx_ant); 1707 6629 zf162725 ural_set_rxantenna(sc, sc->rx_ant); 1708 6629 zf162725 1709 6629 zf162725 ural_set_macaddr(sc, ic->ic_macaddr); 1710 6629 zf162725 1711 6629 zf162725 if (ural_open_pipes(sc) != USB_SUCCESS) { 1712 9345 Quaker ral_debug(RAL_DBG_ERR, "ural_init(): " 1713 6629 zf162725 "could not open pipes.\n"); 1714 6629 zf162725 goto fail; 1715 6629 zf162725 } 1716 6629 zf162725 1717 6629 zf162725 ural_init_tx_queue(sc); 1718 6629 zf162725 1719 6629 zf162725 if (ural_init_rx_queue(sc) != USB_SUCCESS) 1720 6629 zf162725 goto fail; 1721 6629 zf162725 1722 6629 zf162725 /* kick Rx */ 1723 6629 zf162725 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 1724 6629 zf162725 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1725 6629 zf162725 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 1726 6629 zf162725 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 1727 6629 zf162725 tmp |= RAL_DROP_TODS; 1728 6629 zf162725 if (!(sc->sc_rcr & RAL_RCR_PROMISC)) 1729 6629 zf162725 tmp |= RAL_DROP_NOT_TO_ME; 1730 6629 zf162725 } 1731 6629 zf162725 ural_write(sc, RAL_TXRX_CSR2, tmp); 1732 6629 zf162725 sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */ 1733 6629 zf162725 1734 6629 zf162725 return (DDI_SUCCESS); 1735 6629 zf162725 fail: 1736 6629 zf162725 ural_stop(sc); 1737 6629 zf162725 return (EIO); 1738 6629 zf162725 } 1739 6629 zf162725 1740 6629 zf162725 static int 1741 9345 Quaker ural_disconnect(dev_info_t *devinfo) 1742 6629 zf162725 { 1743 6629 zf162725 struct ural_softc *sc; 1744 6629 zf162725 struct ieee80211com *ic; 1745 6629 zf162725 1746 6629 zf162725 /* 1747 6629 zf162725 * We can't call ural_stop() here, since the hardware is removed, 1748 6629 zf162725 * we can't access the register anymore. 1749 6629 zf162725 */ 1750 9345 Quaker sc = ddi_get_soft_state(ural_soft_state_p, ddi_get_instance(devinfo)); 1751 9345 Quaker ASSERT(sc != NULL); 1752 6629 zf162725 1753 9345 Quaker if (!RAL_IS_RUNNING(sc)) /* different device or not inited */ 1754 9345 Quaker return (DDI_SUCCESS); 1755 9345 Quaker 1756 6629 zf162725 ic = &sc->sc_ic; 1757 6629 zf162725 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1758 6629 zf162725 ieee80211_stop_watchdog(ic); /* stop the watchdog */ 1759 6629 zf162725 1760 6629 zf162725 RAL_LOCK(sc); 1761 6629 zf162725 1762 6629 zf162725 sc->sc_tx_timer = 0; 1763 6629 zf162725 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */ 1764 6629 zf162725 1765 6629 zf162725 ural_close_pipes(sc); 1766 6629 zf162725 1767 6629 zf162725 RAL_UNLOCK(sc); 1768 6629 zf162725 1769 6629 zf162725 return (DDI_SUCCESS); 1770 6629 zf162725 } 1771 6629 zf162725 1772 6629 zf162725 static int 1773 9345 Quaker ural_reconnect(dev_info_t *devinfo) 1774 6629 zf162725 { 1775 6629 zf162725 struct ural_softc *sc; 1776 6629 zf162725 int err; 1777 6629 zf162725 1778 9345 Quaker sc = ddi_get_soft_state(ural_soft_state_p, ddi_get_instance(devinfo)); 1779 9345 Quaker ASSERT(sc != NULL); 1780 6629 zf162725 1781 9345 Quaker /* check device changes after disconnect */ 1782 9345 Quaker if (usb_check_same_device(sc->sc_dev, NULL, USB_LOG_L2, -1, 1783 9345 Quaker USB_CHK_BASIC | USB_CHK_CFG, NULL) != USB_SUCCESS) { 1784 9345 Quaker ral_debug(RAL_DBG_ERR, "different device connected\n"); 1785 9345 Quaker return (DDI_FAILURE); 1786 9345 Quaker } 1787 9345 Quaker 1788 6629 zf162725 err = ural_init(sc); 1789 6629 zf162725 1790 6629 zf162725 return (err); 1791 9345 Quaker } 1792 9345 Quaker 1793 9345 Quaker static void 1794 9345 Quaker ural_resume(struct ural_softc *sc) 1795 9345 Quaker { 1796 9345 Quaker /* check device changes after suspend */ 1797 9345 Quaker if (usb_check_same_device(sc->sc_dev, NULL, USB_LOG_L2, -1, 1798 9345 Quaker USB_CHK_BASIC | USB_CHK_CFG, NULL) != USB_SUCCESS) { 1799 9345 Quaker ral_debug(RAL_DBG_ERR, "no or different device connected\n"); 1800 9345 Quaker return; 1801 9345 Quaker } 1802 9345 Quaker 1803 9345 Quaker (void) ural_init(sc); 1804 6629 zf162725 } 1805 6629 zf162725 1806 6629 zf162725 #define URAL_AMRR_MIN_SUCCESS_THRESHOLD 1 1807 6629 zf162725 #define URAL_AMRR_MAX_SUCCESS_THRESHOLD 10 1808 6629 zf162725 1809 6629 zf162725 /* 1810 6629 zf162725 * Naive implementation of the Adaptive Multi Rate Retry algorithm: 1811 6629 zf162725 * "IEEE 802.11 Rate Adaptation: A Practical Approach" 1812 6629 zf162725 * Mathieu Lacage, Hossein Manshaei, Thierry Turletti 1813 6629 zf162725 * INRIA Sophia - Projet Planete 1814 6629 zf162725 * http://www-sop.inria.fr/rapports/sophia/RR-5208.html 1815 6629 zf162725 * 1816 6629 zf162725 * This algorithm is particularly well suited for ural since it does not 1817 6629 zf162725 * require per-frame retry statistics. Note however that since h/w does 1818 6629 zf162725 * not provide per-frame stats, we can't do per-node rate adaptation and 1819 6629 zf162725 * thus automatic rate adaptation is only enabled in STA operating mode. 1820 6629 zf162725 */ 1821 6629 zf162725 #define is_success(amrr) \ 1822 6629 zf162725 ((amrr)->retrycnt < (amrr)->txcnt / 10) 1823 6629 zf162725 #define is_failure(amrr) \ 1824 6629 zf162725 ((amrr)->retrycnt > (amrr)->txcnt / 3) 1825 6629 zf162725 #define is_enough(amrr) \ 1826 6629 zf162725 ((amrr)->txcnt > 10) 1827 6629 zf162725 #define is_min_rate(ni) \ 1828 6629 zf162725 ((ni)->in_txrate == 0) 1829 6629 zf162725 #define is_max_rate(ni) \ 1830 6629 zf162725 ((ni)->in_txrate == (ni)->in_rates.ir_nrates - 1) 1831 6629 zf162725 #define increase_rate(ni) \ 1832 6629 zf162725 ((ni)->in_txrate++) 1833 6629 zf162725 #define decrease_rate(ni) \ 1834 6629 zf162725 ((ni)->in_txrate--) 1835 6629 zf162725 #define reset_cnt(amrr) do { \ 1836 6629 zf162725 (amrr)->txcnt = (amrr)->retrycnt = 0; \ 1837 6629 zf162725 _NOTE(CONSTCOND) \ 1838 6629 zf162725 } while (/* CONSTCOND */0) 1839 6629 zf162725 1840 6629 zf162725 static void 1841 6629 zf162725 ural_ratectl(struct ural_amrr *amrr, struct ieee80211_node *ni) 1842 6629 zf162725 { 1843 6629 zf162725 int need_change = 0; 1844 6629 zf162725 1845 6629 zf162725 if (is_success(amrr) && is_enough(amrr)) { 1846 6629 zf162725 amrr->success++; 1847 6629 zf162725 if (amrr->success >= amrr->success_threshold && 1848 6629 zf162725 !is_max_rate(ni)) { 1849 6629 zf162725 amrr->recovery = 1; 1850 6629 zf162725 amrr->success = 0; 1851 6629 zf162725 increase_rate(ni); 1852 6629 zf162725 need_change = 1; 1853 6629 zf162725 } else { 1854 6629 zf162725 amrr->recovery = 0; 1855 6629 zf162725 } 1856 6629 zf162725 } else if (is_failure(amrr)) { 1857 6629 zf162725 amrr->success = 0; 1858 6629 zf162725 if (!is_min_rate(ni)) { 1859 6629 zf162725 if (amrr->recovery) { 1860 6629 zf162725 amrr->success_threshold *= 2; 1861 6629 zf162725 if (amrr->success_threshold > 1862 6629 zf162725 URAL_AMRR_MAX_SUCCESS_THRESHOLD) 1863 6629 zf162725 amrr->success_threshold = 1864 6629 zf162725 URAL_AMRR_MAX_SUCCESS_THRESHOLD; 1865 6629 zf162725 } else { 1866 6629 zf162725 amrr->success_threshold = 1867 6629 zf162725 URAL_AMRR_MIN_SUCCESS_THRESHOLD; 1868 6629 zf162725 } 1869 6629 zf162725 decrease_rate(ni); 1870 6629 zf162725 need_change = 1; 1871 6629 zf162725 } 1872 6629 zf162725 amrr->recovery = 0; /* original paper was incorrect */ 1873 6629 zf162725 } 1874 6629 zf162725 1875 6629 zf162725 if (is_enough(amrr) || need_change) 1876 6629 zf162725 reset_cnt(amrr); 1877 6629 zf162725 } 1878 6629 zf162725 1879 6629 zf162725 static void 1880 6629 zf162725 ural_amrr_timeout(void *arg) 1881 6629 zf162725 { 1882 6629 zf162725 struct ural_softc *sc = (struct ural_softc *)arg; 1883 6629 zf162725 struct ural_amrr *amrr = &sc->amrr; 1884 6629 zf162725 1885 6629 zf162725 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof (sc->sta)); 1886 6629 zf162725 1887 6629 zf162725 /* count TX retry-fail as Tx errors */ 1888 6629 zf162725 sc->sc_tx_err += sc->sta[9]; 1889 6629 zf162725 sc->sc_tx_retries += (sc->sta[7] + sc->sta[8]); 1890 6629 zf162725 1891 6629 zf162725 amrr->retrycnt = 1892 6629 zf162725 sc->sta[7] + /* TX one-retry ok count */ 1893 6629 zf162725 sc->sta[8] + /* TX more-retry ok count */ 1894 6629 zf162725 sc->sta[9]; /* TX retry-fail count */ 1895 6629 zf162725 1896 6629 zf162725 amrr->txcnt = 1897 6629 zf162725 amrr->retrycnt + 1898 6629 zf162725 sc->sta[6]; /* TX no-retry ok count */ 1899 6629 zf162725 1900 6629 zf162725 ural_ratectl(amrr, sc->sc_ic.ic_bss); 1901 6629 zf162725 1902 6629 zf162725 sc->sc_amrr_id = timeout(ural_amrr_timeout, (void *)sc, 1903 6629 zf162725 drv_usectohz(1000 * 1000)); /* 1 second */ 1904 6629 zf162725 } 1905 6629 zf162725 1906 6629 zf162725 1907 6629 zf162725 static void 1908 6629 zf162725 ural_amrr_start(struct ural_softc *sc, struct ieee80211_node *ni) 1909 6629 zf162725 { 1910 6629 zf162725 struct ural_amrr *amrr = &sc->amrr; 1911 6629 zf162725 int i; 1912 6629 zf162725 1913 6629 zf162725 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 1914 6629 zf162725 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof (sc->sta)); 1915 6629 zf162725 1916 6629 zf162725 amrr->success = 0; 1917 6629 zf162725 amrr->recovery = 0; 1918 6629 zf162725 amrr->txcnt = amrr->retrycnt = 0; 1919 6629 zf162725 amrr->success_threshold = URAL_AMRR_MIN_SUCCESS_THRESHOLD; 1920 6629 zf162725 1921 6629 zf162725 /* set rate to some reasonable initial value */ 1922 6629 zf162725 for (i = ni->in_rates.ir_nrates - 1; 1923 6629 zf162725 i > 0 && (ni->in_rates.ir_rates[i] & IEEE80211_RATE_VAL) > 72; 1924 6629 zf162725 i--) { 1925 6629 zf162725 } 1926 6629 zf162725 1927 6629 zf162725 ni->in_txrate = i; 1928 6629 zf162725 1929 6629 zf162725 sc->sc_amrr_id = timeout(ural_amrr_timeout, (void *)sc, 1930 6629 zf162725 drv_usectohz(1000 * 1000)); /* 1 second */ 1931 6629 zf162725 } 1932 6629 zf162725 1933 6629 zf162725 void 1934 6629 zf162725 ural_watchdog(void *arg) 1935 6629 zf162725 { 1936 6629 zf162725 struct ural_softc *sc = arg; 1937 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 1938 6629 zf162725 int ntimer = 0; 1939 6629 zf162725 1940 6629 zf162725 RAL_LOCK(sc); 1941 6629 zf162725 ic->ic_watchdog_timer = 0; 1942 6629 zf162725 1943 6629 zf162725 if (!RAL_IS_RUNNING(sc)) { 1944 6629 zf162725 RAL_UNLOCK(sc); 1945 6629 zf162725 return; 1946 6629 zf162725 } 1947 6629 zf162725 1948 6629 zf162725 if (sc->sc_tx_timer > 0) { 1949 6629 zf162725 if (--sc->sc_tx_timer == 0) { 1950 9345 Quaker ral_debug(RAL_DBG_ERR, "tx timer timeout\n"); 1951 6629 zf162725 RAL_UNLOCK(sc); 1952 6629 zf162725 (void) ural_init(sc); 1953 6629 zf162725 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1954 6629 zf162725 return; 1955 6629 zf162725 } 1956 6629 zf162725 } 1957 6629 zf162725 1958 6629 zf162725 if (ic->ic_state == IEEE80211_S_RUN) 1959 6629 zf162725 ntimer = 1; 1960 6629 zf162725 1961 6629 zf162725 RAL_UNLOCK(sc); 1962 6629 zf162725 1963 6629 zf162725 ieee80211_watchdog(ic); 1964 6629 zf162725 1965 6629 zf162725 if (ntimer) 1966 6629 zf162725 ieee80211_start_watchdog(ic, ntimer); 1967 6629 zf162725 } 1968 6629 zf162725 1969 6629 zf162725 static int 1970 6629 zf162725 ural_m_start(void *arg) 1971 6629 zf162725 { 1972 6629 zf162725 struct ural_softc *sc = (struct ural_softc *)arg; 1973 6629 zf162725 int err; 1974 6629 zf162725 1975 6629 zf162725 /* 1976 6629 zf162725 * initialize RT2500USB hardware 1977 6629 zf162725 */ 1978 6629 zf162725 err = ural_init(sc); 1979 6629 zf162725 if (err != DDI_SUCCESS) { 1980 9345 Quaker ral_debug(RAL_DBG_ERR, "device configuration failed\n"); 1981 6629 zf162725 goto fail; 1982 6629 zf162725 } 1983 6629 zf162725 sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */ 1984 6629 zf162725 return (err); 1985 6629 zf162725 1986 6629 zf162725 fail: 1987 6629 zf162725 ural_stop(sc); 1988 6629 zf162725 return (err); 1989 6629 zf162725 } 1990 6629 zf162725 1991 6629 zf162725 static void 1992 6629 zf162725 ural_m_stop(void *arg) 1993 6629 zf162725 { 1994 6629 zf162725 struct ural_softc *sc = (struct ural_softc *)arg; 1995 6629 zf162725 1996 6629 zf162725 (void) ural_stop(sc); 1997 6629 zf162725 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */ 1998 6629 zf162725 } 1999 6629 zf162725 2000 6629 zf162725 static int 2001 6629 zf162725 ural_m_unicst(void *arg, const uint8_t *macaddr) 2002 6629 zf162725 { 2003 6629 zf162725 struct ural_softc *sc = (struct ural_softc *)arg; 2004 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 2005 6629 zf162725 2006 9345 Quaker ral_debug(RAL_DBG_MSG, "ural_m_unicst(): " MACSTR "\n", 2007 6629 zf162725 MAC2STR(macaddr)); 2008 6629 zf162725 2009 6629 zf162725 IEEE80211_ADDR_COPY(ic->ic_macaddr, macaddr); 2010 6629 zf162725 (void) ural_set_macaddr(sc, (uint8_t *)macaddr); 2011 6629 zf162725 (void) ural_init(sc); 2012 6629 zf162725 2013 6629 zf162725 return (0); 2014 6629 zf162725 } 2015 6629 zf162725 2016 6629 zf162725 /*ARGSUSED*/ 2017 6629 zf162725 static int 2018 6629 zf162725 ural_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 2019 6629 zf162725 { 2020 6629 zf162725 return (0); 2021 6629 zf162725 } 2022 6629 zf162725 2023 6629 zf162725 static int 2024 6629 zf162725 ural_m_promisc(void *arg, boolean_t on) 2025 6629 zf162725 { 2026 6629 zf162725 struct ural_softc *sc = (struct ural_softc *)arg; 2027 6629 zf162725 2028 6629 zf162725 if (on) { 2029 6629 zf162725 sc->sc_rcr |= RAL_RCR_PROMISC; 2030 6629 zf162725 sc->sc_rcr |= RAL_RCR_MULTI; 2031 6629 zf162725 } else { 2032 6629 zf162725 sc->sc_rcr &= ~RAL_RCR_PROMISC; 2033 6629 zf162725 sc->sc_rcr &= ~RAL_RCR_PROMISC; 2034 6629 zf162725 } 2035 6629 zf162725 2036 6629 zf162725 ural_update_promisc(sc); 2037 6629 zf162725 return (0); 2038 6629 zf162725 } 2039 6629 zf162725 2040 8099 Quaker /* 2041 8099 Quaker * callback functions for /get/set properties 2042 8099 Quaker */ 2043 8099 Quaker static int 2044 8099 Quaker ural_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num, 2045 8099 Quaker uint_t wldp_length, const void *wldp_buf) 2046 8099 Quaker { 2047 8099 Quaker struct ural_softc *sc = (struct ural_softc *)arg; 2048 8099 Quaker struct ieee80211com *ic = &sc->sc_ic; 2049 8099 Quaker int err; 2050 8099 Quaker 2051 8099 Quaker err = ieee80211_setprop(ic, pr_name, wldp_pr_num, 2052 8099 Quaker wldp_length, wldp_buf); 2053 8099 Quaker RAL_LOCK(sc); 2054 8099 Quaker if (err == ENETRESET) { 2055 8099 Quaker if (RAL_IS_RUNNING(sc)) { 2056 8099 Quaker RAL_UNLOCK(sc); 2057 8099 Quaker (void) ural_init(sc); 2058 8099 Quaker (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2059 8099 Quaker RAL_LOCK(sc); 2060 8099 Quaker } 2061 8099 Quaker err = 0; 2062 8099 Quaker } 2063 8099 Quaker RAL_UNLOCK(sc); 2064 8099 Quaker 2065 8099 Quaker return (err); 2066 8099 Quaker } 2067 8099 Quaker 2068 8099 Quaker static int 2069 8099 Quaker ural_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num, 2070 8118 Vasumathi uint_t pr_flags, uint_t wldp_length, void *wldp_buf, uint_t *perm) 2071 8099 Quaker { 2072 8099 Quaker struct ural_softc *sc = (struct ural_softc *)arg; 2073 8099 Quaker int err; 2074 8099 Quaker 2075 8099 Quaker err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num, 2076 8118 Vasumathi pr_flags, wldp_length, wldp_buf, perm); 2077 8099 Quaker 2078 8099 Quaker return (err); 2079 8099 Quaker } 2080 8099 Quaker 2081 6629 zf162725 static void 2082 6629 zf162725 ural_m_ioctl(void* arg, queue_t *wq, mblk_t *mp) 2083 6629 zf162725 { 2084 6629 zf162725 struct ural_softc *sc = (struct ural_softc *)arg; 2085 6629 zf162725 struct ieee80211com *ic = &sc->sc_ic; 2086 6629 zf162725 int err; 2087 6629 zf162725 2088 6629 zf162725 err = ieee80211_ioctl(ic, wq, mp); 2089 6629 zf162725 RAL_LOCK(sc); 2090 6629 zf162725 if (err == ENETRESET) { 2091 6629 zf162725 if (RAL_IS_RUNNING(sc)) { 2092 6629 zf162725 RAL_UNLOCK(sc); 2093 6629 zf162725 (void) ural_init(sc); 2094 6629 zf162725 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2095 6629 zf162725 RAL_LOCK(sc); 2096 6629 zf162725 } 2097 6629 zf162725 } 2098 6629 zf162725 RAL_UNLOCK(sc); 2099 6629 zf162725 } 2100 6629 zf162725 2101 6629 zf162725 static int 2102 6629 zf162725 ural_m_stat(void *arg, uint_t stat, uint64_t *val) 2103 6629 zf162725 { 2104 6629 zf162725 struct ural_softc *sc = (struct ural_softc *)arg; 2105 6629 zf162725 ieee80211com_t *ic = &sc->sc_ic; 2106 6629 zf162725 ieee80211_node_t *ni = ic->ic_bss; 2107 6629 zf162725 struct ieee80211_rateset *rs = &ni->in_rates; 2108 6629 zf162725 2109 6629 zf162725 RAL_LOCK(sc); 2110 6629 zf162725 switch (stat) { 2111 6629 zf162725 case MAC_STAT_IFSPEED: 2112 6629 zf162725 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ? 2113 6629 zf162725 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL) 2114 6890 ql147931 : ic->ic_fixed_rate) / 2 * 1000000; 2115 6629 zf162725 break; 2116 6629 zf162725 case MAC_STAT_NOXMTBUF: 2117 6629 zf162725 *val = sc->sc_tx_nobuf; 2118 6629 zf162725 break; 2119 6629 zf162725 case MAC_STAT_NORCVBUF: 2120 6629 zf162725 *val = sc->sc_rx_nobuf; 2121 6629 zf162725 break; 2122 6629 zf162725 case MAC_STAT_IERRORS: 2123 6629 zf162725 *val = sc->sc_rx_err; 2124 6629 zf162725 break; 2125 6629 zf162725 case MAC_STAT_RBYTES: 2126 6629 zf162725 *val = ic->ic_stats.is_rx_bytes; 2127 6629 zf162725 break; 2128 6629 zf162725 case MAC_STAT_IPACKETS: 2129 6629 zf162725 *val = ic->ic_stats.is_rx_frags; 2130 6629 zf162725 break; 2131 6629 zf162725 case MAC_STAT_OBYTES: 2132 6629 zf162725 *val = ic->ic_stats.is_tx_bytes; 2133 6629 zf162725 break; 2134 6629 zf162725 case MAC_STAT_OPACKETS: 2135 6629 zf162725 *val = ic->ic_stats.is_tx_frags; 2136 6629 zf162725 break; 2137 6629 zf162725 case MAC_STAT_OERRORS: 2138 6629 zf162725 case WIFI_STAT_TX_FAILED: 2139 6629 zf162725 *val = sc->sc_tx_err; 2140 6629 zf162725 break; 2141 6629 zf162725 case WIFI_STAT_TX_RETRANS: 2142 6629 zf162725 *val = sc->sc_tx_retries; 2143 6629 zf162725 break; 2144 6629 zf162725 case WIFI_STAT_FCS_ERRORS: 2145 6629 zf162725 case WIFI_STAT_WEP_ERRORS: 2146 6629 zf162725 case WIFI_STAT_TX_FRAGS: 2147 6629 zf162725 case WIFI_STAT_MCAST_TX: 2148 6629 zf162725 case WIFI_STAT_RTS_SUCCESS: 2149 6629 zf162725 case WIFI_STAT_RTS_FAILURE: 2150 6629 zf162725 case WIFI_STAT_ACK_FAILURE: 2151 6629 zf162725 case WIFI_STAT_RX_FRAGS: 2152 6629 zf162725 case WIFI_STAT_MCAST_RX: 2153 6629 zf162725 case WIFI_STAT_RX_DUPS: 2154 6629 zf162725 RAL_UNLOCK(sc); 2155 6629 zf162725 return (ieee80211_stat(ic, stat, val)); 2156 6629 zf162725 default: 2157 6629 zf162725 RAL_UNLOCK(sc); 2158 6629 zf162725 return (ENOTSUP); 2159 6629 zf162725 } 2160 6629 zf162725 RAL_UNLOCK(sc); 2161 6629 zf162725 2162 6629 zf162725 return (0); 2163 6629 zf162725 } 2164 6629 zf162725 2165 6629 zf162725 2166 6629 zf162725 static int 2167 6629 zf162725 ural_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 2168 6629 zf162725 { 2169 6629 zf162725 struct ural_softc *sc; 2170 6629 zf162725 struct ieee80211com *ic; 2171 6629 zf162725 int err, i; 2172 6629 zf162725 int instance; 2173 6629 zf162725 2174 6629 zf162725 char strbuf[32]; 2175 6629 zf162725 2176 6629 zf162725 wifi_data_t wd = { 0 }; 2177 6629 zf162725 mac_register_t *macp; 2178 6629 zf162725 2179 9345 Quaker switch (cmd) { 2180 9345 Quaker case DDI_ATTACH: 2181 9345 Quaker break; 2182 9345 Quaker case DDI_RESUME: 2183 9345 Quaker sc = ddi_get_soft_state(ural_soft_state_p, 2184 9345 Quaker ddi_get_instance(devinfo)); 2185 9345 Quaker ASSERT(sc != NULL); 2186 9345 Quaker ural_resume(sc); 2187 9345 Quaker return (DDI_SUCCESS); 2188 9345 Quaker default: 2189 6629 zf162725 return (DDI_FAILURE); 2190 9345 Quaker } 2191 6629 zf162725 2192 6629 zf162725 instance = ddi_get_instance(devinfo); 2193 6629 zf162725 2194 6629 zf162725 if (ddi_soft_state_zalloc(ural_soft_state_p, instance) != DDI_SUCCESS) { 2195 9345 Quaker ral_debug(RAL_DBG_MSG, "ural_attach(): " 2196 6629 zf162725 "unable to alloc soft_state_p\n"); 2197 6629 zf162725 return (DDI_FAILURE); 2198 6629 zf162725 } 2199 6629 zf162725 2200 6629 zf162725 sc = ddi_get_soft_state(ural_soft_state_p, instance); 2201 6629 zf162725 ic = (ieee80211com_t *)&sc->sc_ic; 2202 6629 zf162725 sc->sc_dev = devinfo; 2203 6629 zf162725 2204 6629 zf162725 if (usb_client_attach(devinfo, USBDRV_VERSION, 0) != USB_SUCCESS) { 2205 9345 Quaker ral_debug(RAL_DBG_ERR, 2206 6629 zf162725 "ural_attach(): usb_client_attach failed\n"); 2207 6629 zf162725 goto fail1; 2208 6629 zf162725 } 2209 6629 zf162725 2210 6629 zf162725 if (usb_get_dev_data(devinfo, &sc->sc_udev, 2211 6629 zf162725 USB_PARSE_LVL_ALL, 0) != USB_SUCCESS) { 2212 6629 zf162725 sc->sc_udev = NULL; 2213 6629 zf162725 goto fail2; 2214 6629 zf162725 } 2215 6629 zf162725 2216 6629 zf162725 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL); 2217 6629 zf162725 mutex_init(&sc->tx_lock, NULL, MUTEX_DRIVER, NULL); 2218 6629 zf162725 mutex_init(&sc->rx_lock, NULL, MUTEX_DRIVER, NULL); 2219 6629 zf162725 2220 6629 zf162725 /* retrieve RT2570 rev. no */ 2221 6629 zf162725 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 2222 6629 zf162725 2223 6629 zf162725 /* retrieve MAC address and various other things from EEPROM */ 2224 6629 zf162725 ural_read_eeprom(sc); 2225 6629 zf162725 2226 9345 Quaker ral_debug(RAL_DBG_MSG, "ural: MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 2227 6629 zf162725 sc->asic_rev, ural_get_rf(sc->rf_rev)); 2228 6629 zf162725 2229 6629 zf162725 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 2230 6629 zf162725 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 2231 6629 zf162725 ic->ic_state = IEEE80211_S_INIT; 2232 6629 zf162725 2233 6629 zf162725 ic->ic_maxrssi = 63; 2234 6629 zf162725 ic->ic_set_shortslot = ural_update_slot; 2235 6629 zf162725 ic->ic_xmit = ural_send; 2236 6629 zf162725 2237 6629 zf162725 /* set device capabilities */ 2238 6629 zf162725 ic->ic_caps = 2239 6629 zf162725 IEEE80211_C_TXPMGT | /* tx power management */ 2240 6629 zf162725 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 2241 6629 zf162725 IEEE80211_C_SHSLOT; /* short slot time supported */ 2242 6629 zf162725 2243 6629 zf162725 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */ 2244 6629 zf162725 2245 6629 zf162725 #define IEEE80211_CHAN_A \ 2246 6629 zf162725 (IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM) 2247 6629 zf162725 2248 6629 zf162725 if (sc->rf_rev == RAL_RF_5222) { 2249 6629 zf162725 /* set supported .11a rates */ 2250 6629 zf162725 ic->ic_sup_rates[IEEE80211_MODE_11A] = ural_rateset_11a; 2251 6629 zf162725 2252 6629 zf162725 /* set supported .11a channels */ 2253 6629 zf162725 for (i = 36; i <= 64; i += 4) { 2254 6629 zf162725 ic->ic_sup_channels[i].ich_freq = 2255 6629 zf162725 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 2256 6629 zf162725 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A; 2257 6629 zf162725 } 2258 6629 zf162725 for (i = 100; i <= 140; i += 4) { 2259 6629 zf162725 ic->ic_sup_channels[i].ich_freq = 2260 6629 zf162725 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 2261 6629 zf162725 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A; 2262 6629 zf162725 } 2263 6629 zf162725 for (i = 149; i <= 161; i += 4) { 2264 6629 zf162725 ic->ic_sup_channels[i].ich_freq = 2265 6629 zf162725 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 2266 6629 zf162725 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A; 2267 6629 zf162725 } 2268 6629 zf162725 } 2269 6629 zf162725 2270 6629 zf162725 /* set supported .11b and .11g rates */ 2271 6629 zf162725 ic->ic_sup_rates[IEEE80211_MODE_11B] = ural_rateset_11b; 2272 6629 zf162725 ic->ic_sup_rates[IEEE80211_MODE_11G] = ural_rateset_11g; 2273 6629 zf162725 2274 6629 zf162725 /* set supported .11b and .11g channels (1 through 14) */ 2275 6629 zf162725 for (i = 1; i <= 14; i++) { 2276 6629 zf162725 ic->ic_sup_channels[i].ich_freq = 2277 6629 zf162725 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 2278 6629 zf162725 ic->ic_sup_channels[i].ich_flags = 2279 6629 zf162725 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 2280 6629 zf162725 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 2281 6629 zf162725 } 2282 6629 zf162725 2283 6629 zf162725 ieee80211_attach(ic); 2284 6629 zf162725 2285 6629 zf162725 /* register WPA door */ 2286 6629 zf162725 ieee80211_register_door(ic, ddi_driver_name(devinfo), 2287 6629 zf162725 ddi_get_instance(devinfo)); 2288 6629 zf162725 2289 6629 zf162725 /* override state transition machine */ 2290 6629 zf162725 sc->sc_newstate = ic->ic_newstate; 2291 6629 zf162725 ic->ic_newstate = ural_newstate; 2292 6629 zf162725 ic->ic_watchdog = ural_watchdog; 2293 6629 zf162725 ieee80211_media_init(ic); 2294 6629 zf162725 ic->ic_def_txkey = 0; 2295 6629 zf162725 2296 6629 zf162725 sc->sc_rcr = 0; 2297 6629 zf162725 sc->dwelltime = 300; 2298 9345 Quaker sc->sc_flags &= 0; 2299 6629 zf162725 2300 6629 zf162725 /* 2301 6629 zf162725 * Provide initial settings for the WiFi plugin; whenever this 2302 6629 zf162725 * information changes, we need to call mac_plugindata_update() 2303 6629 zf162725 */ 2304 6629 zf162725 wd.wd_opmode = ic->ic_opmode; 2305 6629 zf162725 wd.wd_secalloc = WIFI_SEC_NONE; 2306 6629 zf162725 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid); 2307 6629 zf162725 2308 6629 zf162725 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 2309 9345 Quaker ral_debug(RAL_DBG_ERR, "ural_attach(): " 2310 6629 zf162725 "MAC version mismatch\n"); 2311 6629 zf162725 goto fail3; 2312 6629 zf162725 } 2313 6629 zf162725 2314 6629 zf162725 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI; 2315 6629 zf162725 macp->m_driver = sc; 2316 6629 zf162725 macp->m_dip = devinfo; 2317 6629 zf162725 macp->m_src_addr = ic->ic_macaddr; 2318 6629 zf162725 macp->m_callbacks = &ural_m_callbacks; 2319 6629 zf162725 macp->m_min_sdu = 0; 2320 6629 zf162725 macp->m_max_sdu = IEEE80211_MTU; 2321 6629 zf162725 macp->m_pdata = &wd; 2322 6629 zf162725 macp->m_pdata_size = sizeof (wd); 2323 6629 zf162725 2324 6629 zf162725 err = mac_register(macp, &ic->ic_mach); 2325 6629 zf162725 mac_free(macp); 2326 6629 zf162725 if (err != 0) { 2327 9345 Quaker ral_debug(RAL_DBG_ERR, "ural_attach(): " 2328 6629 zf162725 "mac_register() err %x\n", err); 2329 6629 zf162725 goto fail3; 2330 6629 zf162725 } 2331 6629 zf162725 2332 9345 Quaker if (usb_register_hotplug_cbs(devinfo, ural_disconnect, 2333 9345 Quaker ural_reconnect) != USB_SUCCESS) { 2334 9345 Quaker ral_debug(RAL_DBG_ERR, 2335 6629 zf162725 "ural: ural_attach() failed to register events"); 2336 6629 zf162725 goto fail4; 2337 6629 zf162725 } 2338 6629 zf162725 2339 6629 zf162725 /* 2340 6629 zf162725 * Create minor node of type DDI_NT_NET_WIFI 2341 6629 zf162725 */ 2342 6629 zf162725 (void) snprintf(strbuf, sizeof (strbuf), "%s%d", 2343 6629 zf162725 "ural", instance); 2344 6629 zf162725 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR, 2345 6629 zf162725 instance + 1, DDI_NT_NET_WIFI, 0); 2346 6629 zf162725 2347 6629 zf162725 if (err != DDI_SUCCESS) 2348 9345 Quaker ral_debug(RAL_DBG_ERR, "ddi_create_minor_node() failed\n"); 2349 6629 zf162725 2350 6629 zf162725 /* 2351 6629 zf162725 * Notify link is down now 2352 6629 zf162725 */ 2353 6629 zf162725 mac_link_update(ic->ic_mach, LINK_STATE_DOWN); 2354 6629 zf162725 2355 6629 zf162725 return (DDI_SUCCESS); 2356 6629 zf162725 fail4: 2357 6629 zf162725 (void) mac_unregister(ic->ic_mach); 2358 6629 zf162725 fail3: 2359 6629 zf162725 mutex_destroy(&sc->sc_genlock); 2360 6629 zf162725 mutex_destroy(&sc->tx_lock); 2361 6629 zf162725 mutex_destroy(&sc->rx_lock); 2362 6629 zf162725 fail2: 2363 6629 zf162725 usb_client_detach(sc->sc_dev, sc->sc_udev); 2364 6629 zf162725 fail1: 2365 6629 zf162725 ddi_soft_state_free(ural_soft_state_p, ddi_get_instance(devinfo)); 2366 6629 zf162725 2367 6629 zf162725 return (DDI_FAILURE); 2368 6629 zf162725 } 2369 6629 zf162725 2370 6629 zf162725 static int 2371 6629 zf162725 ural_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2372 6629 zf162725 { 2373 6629 zf162725 struct ural_softc *sc; 2374 6629 zf162725 2375 6629 zf162725 sc = ddi_get_soft_state(ural_soft_state_p, ddi_get_instance(devinfo)); 2376 9345 Quaker ASSERT(sc != NULL); 2377 6629 zf162725 2378 9345 Quaker switch (cmd) { 2379 9345 Quaker case DDI_DETACH: 2380 9345 Quaker break; 2381 9345 Quaker case DDI_SUSPEND: 2382 9345 Quaker if (RAL_IS_RUNNING(sc)) 2383 9345 Quaker (void) ural_stop(sc); 2384 9345 Quaker return (DDI_SUCCESS); 2385 9345 Quaker default: 2386 6629 zf162725 return (DDI_FAILURE); 2387 9345 Quaker } 2388 6629 zf162725 2389 7507 Xinghua if (mac_disable(sc->sc_ic.ic_mach) != 0) 2390 7507 Xinghua return (DDI_FAILURE); 2391 7507 Xinghua 2392 6629 zf162725 ural_stop(sc); 2393 6629 zf162725 usb_unregister_hotplug_cbs(devinfo); 2394 6629 zf162725 2395 6629 zf162725 /* 2396 6629 zf162725 * Unregister from the MAC layer subsystem 2397 6629 zf162725 */ 2398 7507 Xinghua (void) mac_unregister(sc->sc_ic.ic_mach); 2399 6629 zf162725 2400 6629 zf162725 /* 2401 6629 zf162725 * detach ieee80211 layer 2402 6629 zf162725 */ 2403 6629 zf162725 ieee80211_detach(&sc->sc_ic); 2404 6629 zf162725 2405 6629 zf162725 mutex_destroy(&sc->sc_genlock); 2406 6629 zf162725 mutex_destroy(&sc->tx_lock); 2407 6629 zf162725 mutex_destroy(&sc->rx_lock); 2408 6629 zf162725 2409 6629 zf162725 /* pipes will be close in ural_stop() */ 2410 6629 zf162725 usb_client_detach(devinfo, sc->sc_udev); 2411 6629 zf162725 sc->sc_udev = NULL; 2412 6629 zf162725 2413 6629 zf162725 ddi_remove_minor_node(devinfo, NULL); 2414 6629 zf162725 ddi_soft_state_free(ural_soft_state_p, ddi_get_instance(devinfo)); 2415 6629 zf162725 2416 6629 zf162725 return (DDI_SUCCESS); 2417 6629 zf162725 } 2418 6629 zf162725 2419 6629 zf162725 int 2420 6629 zf162725 _info(struct modinfo *modinfop) 2421 6629 zf162725 { 2422 6629 zf162725 return (mod_info(&modlinkage, modinfop)); 2423 6629 zf162725 } 2424 6629 zf162725 2425 6629 zf162725 int 2426 6629 zf162725 _init(void) 2427 6629 zf162725 { 2428 6629 zf162725 int status; 2429 6629 zf162725 2430 6629 zf162725 status = ddi_soft_state_init(&ural_soft_state_p, 2431 6629 zf162725 sizeof (struct ural_softc), 1); 2432 6629 zf162725 if (status != 0) 2433 6629 zf162725 return (status); 2434 6629 zf162725 2435 6629 zf162725 mac_init_ops(&ural_dev_ops, "ural"); 2436 6629 zf162725 status = mod_install(&modlinkage); 2437 6629 zf162725 if (status != 0) { 2438 6629 zf162725 mac_fini_ops(&ural_dev_ops); 2439 6629 zf162725 ddi_soft_state_fini(&ural_soft_state_p); 2440 6629 zf162725 } 2441 6629 zf162725 return (status); 2442 6629 zf162725 } 2443 6629 zf162725 2444 6629 zf162725 int 2445 6629 zf162725 _fini(void) 2446 6629 zf162725 { 2447 6629 zf162725 int status; 2448 6629 zf162725 2449 6629 zf162725 status = mod_remove(&modlinkage); 2450 6629 zf162725 if (status == 0) { 2451 6629 zf162725 mac_fini_ops(&ural_dev_ops); 2452 6629 zf162725 ddi_soft_state_fini(&ural_soft_state_p); 2453 6629 zf162725 } 2454 6629 zf162725 return (status); 2455 6629 zf162725 } 2456
Indexes created Fri Nov 27 17:59:51 UTC 2009
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