1 5578 mx205022 /* 2 5578 mx205022 * CDDL HEADER START 3 5578 mx205022 * 4 5578 mx205022 * The contents of this file are subject to the terms of the 5 5578 mx205022 * Common Development and Distribution License (the "License"). 6 5578 mx205022 * You may not use this file except in compliance with the License. 7 5578 mx205022 * 8 5578 mx205022 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 5578 mx205022 * or http://www.opensolaris.org/os/licensing. 10 5578 mx205022 * See the License for the specific language governing permissions 11 5578 mx205022 * and limitations under the License. 12 5578 mx205022 * 13 5578 mx205022 * When distributing Covered Code, include this CDDL HEADER in each 14 5578 mx205022 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 5578 mx205022 * If applicable, add the following below this CDDL HEADER, with the 16 5578 mx205022 * fields enclosed by brackets "[]" replaced with your own identifying 17 5578 mx205022 * information: Portions Copyright [yyyy] [name of copyright owner] 18 5578 mx205022 * 19 5578 mx205022 * CDDL HEADER END 20 5578 mx205022 */ 21 5578 mx205022 22 5574 mx205022 /* 23 9708 Zhen * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 5574 mx205022 * Use is subject to license terms. 25 5574 mx205022 */ 26 5574 mx205022 27 5574 mx205022 #ifndef _SYS_NGE_H 28 5574 mx205022 #define _SYS_NGE_H 29 5574 mx205022 30 5574 mx205022 #ifdef __cplusplus 31 5574 mx205022 extern "C" { 32 5574 mx205022 #endif 33 5574 mx205022 34 5574 mx205022 35 5574 mx205022 #include <sys/types.h> 36 5574 mx205022 #include <sys/stream.h> 37 5574 mx205022 #include <sys/strsun.h> 38 5574 mx205022 #include <sys/strsubr.h> 39 5574 mx205022 #include <sys/stat.h> 40 5574 mx205022 #include <sys/pci.h> 41 5574 mx205022 #include <sys/note.h> 42 5574 mx205022 #include <sys/modctl.h> 43 5574 mx205022 #include <sys/kstat.h> 44 5574 mx205022 #include <sys/ethernet.h> 45 5574 mx205022 #include <sys/pattr.h> 46 5574 mx205022 #include <sys/errno.h> 47 5574 mx205022 #include <sys/dlpi.h> 48 5574 mx205022 #include <sys/devops.h> 49 5574 mx205022 #include <sys/debug.h> 50 5574 mx205022 #include <sys/conf.h> 51 5574 mx205022 #include <sys/callb.h> 52 5574 mx205022 53 5574 mx205022 #include <netinet/ip6.h> 54 5574 mx205022 55 5574 mx205022 #include <inet/common.h> 56 5574 mx205022 #include <inet/ip.h> 57 5574 mx205022 #include <netinet/udp.h> 58 5574 mx205022 #include <inet/mi.h> 59 5574 mx205022 #include <inet/nd.h> 60 5574 mx205022 61 5574 mx205022 #include <sys/ddi.h> 62 5574 mx205022 #include <sys/sunddi.h> 63 5574 mx205022 64 8275 Eric #include <sys/mac_provider.h> 65 5574 mx205022 #include <sys/mac_ether.h> 66 5574 mx205022 67 5574 mx205022 /* 68 5574 mx205022 * Reconfiguring the network devices requires the net_config privilege 69 5574 mx205022 * in Solaris 10+. 70 5574 mx205022 */ 71 5574 mx205022 extern int secpolicy_net_config(const cred_t *, boolean_t); 72 5574 mx205022 73 5574 mx205022 #include <sys/netlb.h> 74 5574 mx205022 #include <sys/miiregs.h> 75 5574 mx205022 76 5574 mx205022 #include "nge_chip.h" 77 5574 mx205022 78 5574 mx205022 #define PIO_ADDR(ngep, offset) ((void *)((caddr_t)(ngep)->io_regs+(offset))) 79 5574 mx205022 /* 80 5574 mx205022 * Copy an ethernet address 81 5574 mx205022 */ 82 5574 mx205022 #define ethaddr_copy(src, dst) bcopy((src), (dst), ETHERADDRL) 83 5574 mx205022 #define ether_eq(a, b) (bcmp((caddr_t)(a), (caddr_t)(b), (ETHERADDRL)) == 0) 84 5574 mx205022 85 5574 mx205022 #define BIS(w, b) (((w) & (b)) ? B_TRUE : B_FALSE) 86 5574 mx205022 #define BIC(w, b) (((w) & (b)) ? B_FALSE : B_TRUE) 87 5574 mx205022 #define UPORDOWN(x) ((x) ? "up" : "down") 88 5574 mx205022 89 5574 mx205022 #define NGE_DRIVER_NAME "nge" 90 5574 mx205022 91 5574 mx205022 /* 92 5574 mx205022 * 'Progress' bit flags ... 93 5574 mx205022 */ 94 5574 mx205022 #define PROGRESS_CFG 0x0001 /* config space mapped */ 95 5574 mx205022 #define PROGRESS_REGS 0x0002 /* registers mapped */ 96 5574 mx205022 #define PROGRESS_BUFS 0x0004 /* registers mapped */ 97 5574 mx205022 #define PROGRESS_RESCHED 0x0008 /* resched softint registered */ 98 5574 mx205022 #define PROGRESS_FACTOTUM 0x0010 /* factotum softint registered */ 99 5574 mx205022 #define PROGRESS_SWINT 0x0020 /* s/w interrupt registered */ 100 5574 mx205022 #define PROGRESS_INTR 0x0040 /* h/w interrupt registered */ 101 5574 mx205022 /* and mutexen initialised */ 102 5574 mx205022 #define PROGRESS_HWINT 0x0080 103 5574 mx205022 #define PROGRESS_PHY 0x0100 /* PHY initialised */ 104 5574 mx205022 #define PROGRESS_NDD 0x0200 /* NDD parameters set up */ 105 5574 mx205022 #define PROGRESS_KSTATS 0x0400 /* kstats created */ 106 5574 mx205022 #define PROGRESS_READY 0x0800 /* ready for work */ 107 5574 mx205022 108 5574 mx205022 #define NGE_HW_ERR 0x00 109 5574 mx205022 #define NGE_HW_LINK 0x01 110 5574 mx205022 #define NGE_HW_BM 0x02 111 5574 mx205022 #define NGE_HW_RCHAN 0x03 112 5574 mx205022 #define NGE_HW_TCHAN 0x04 113 5574 mx205022 #define NGE_HW_ROM 0x05 114 5574 mx205022 #define NGE_SW_PROBLEM_ID 0x06 115 5574 mx205022 116 5574 mx205022 117 5574 mx205022 /* 118 5574 mx205022 * NOTES: 119 5574 mx205022 * 120 5574 mx205022 * #defines: 121 5574 mx205022 * 122 5574 mx205022 * NGE_PCI_CONFIG_RNUMBER and NGE_PCI_OPREGS_RNUMBER are the 123 5574 mx205022 * register-set numbers to use for the config space registers 124 5574 mx205022 * and the operating registers respectively. On an OBP-based 125 5574 mx205022 * machine, regset 0 refers to CONFIG space, and regset 1 will 126 5574 mx205022 * be the operating registers in MEMORY space. If an expansion 127 5574 mx205022 * ROM is fitted, it may appear as a further register set. 128 5574 mx205022 * 129 5574 mx205022 * NGE_DMA_MODE defines the mode (STREAMING/CONSISTENT) used 130 5574 mx205022 * for the data buffers. The descriptors are always set up 131 5574 mx205022 * in CONSISTENT mode. 132 5574 mx205022 * 133 5574 mx205022 * NGE_HEADROOM defines how much space we'll leave in allocated 134 5574 mx205022 * mblks before the first valid data byte. This should be chosen 135 5574 mx205022 * to be 2 modulo 4, so that once the ethernet header (14 bytes) 136 5574 mx205022 * has been stripped off, the packet data will be 4-byte aligned. 137 5574 mx205022 * The remaining space can be used by upstream modules to prepend 138 5574 mx205022 * any headers required. 139 5574 mx205022 */ 140 5574 mx205022 141 5574 mx205022 142 5574 mx205022 #define NGE_PCI_OPREGS_RNUMBER 1 143 5574 mx205022 #define NGE_DMA_MODE DDI_DMA_STREAMING 144 5574 mx205022 #define NGE_HEADROOM 6 145 5574 mx205022 #define ETHER_HEAD_LEN 14 146 5574 mx205022 #ifndef VTAG_SIZE 147 5574 mx205022 #define VTAG_SIZE 4 148 5574 mx205022 #endif 149 5574 mx205022 150 10615 Zhen #define NGE_CYCLIC_PERIOD (1000000000) 151 5574 mx205022 152 5574 mx205022 #define NGE_DEFAULT_MTU 1500 153 5574 mx205022 #define NGE_DEFAULT_SDU 1518 154 5574 mx205022 #define NGE_MTU_2500 2500 155 5574 mx205022 #define NGE_MTU_4500 4500 156 5574 mx205022 #define NGE_MAX_MTU 9000 157 5574 mx205022 #define NGE_MAX_SDU 9018 158 5574 mx205022 159 5659 jj146644 #define NGE_DESC_MIN 0x200 160 5574 mx205022 161 5574 mx205022 #define NGE_STD_BUFSZ 1792 162 5574 mx205022 #define NGE_JB2500_BUFSZ (3*1024) 163 5574 mx205022 #define NGE_JB4500_BUFSZ (5*1024) 164 5574 mx205022 #define NGE_JB9000_BUFSZ (9*1024) 165 5574 mx205022 166 5574 mx205022 #define NGE_SEND_SLOTS_DESC_1024 1024 167 5574 mx205022 #define NGE_SEND_SLOTS_DESC_3072 3072 168 5574 mx205022 #define NGE_SEND_JB2500_SLOTS_DESC 3072 169 5574 mx205022 #define NGE_SEND_JB4500_SLOTS_DESC 2048 170 5574 mx205022 #define NGE_SEND_JB9000_SLOTS_DESC 1024 171 5574 mx205022 #define NGE_SEND_LOWMEM_SLOTS_DESC 1024 172 5574 mx205022 #define NGE_SEND_SLOTS_BUF 3072 173 5574 mx205022 174 5574 mx205022 #define NGE_RECV_SLOTS_DESC_1024 1024 175 5574 mx205022 #define NGE_RECV_SLOTS_DESC_3072 3072 176 5574 mx205022 #define NGE_RECV_JB2500_SLOTS_DESC 3072 177 5574 mx205022 #define NGE_RECV_JB4500_SLOTS_DESC 2048 178 5574 mx205022 #define NGE_RECV_JB9000_SLOTS_DESC 1024 179 5574 mx205022 #define NGE_RECV_LOWMEM_SLOTS_DESC 1024 180 5574 mx205022 #define NGE_RECV_SLOTS_BUF 6144 181 5574 mx205022 182 5574 mx205022 #define NGE_SPLIT_32 32 183 5574 mx205022 #define NGE_SPLIT_96 96 184 5574 mx205022 #define NGE_SPLIT_256 256 185 5574 mx205022 186 5574 mx205022 #define NGE_RX_COPY_SIZE 512 187 5574 mx205022 #define NGE_TX_COPY_SIZE 512 188 5574 mx205022 #define NGE_MAP_FRAGS 3 189 5574 mx205022 #define NGE_MAX_COOKIES 3 190 5574 mx205022 #define NGE_MAX_DMA_HDR (4*1024) 191 5574 mx205022 192 5659 jj146644 /* Used by interrupt moderation */ 193 10615 Zhen #define NGE_TFINT_DEFAULT 32 194 10615 Zhen #define NGE_POLL_TUNE 80000 195 10615 Zhen #define NGE_POLL_ENTER 10000 196 10615 Zhen #define NGE_POLL_MAX 1280000 197 5659 jj146644 #define NGE_POLL_QUIET_TIME 100 198 5659 jj146644 #define NGE_POLL_BUSY_TIME 2 199 5574 mx205022 200 5574 mx205022 /* 201 5574 mx205022 * NGE-specific ioctls ... 202 5574 mx205022 */ 203 5574 mx205022 #define NGE_IOC ((((('N' << 8) + 'G') << 8) + 'E') << 8) 204 5574 mx205022 205 5574 mx205022 /* 206 5574 mx205022 * PHY register read/write ioctls, used by cable test software 207 5574 mx205022 */ 208 5574 mx205022 #define NGE_MII_READ (NGE_IOC|1) 209 5574 mx205022 #define NGE_MII_WRITE (NGE_IOC|2) 210 5574 mx205022 211 5574 mx205022 /* 212 5574 mx205022 * SEEPROM read/write ioctls, for use by SEEPROM upgrade utility 213 5574 mx205022 * 214 5574 mx205022 * Note: SEEPROMs can only be accessed as 32-bit words, so <see_addr> 215 5574 mx205022 * must be a multiple of 4. Not all systems have a SEEPROM fitted! 216 5574 mx205022 */ 217 5574 mx205022 #define NGE_SEE_READ (NGE_IOC|3) 218 5574 mx205022 #define NGE_SEE_WRITE (NGE_IOC|4) 219 5574 mx205022 220 5574 mx205022 221 5574 mx205022 /* 222 5574 mx205022 * These diagnostic IOCTLS are enabled only in DEBUG drivers 223 5574 mx205022 */ 224 5574 mx205022 #define NGE_DIAG (NGE_IOC|5) /* currently a no-op */ 225 5574 mx205022 #define NGE_PEEK (NGE_IOC|6) 226 5574 mx205022 #define NGE_POKE (NGE_IOC|7) 227 5574 mx205022 #define NGE_PHY_RESET (NGE_IOC|8) 228 5574 mx205022 #define NGE_SOFT_RESET (NGE_IOC|9) 229 5574 mx205022 #define NGE_HARD_RESET (NGE_IOC|10) 230 5574 mx205022 231 5574 mx205022 232 5574 mx205022 enum NGE_HW_OP { 233 5574 mx205022 NGE_CLEAR = 0, 234 5574 mx205022 NGE_SET 235 5574 mx205022 }; 236 5574 mx205022 237 5574 mx205022 /* 238 5574 mx205022 * Required state according to GLD 239 5574 mx205022 */ 240 5574 mx205022 enum nge_mac_state { 241 5574 mx205022 NGE_MAC_UNKNOWN, 242 5574 mx205022 NGE_MAC_RESET, 243 5574 mx205022 NGE_MAC_STOPPED, 244 5574 mx205022 NGE_MAC_STARTED, 245 5574 mx205022 NGE_MAC_UNATTACH 246 5574 mx205022 }; 247 5574 mx205022 enum loop_type { 248 5574 mx205022 NGE_LOOP_NONE = 0, 249 5574 mx205022 NGE_LOOP_EXTERNAL_100, 250 5574 mx205022 NGE_LOOP_EXTERNAL_10, 251 5574 mx205022 NGE_LOOP_INTERNAL_PHY, 252 5574 mx205022 }; 253 5574 mx205022 254 5574 mx205022 /* 255 5574 mx205022 * (Internal) return values from send_msg subroutines 256 5574 mx205022 */ 257 5574 mx205022 enum send_status { 258 5574 mx205022 SEND_COPY_FAIL = -1, /* => GLD_NORESOURCES */ 259 5574 mx205022 SEND_MAP_FAIL, /* => GLD_NORESOURCES */ 260 5574 mx205022 SEND_COPY_SUCESS, /* OK, msg queued */ 261 5574 mx205022 SEND_MAP_SUCCESS /* OK, free msg */ 262 5574 mx205022 }; 263 5574 mx205022 264 5574 mx205022 /* 265 5574 mx205022 * (Internal) return values from ioctl subroutines 266 5574 mx205022 */ 267 5574 mx205022 enum ioc_reply { 268 5574 mx205022 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 269 5574 mx205022 IOC_DONE, /* OK, reply sent */ 270 5574 mx205022 IOC_ACK, /* OK, just send ACK */ 271 5574 mx205022 IOC_REPLY, /* OK, just send reply */ 272 5574 mx205022 IOC_RESTART_ACK, /* OK, restart & ACK */ 273 5574 mx205022 IOC_RESTART_REPLY /* OK, restart & reply */ 274 5574 mx205022 }; 275 5574 mx205022 276 5574 mx205022 enum nge_pp_type { 277 5574 mx205022 NGE_PP_SPACE_CFG = 0, 278 5574 mx205022 NGE_PP_SPACE_REG, 279 5574 mx205022 NGE_PP_SPACE_NIC, 280 5574 mx205022 NGE_PP_SPACE_MII, 281 5574 mx205022 NGE_PP_SPACE_NGE, 282 5574 mx205022 NGE_PP_SPACE_TXDESC, 283 5574 mx205022 NGE_PP_SPACE_TXBUFF, 284 5574 mx205022 NGE_PP_SPACE_RXDESC, 285 5574 mx205022 NGE_PP_SPACE_RXBUFF, 286 5574 mx205022 NGE_PP_SPACE_STATISTICS, 287 5574 mx205022 NGE_PP_SPACE_SEEPROM, 288 5574 mx205022 NGE_PP_SPACE_FLASH 289 5574 mx205022 }; 290 5574 mx205022 291 5574 mx205022 /* 292 5574 mx205022 * Flag to kstat type 293 5574 mx205022 */ 294 5574 mx205022 enum nge_kstat_type { 295 5574 mx205022 NGE_KSTAT_RAW = 0, 296 5574 mx205022 NGE_KSTAT_STATS, 297 5574 mx205022 NGE_KSTAT_CHIPID, 298 5574 mx205022 NGE_KSTAT_DEBUG, 299 5574 mx205022 NGE_KSTAT_COUNT 300 5574 mx205022 }; 301 5574 mx205022 302 5574 mx205022 303 5574 mx205022 /* 304 5574 mx205022 * Actual state of the nvidia's chip 305 5574 mx205022 */ 306 5574 mx205022 enum nge_chip_state { 307 5574 mx205022 NGE_CHIP_FAULT = -2, /* fault, need reset */ 308 5574 mx205022 NGE_CHIP_ERROR, /* error, want reset */ 309 5574 mx205022 NGE_CHIP_INITIAL, /* Initial state only */ 310 5574 mx205022 NGE_CHIP_RESET, /* reset, need init */ 311 5574 mx205022 NGE_CHIP_STOPPED, /* Tx/Rx stopped */ 312 5574 mx205022 NGE_CHIP_RUNNING /* with interrupts */ 313 5574 mx205022 }; 314 5574 mx205022 315 5574 mx205022 enum nge_eeprom_size { 316 5574 mx205022 EEPROM_1K = 0, 317 5574 mx205022 EEPROM_2K, 318 5574 mx205022 EEPROM_4K, 319 5574 mx205022 EEPROM_8K, 320 5574 mx205022 EEPROM_16K, 321 5574 mx205022 EEPROM_32K, 322 5574 mx205022 EEPROM_64K 323 5574 mx205022 }; 324 5574 mx205022 325 5574 mx205022 enum nge_eeprom_access_wid { 326 5574 mx205022 ACCESS_8BIT = 0, 327 5574 mx205022 ACCESS_16BIT 328 5574 mx205022 }; 329 5574 mx205022 330 5574 mx205022 /* 331 5574 mx205022 * MDIO operation 332 5574 mx205022 */ 333 5574 mx205022 enum nge_mdio_operation { 334 5574 mx205022 NGE_MDIO_READ = 0, 335 5574 mx205022 NGE_MDIO_WRITE 336 5574 mx205022 }; 337 5574 mx205022 338 5574 mx205022 /* 339 5574 mx205022 * Speed selection 340 5574 mx205022 */ 341 5574 mx205022 enum nge_speed { 342 5574 mx205022 UNKOWN_SPEED = 0, 343 5574 mx205022 NGE_10M, 344 5574 mx205022 NGE_100M, 345 5574 mx205022 NGE_1000M 346 5574 mx205022 }; 347 5574 mx205022 348 5574 mx205022 /* 349 5574 mx205022 * Duplex selection 350 5574 mx205022 */ 351 5574 mx205022 enum nge_duplex { 352 5574 mx205022 UNKOWN_DUPLEX = 0, 353 5574 mx205022 NGE_HD, 354 5574 mx205022 NGE_FD 355 5574 mx205022 }; 356 5574 mx205022 357 5574 mx205022 typedef struct { 358 5574 mx205022 ether_addr_t addr; /* in canonical form */ 359 5574 mx205022 uint8_t spare; 360 5574 mx205022 uint8_t set; /* nonzero => valid */ 361 5574 mx205022 } nge_mac_addr_t; 362 5574 mx205022 363 5574 mx205022 struct nge; 364 5574 mx205022 365 5574 mx205022 366 5574 mx205022 #define CHIP_FLAG_COPPER 0x40 367 5574 mx205022 368 5574 mx205022 /* 369 5574 mx205022 * Collection of physical-layer functions to: 370 5574 mx205022 * (re)initialise the physical layer 371 5574 mx205022 * update it to match software settings 372 5574 mx205022 * check for link status change 373 5574 mx205022 */ 374 5574 mx205022 typedef struct { 375 6366 mx205022 boolean_t (*phys_restart)(struct nge *); 376 5574 mx205022 void (*phys_update)(struct nge *); 377 5574 mx205022 boolean_t (*phys_check)(struct nge *); 378 5574 mx205022 } phys_ops_t; 379 5574 mx205022 380 5574 mx205022 struct nge_see_rw { 381 5574 mx205022 uint32_t see_addr; /* Byte offset within SEEPROM */ 382 5574 mx205022 uint32_t see_data; /* Data read/data to write */ 383 5574 mx205022 }; 384 5574 mx205022 385 5574 mx205022 typedef struct { 386 5574 mx205022 uint64_t pp_acc_size; /* in bytes: 1,2,4,8 */ 387 5574 mx205022 uint64_t pp_acc_space; /* See #defines below */ 388 5574 mx205022 uint64_t pp_acc_offset; 389 5574 mx205022 uint64_t pp_acc_data; /* output for peek */ 390 5574 mx205022 /* input for poke */ 391 5574 mx205022 } nge_peekpoke_t; 392 5574 mx205022 393 5574 mx205022 typedef uintptr_t nge_regno_t; /* register # (offset) */ 394 5574 mx205022 395 5574 mx205022 typedef struct _mul_list { 396 5574 mx205022 struct _mul_list *next; 397 5574 mx205022 uint32_t ref_cnt; 398 5574 mx205022 ether_addr_t mul_addr; 399 5574 mx205022 }mul_item, *pmul_item; 400 5574 mx205022 401 5574 mx205022 /* 402 5574 mx205022 * Describes one chunk of allocated DMA-able memory 403 5574 mx205022 * 404 5574 mx205022 * In some cases, this is a single chunk as allocated from the system; 405 5574 mx205022 * but we also use this structure to represent slices carved off such 406 5574 mx205022 * a chunk. Even when we don't really need all the information, we 407 5574 mx205022 * use this structure as a convenient way of correlating the various 408 5574 mx205022 * ways of looking at a piece of memory (kernel VA, IO space DVMA, 409 5574 mx205022 * handle+offset, etc). 410 5574 mx205022 */ 411 5574 mx205022 typedef struct dma_area 412 5574 mx205022 { 413 5574 mx205022 414 5574 mx205022 caddr_t private; /* pointer to nge */ 415 5574 mx205022 frtn_t rx_recycle; /* recycle function */ 416 5574 mx205022 mblk_t *mp; 417 5574 mx205022 ddi_acc_handle_t acc_hdl; /* handle for memory */ 418 5574 mx205022 void *mem_va; /* CPU VA of memory */ 419 5574 mx205022 uint32_t nslots; /* number of slots */ 420 5574 mx205022 uint32_t size; /* size per slot */ 421 5574 mx205022 size_t alength; /* allocated size */ 422 5574 mx205022 /* >= product of above */ 423 5574 mx205022 ddi_dma_handle_t dma_hdl; /* DMA handle */ 424 5574 mx205022 offset_t offset; /* relative to handle */ 425 5574 mx205022 ddi_dma_cookie_t cookie; /* associated cookie */ 426 5574 mx205022 uint32_t ncookies; 427 5574 mx205022 uint32_t signature; /* buffer signature */ 428 5574 mx205022 /* for deciding to free */ 429 5574 mx205022 /* or to reuse buffers */ 430 5574 mx205022 boolean_t rx_delivered; /* hold by upper layer */ 431 5574 mx205022 struct dma_area *next; 432 5574 mx205022 } dma_area_t; 433 5574 mx205022 434 5574 mx205022 #define HOST_OWN 0x00000000 435 5574 mx205022 #define CONTROLER_OWN 0x00000001 436 5574 mx205022 #define NGE_END_PACKET 0x00000002 437 5574 mx205022 438 5574 mx205022 439 5574 mx205022 typedef struct nge_dmah_node 440 5574 mx205022 { 441 5574 mx205022 struct nge_dmah_node *next; 442 5574 mx205022 ddi_dma_handle_t hndl; 443 5574 mx205022 } nge_dmah_node_t; 444 5574 mx205022 445 5574 mx205022 typedef struct nge_dmah_list 446 5574 mx205022 { 447 5574 mx205022 nge_dmah_node_t *head; 448 5574 mx205022 nge_dmah_node_t *tail; 449 5574 mx205022 } nge_dmah_list_t; 450 5574 mx205022 451 5574 mx205022 /* 452 5574 mx205022 * Software version of the Recv Descriptor 453 5574 mx205022 * There's one of these for each recv buffer (up to 512 per ring) 454 5574 mx205022 */ 455 5574 mx205022 typedef struct sw_rx_sbd { 456 5574 mx205022 457 5574 mx205022 dma_area_t desc; /* (const) related h/w */ 458 5574 mx205022 /* descriptor area */ 459 5574 mx205022 dma_area_t *bufp; /* (const) related */ 460 5574 mx205022 /* buffer area */ 461 5574 mx205022 uint8_t flags; 462 5574 mx205022 } sw_rx_sbd_t; 463 5574 mx205022 464 5574 mx205022 /* 465 5574 mx205022 * Software version of the send Buffer Descriptor 466 5574 mx205022 * There's one of these for each send buffer (up to 512 per ring) 467 5574 mx205022 */ 468 5574 mx205022 typedef struct sw_tx_sbd { 469 5574 mx205022 470 5574 mx205022 dma_area_t desc; /* (const) related h/w */ 471 5574 mx205022 /* descriptor area */ 472 5574 mx205022 dma_area_t pbuf; /* (const) related */ 473 5574 mx205022 /* buffer area */ 474 5574 mx205022 void (*tx_recycle)(struct sw_tx_sbd *); 475 5574 mx205022 uint32_t flags; 476 5574 mx205022 mblk_t *mp; /* related mblk, if any */ 477 5574 mx205022 nge_dmah_list_t mp_hndl; 478 5574 mx205022 uint32_t frags; 479 5574 mx205022 uint32_t ncookies; /* dma cookie number */ 480 5574 mx205022 481 5574 mx205022 } sw_tx_sbd_t; 482 5574 mx205022 483 5574 mx205022 /* 484 5574 mx205022 * Software Receive Buffer (Producer) Ring Control Block 485 5574 mx205022 * There's one of these for each receiver producer ring (up to 3), 486 5574 mx205022 * but each holds buffers of a different size. 487 5574 mx205022 */ 488 5574 mx205022 typedef struct buff_ring { 489 5574 mx205022 490 5574 mx205022 uint64_t nslots; /* descriptor area */ 491 5574 mx205022 struct nge *ngep; /* (const) containing */ 492 5574 mx205022 /* driver soft state */ 493 5574 mx205022 /* initialise same */ 494 5574 mx205022 uint64_t rx_hold; 495 5574 mx205022 sw_rx_sbd_t *sw_rbds; /* software descriptors */ 496 5574 mx205022 sw_rx_sbd_t *free_rbds; /* free ring */ 497 5574 mx205022 dma_area_t *free_list; /* available buffer queue */ 498 5574 mx205022 dma_area_t *recycle_list; /* recycling buffer queue */ 499 5574 mx205022 kmutex_t recycle_lock[1]; 500 5988 vb160487 uint32_t buf_sign; /* buffer ring signature */ 501 5988 vb160487 /* for deciding to free */ 502 5988 vb160487 /* or to reuse buffers */ 503 5574 mx205022 boolean_t rx_bcopy; 504 5574 mx205022 } buff_ring_t; 505 5574 mx205022 506 5574 mx205022 /* 507 5574 mx205022 * Software Receive (Return) Ring Control Block 508 5574 mx205022 * There's one of these for each receiver return ring (up to 16). 509 5574 mx205022 */ 510 5574 mx205022 typedef struct recv_ring { 511 5574 mx205022 /* 512 5574 mx205022 * The elements flagged (const) in the comments below are 513 5574 mx205022 * set up once during initialiation and thereafter unchanged. 514 5574 mx205022 */ 515 5574 mx205022 dma_area_t desc; /* (const) related h/w */ 516 5574 mx205022 /* descriptor area */ 517 5574 mx205022 struct nge *ngep; /* (const) containing */ 518 5574 mx205022 /* driver soft state */ 519 5574 mx205022 uint16_t prod_index; /* (const) ptr to h/w */ 520 5574 mx205022 /* "producer index" */ 521 5574 mx205022 mac_resource_handle_t handle; 522 5574 mx205022 } recv_ring_t; 523 5574 mx205022 524 5574 mx205022 525 5574 mx205022 526 5574 mx205022 /* 527 5574 mx205022 * Software Send Ring Control Block 528 5574 mx205022 * There's one of these for each of (up to) 1 send rings 529 5574 mx205022 */ 530 5574 mx205022 typedef struct send_ring { 531 5574 mx205022 /* 532 5574 mx205022 * The elements flagged (const) in the comments below are 533 5574 mx205022 * set up once during initialiation and thereafter unchanged. 534 5574 mx205022 */ 535 5574 mx205022 dma_area_t desc; /* (const) related h/w */ 536 5574 mx205022 /* descriptor area */ 537 5574 mx205022 dma_area_t buf[NGE_SEND_SLOTS_BUF]; 538 5574 mx205022 /* buffer area(s) */ 539 5574 mx205022 struct nge *ngep; /* (const) containing */ 540 5574 mx205022 /* driver soft state */ 541 5574 mx205022 542 7781 Min uint32_t tx_hwmark; 543 7781 Min uint32_t tx_lwmark; 544 5574 mx205022 545 5574 mx205022 /* 546 5574 mx205022 * The tx_lock must be held when updating 547 5574 mx205022 * the s/w producer index 548 5574 mx205022 * (tx_next) 549 5574 mx205022 */ 550 5574 mx205022 kmutex_t tx_lock[1]; /* serialize h/w update */ 551 7781 Min uint32_t tx_next; /* next slot to use */ 552 7781 Min uint32_t tx_flow; 553 5574 mx205022 554 5574 mx205022 /* 555 5574 mx205022 * These counters/indexes are manipulated in the transmit 556 5574 mx205022 * path using atomics rather than mutexes for speed 557 5574 mx205022 */ 558 7781 Min uint32_t tx_free; /* # of slots available */ 559 5574 mx205022 560 5574 mx205022 /* 561 5574 mx205022 * index (tc_next). 562 5574 mx205022 */ 563 5574 mx205022 kmutex_t tc_lock[1]; 564 7781 Min uint32_t tc_next; /* next slot to recycle */ 565 5574 mx205022 /* ("consumer index") */ 566 5574 mx205022 567 5574 mx205022 sw_tx_sbd_t *sw_sbds; /* software descriptors */ 568 5574 mx205022 569 5574 mx205022 kmutex_t dmah_lock; 570 5574 mx205022 nge_dmah_list_t dmah_free; 571 5574 mx205022 nge_dmah_node_t dmahndl[NGE_MAX_DMA_HDR]; 572 5574 mx205022 573 5574 mx205022 } send_ring_t; 574 5574 mx205022 575 5574 mx205022 576 5574 mx205022 typedef struct { 577 5574 mx205022 uint32_t businfo; /* from private reg */ 578 5574 mx205022 uint16_t command; /* saved during attach */ 579 5574 mx205022 580 5574 mx205022 uint16_t vendor; /* vendor-id */ 581 5574 mx205022 uint16_t device; /* device-id */ 582 5574 mx205022 uint16_t subven; /* subsystem-vendor-id */ 583 5574 mx205022 uint16_t subdev; /* subsystem-id */ 584 5574 mx205022 uint8_t class_code; 585 5574 mx205022 uint8_t revision; /* revision-id */ 586 5574 mx205022 uint8_t clsize; /* cache-line-size */ 587 5574 mx205022 uint8_t latency; /* latency-timer */ 588 5574 mx205022 uint8_t flags; 589 5574 mx205022 590 5574 mx205022 uint16_t phy_type; /* Fiber module type */ 591 5574 mx205022 uint64_t hw_mac_addr; /* from chip register */ 592 5574 mx205022 nge_mac_addr_t vendor_addr; /* transform of same */ 593 5574 mx205022 } chip_info_t; 594 5574 mx205022 595 5574 mx205022 596 5574 mx205022 typedef struct { 597 5574 mx205022 offset_t index; 598 5574 mx205022 char *name; 599 5574 mx205022 } nge_ksindex_t; 600 5574 mx205022 601 5574 mx205022 typedef struct { 602 5574 mx205022 uint64_t tso_err_mss; 603 5574 mx205022 uint64_t tso_dis; 604 5574 mx205022 uint64_t tso_err_nosum; 605 5574 mx205022 uint64_t tso_err_hov; 606 5574 mx205022 uint64_t tso_err_huf; 607 5574 mx205022 uint64_t tso_err_l2; 608 5574 mx205022 uint64_t tso_err_ip; 609 5574 mx205022 uint64_t tso_err_l4; 610 5574 mx205022 uint64_t tso_err_tcp; 611 5574 mx205022 uint64_t hsum_err_ip; 612 5574 mx205022 uint64_t hsum_err_l4; 613 5574 mx205022 }fe_statistics_t; 614 5574 mx205022 615 5574 mx205022 /* 616 5574 mx205022 * statistics parameters to tune the driver 617 5574 mx205022 */ 618 5574 mx205022 typedef struct { 619 5574 mx205022 uint64_t intr_count; 620 5574 mx205022 uint64_t intr_lval; 621 5574 mx205022 uint64_t recv_realloc; 622 5574 mx205022 uint64_t poll_time; 623 5574 mx205022 uint64_t recy_free; 624 5574 mx205022 uint64_t recv_count; 625 5574 mx205022 uint64_t xmit_count; 626 5574 mx205022 uint64_t obytes; 627 5574 mx205022 uint64_t rbytes; 628 5574 mx205022 uint64_t mp_alloc_err; 629 5574 mx205022 uint64_t dma_alloc_err; 630 5574 mx205022 uint64_t kmem_alloc_err; 631 5574 mx205022 uint64_t load_context; 632 5574 mx205022 uint64_t ip_hwsum_err; 633 5574 mx205022 uint64_t tcp_hwsum_err; 634 5574 mx205022 uint64_t rx_nobuffer; 635 5574 mx205022 uint64_t rx_err; 636 5574 mx205022 uint64_t tx_stop_err; 637 5574 mx205022 uint64_t tx_stall; 638 5574 mx205022 uint64_t tx_rsrv_fail; 639 5574 mx205022 uint64_t tx_resched; 640 5574 mx205022 fe_statistics_t fe_err; 641 5574 mx205022 }nge_sw_statistics_t; 642 5574 mx205022 643 5574 mx205022 typedef struct { 644 5574 mx205022 nge_hw_statistics_t hw_statistics; 645 5574 mx205022 nge_sw_statistics_t sw_statistics; 646 5574 mx205022 }nge_statistics_t; 647 5574 mx205022 648 5574 mx205022 struct nge_desc_attr { 649 5574 mx205022 650 5574 mx205022 size_t rxd_size; 651 5574 mx205022 size_t txd_size; 652 5574 mx205022 653 5574 mx205022 ddi_dma_attr_t *dma_attr; 654 5574 mx205022 ddi_dma_attr_t *tx_dma_attr; 655 5574 mx205022 656 5574 mx205022 void (*rxd_fill)(void *, const ddi_dma_cookie_t *, size_t); 657 5574 mx205022 uint32_t (*rxd_check)(const void *, size_t *); 658 5574 mx205022 659 5574 mx205022 void (*txd_fill)(void *, const ddi_dma_cookie_t *, size_t, 660 10615 Zhen uint32_t, boolean_t, boolean_t); 661 5574 mx205022 662 9906 Zhen uint32_t (*txd_check)(const void *); 663 5574 mx205022 }; 664 5574 mx205022 665 5574 mx205022 typedef struct nge_desc_attr nge_desc_attr_t; 666 5574 mx205022 667 5574 mx205022 /* 668 5574 mx205022 * Structure used to hold the device-specific config parameters. 669 5574 mx205022 * The setting of such parameters may not consistent with the 670 5574 mx205022 * hardware feature of the device. It's used for software purpose. 671 5574 mx205022 */ 672 5574 mx205022 typedef struct nge_dev_spec_param { 673 5574 mx205022 boolean_t msi; /* specifies msi support */ 674 5574 mx205022 boolean_t msi_x; /* specifies msi_x support */ 675 5574 mx205022 boolean_t vlan; /* specifies vlan support */ 676 5848 jj146644 boolean_t advanced_pm; /* advanced power management support */ 677 8218 Min boolean_t mac_addr_order; /* mac address order */ 678 5574 mx205022 boolean_t tx_pause_frame; /* specifies tx pause frame support */ 679 5574 mx205022 boolean_t rx_pause_frame; /* specifies rx pause frame support */ 680 5574 mx205022 boolean_t jumbo; /* jumbo frame support */ 681 5574 mx205022 boolean_t tx_rx_64byte; /* set the max tx/rx prd fetch size */ 682 5574 mx205022 boolean_t rx_hw_checksum; /* specifies tx hw checksum feature */ 683 5574 mx205022 uint32_t tx_hw_checksum; /* specifies rx hw checksum feature */ 684 5574 mx205022 uint32_t desc_type; /* specifies descriptor type */ 685 5574 mx205022 uint32_t rx_desc_num; /* specifies rx descriptor number */ 686 5574 mx205022 uint32_t tx_desc_num; /* specifies tx descriptor number */ 687 5574 mx205022 uint32_t nge_split; /* specifies the split number */ 688 5574 mx205022 } nge_dev_spec_param_t; 689 5574 mx205022 690 5574 mx205022 typedef struct nge { 691 5574 mx205022 /* 692 5574 mx205022 * These fields are set by attach() and unchanged thereafter ... 693 5574 mx205022 */ 694 5574 mx205022 dev_info_t *devinfo; /* device instance */ 695 5574 mx205022 mac_handle_t mh; /* mac module handle */ 696 5574 mx205022 chip_info_t chipinfo; 697 5574 mx205022 ddi_acc_handle_t cfg_handle; /* DDI I/O handle */ 698 5574 mx205022 ddi_acc_handle_t io_handle; /* DDI I/O handle */ 699 5574 mx205022 void *io_regs; /* mapped registers */ 700 5574 mx205022 701 5574 mx205022 ddi_periodic_t periodic_id; /* periodical callback */ 702 5574 mx205022 uint32_t factotum_flag; 703 5574 mx205022 ddi_softint_handle_t factotum_hdl; /* factotum callback */ 704 5574 mx205022 ddi_softint_handle_t resched_hdl; /* reschedule callback */ 705 5574 mx205022 uint_t soft_pri; 706 5574 mx205022 707 5574 mx205022 ddi_intr_handle_t *htable; /* for array of interrupts */ 708 5574 mx205022 int intr_type; /* type of interrupt */ 709 5574 mx205022 int intr_actual_cnt; /* alloc intrs count */ 710 5574 mx205022 int intr_req_cnt; /* request intrs count */ 711 5574 mx205022 uint_t intr_pri; /* interrupt priority */ 712 5574 mx205022 int intr_cap; /* interrupt capabilities */ 713 5574 mx205022 714 5574 mx205022 uint32_t progress; /* attach tracking */ 715 5574 mx205022 uint32_t debug; /* flag to debug function */ 716 5574 mx205022 717 5574 mx205022 char ifname[8]; /* "nge0" ... "nge999" */ 718 5574 mx205022 719 5574 mx205022 720 5574 mx205022 enum nge_mac_state nge_mac_state; /* definitions above */ 721 5574 mx205022 enum nge_chip_state nge_chip_state; /* definitions above */ 722 5574 mx205022 boolean_t promisc; 723 7155 mx205022 boolean_t record_promisc; 724 5574 mx205022 boolean_t suspended; 725 5574 mx205022 726 5574 mx205022 int resched_needed; 727 5574 mx205022 uint32_t default_mtu; 728 5574 mx205022 uint32_t max_sdu; 729 5574 mx205022 uint32_t buf_size; 730 5574 mx205022 uint32_t rx_desc; 731 5574 mx205022 uint32_t tx_desc; 732 5574 mx205022 uint32_t rx_buf; 733 5574 mx205022 uint32_t nge_split; 734 5574 mx205022 uint32_t watchdog; 735 5574 mx205022 uint32_t lowmem_mode; 736 5574 mx205022 737 5574 mx205022 738 5574 mx205022 /* 739 5574 mx205022 * Runtime read-write data starts here ... 740 5574 mx205022 * 1 Receive Rings 741 5574 mx205022 * 1 Send Rings 742 5574 mx205022 * 743 5574 mx205022 * Note: they're not necessarily all used. 744 5574 mx205022 */ 745 5574 mx205022 struct buff_ring buff[1]; 746 5574 mx205022 struct recv_ring recv[1]; 747 5574 mx205022 struct send_ring send[1]; 748 5574 mx205022 749 5574 mx205022 750 5574 mx205022 kmutex_t genlock[1]; 751 5574 mx205022 krwlock_t rwlock[1]; 752 5574 mx205022 kmutex_t softlock[1]; 753 5574 mx205022 uint32_t intr_masks; 754 5574 mx205022 boolean_t poll; 755 5574 mx205022 boolean_t ch_intr_mode; 756 5659 jj146644 boolean_t intr_moderation; 757 5574 mx205022 uint32_t recv_count; 758 5659 jj146644 uint32_t quiet_time; 759 5659 jj146644 uint32_t busy_time; 760 10615 Zhen uint64_t tpkts_last; 761 10615 Zhen uint32_t tfint_threshold; 762 5574 mx205022 uint32_t sw_intr_intv; 763 5574 mx205022 nge_mac_addr_t cur_uni_addr; 764 5574 mx205022 uint32_t rx_datahwm; 765 5574 mx205022 uint32_t rx_prdlwm; 766 5574 mx205022 uint32_t rx_prdhwm; 767 5574 mx205022 uint32_t rx_def; 768 5574 mx205022 uint32_t desc_mode; 769 5574 mx205022 770 5574 mx205022 mul_item *pcur_mulist; 771 5574 mx205022 nge_mac_addr_t cur_mul_addr; 772 5574 mx205022 nge_mac_addr_t cur_mul_mask; 773 5574 mx205022 774 5574 mx205022 nge_desc_attr_t desc_attr; 775 5574 mx205022 776 5574 mx205022 /* 777 5574 mx205022 * Link state data (protected by genlock) 778 5574 mx205022 */ 779 5574 mx205022 int32_t link_state; /* See GLD #defines */ 780 5574 mx205022 uint32_t stall_cknum; /* Stall check number */ 781 5574 mx205022 782 5574 mx205022 uint32_t phy_xmii_addr; 783 5574 mx205022 uint32_t phy_id; 784 5574 mx205022 uint32_t phy_mode; 785 5574 mx205022 const phys_ops_t *physops; 786 5574 mx205022 uint16_t phy_gen_status; 787 5574 mx205022 788 5574 mx205022 uint32_t param_loop_mode; 789 5574 mx205022 790 5574 mx205022 kstat_t *nge_kstats[NGE_KSTAT_COUNT]; 791 5574 mx205022 nge_statistics_t statistics; 792 5574 mx205022 793 5574 mx205022 nge_dev_spec_param_t dev_spec_param; 794 5574 mx205022 795 6200 mx205022 uint32_t param_en_pause:1, 796 6200 mx205022 param_en_asym_pause:1, 797 6200 mx205022 param_en_1000hdx:1, 798 6200 mx205022 param_en_1000fdx:1, 799 6200 mx205022 param_en_100fdx:1, 800 6200 mx205022 param_en_100hdx:1, 801 6200 mx205022 param_en_10fdx:1, 802 6200 mx205022 param_en_10hdx:1, 803 6512 sowmini param_adv_autoneg:1, 804 6512 sowmini param_adv_pause:1, 805 6512 sowmini param_adv_asym_pause:1, 806 6512 sowmini param_adv_1000fdx:1, 807 6512 sowmini param_adv_1000hdx:1, 808 6512 sowmini param_adv_100fdx:1, 809 6512 sowmini param_adv_100hdx:1, 810 6512 sowmini param_adv_10fdx:1, 811 6512 sowmini param_adv_10hdx:1, 812 6512 sowmini param_lp_autoneg:1, 813 6512 sowmini param_lp_pause:1, 814 6512 sowmini param_lp_asym_pause:1, 815 6512 sowmini param_lp_1000fdx:1, 816 6512 sowmini param_lp_1000hdx:1, 817 6512 sowmini param_lp_100fdx:1, 818 6512 sowmini param_lp_100hdx:1, 819 6512 sowmini param_lp_10fdx:1, 820 6512 sowmini param_lp_10hdx:1, 821 6512 sowmini param_link_up:1, 822 6512 sowmini param_link_autoneg:1, 823 6512 sowmini param_link_rx_pause:1, 824 6512 sowmini param_link_tx_pause:1, 825 6512 sowmini param_pad_to_32:2; 826 6512 sowmini uint64_t param_link_speed; 827 6512 sowmini link_duplex_t param_link_duplex; 828 6512 sowmini int param_txbcopy_threshold; 829 6512 sowmini int param_rxbcopy_threshold; 830 6512 sowmini int param_recv_max_packet; 831 6512 sowmini int param_poll_quiet_time; 832 6512 sowmini int param_poll_busy_time; 833 6512 sowmini int param_rx_intr_hwater; 834 6512 sowmini int param_rx_intr_lwater; 835 5574 mx205022 } nge_t; 836 5574 mx205022 837 5574 mx205022 extern const nge_ksindex_t nge_statistics[]; 838 5574 mx205022 839 5574 mx205022 /* 840 5574 mx205022 * Sync a DMA area described by a dma_area_t 841 5574 mx205022 */ 842 5574 mx205022 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \ 843 5574 mx205022 (area).offset, (area).alength, (flag))) 844 5574 mx205022 845 5574 mx205022 /* 846 5574 mx205022 * Find the (kernel virtual) address of block of memory 847 5574 mx205022 * described by a dma_area_t 848 5574 mx205022 */ 849 5574 mx205022 #define DMA_VPTR(area) ((area).mem_va) 850 5574 mx205022 851 5574 mx205022 /* 852 5574 mx205022 * Zero a block of memory described by a dma_area_t 853 5574 mx205022 */ 854 5574 mx205022 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).alength) 855 5574 mx205022 856 5574 mx205022 /* 857 5574 mx205022 * Next/Prev value of a cyclic index 858 5574 mx205022 */ 859 5574 mx205022 #define NEXT(index, limit) ((index) + 1 < (limit) ? (index) + 1 : 0) 860 5574 mx205022 #define PREV(index, limit) (0 == (index) ? (limit - 1) : (index) - 1) 861 5574 mx205022 862 5574 mx205022 #define NEXT_INDEX(ndx, num, lim)\ 863 5574 mx205022 (((ndx) + (num) < (lim)) ? ((ndx) + (num)) : ((ndx) + (num) - (lim))) 864 5574 mx205022 865 5574 mx205022 866 5574 mx205022 /* 867 5574 mx205022 * Property lookups 868 5574 mx205022 */ 869 5574 mx205022 #define NGE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 870 5574 mx205022 DDI_PROP_DONTPASS, (n)) 871 5574 mx205022 #define NGE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 872 5574 mx205022 DDI_PROP_DONTPASS, (n), -1) 873 5574 mx205022 874 5574 mx205022 875 5574 mx205022 /* 876 5574 mx205022 * Debugging ... 877 5574 mx205022 */ 878 5574 mx205022 #ifdef DEBUG 879 5574 mx205022 #define NGE_DEBUGGING 1 880 5574 mx205022 #else 881 5574 mx205022 #define NGE_DEBUGGING 0 882 5574 mx205022 #endif /* DEBUG */ 883 5574 mx205022 884 5574 mx205022 /* 885 5574 mx205022 * Bit flags in the 'debug' word ... 886 5574 mx205022 */ 887 5574 mx205022 #define NGE_DBG_STOP 0x00000001 /* early debug_enter() */ 888 5574 mx205022 #define NGE_DBG_TRACE 0x00000002 /* general flow tracing */ 889 5574 mx205022 890 5574 mx205022 #define NGE_DBG_MII 0x00000010 /* low-level MII access */ 891 5574 mx205022 #define NGE_DBG_CHIP 0x00000020 /* low(ish)-level code */ 892 5574 mx205022 893 5574 mx205022 #define NGE_DBG_RECV 0x00000100 /* receive-side code */ 894 5574 mx205022 #define NGE_DBG_SEND 0x00000200 /* packet-send code */ 895 5574 mx205022 896 5574 mx205022 #define NGE_DBG_INIT 0x00100000 /* initialisation */ 897 5574 mx205022 #define NGE_DBG_NEMO 0x00200000 /* MAC layer entry points */ 898 5574 mx205022 #define NGE_DBG_STATS 0x00400000 /* statistics */ 899 5574 mx205022 900 5574 mx205022 #define NGE_DBG_BADIOC 0x01000000 /* unknown ioctls */ 901 5574 mx205022 902 5574 mx205022 #define NGE_DBG_NDD 0x10000000 /* NDD operations */ 903 5574 mx205022 904 5574 mx205022 905 5574 mx205022 906 5574 mx205022 /* 907 5574 mx205022 * 'Do-if-debugging' macro. The parameter <command> should be one or more 908 5574 mx205022 * C statements (but without the *final* semicolon), which will either be 909 5574 mx205022 * compiled inline or completely ignored, depending on the NGE_DEBUGGING 910 5574 mx205022 * compile-time flag. 911 5574 mx205022 * 912 5574 mx205022 * You should get a compile-time error (at least on a DEBUG build) if 913 5574 mx205022 * your statement isn't actually a statement, rather than unexpected 914 5574 mx205022 * run-time behaviour caused by unintended matching of if-then-elses etc. 915 5574 mx205022 * 916 5574 mx205022 * Note that the NGE_DDB() macro itself can only be used as a statement, 917 5574 mx205022 * not an expression, and should always be followed by a semicolon. 918 5574 mx205022 */ 919 5574 mx205022 #if NGE_DEBUGGING 920 5574 mx205022 #define NGE_DDB(command) do { \ 921 5574 mx205022 { command; } \ 922 5574 mx205022 _NOTE(CONSTANTCONDITION) \ 923 5574 mx205022 } while (0) 924 5574 mx205022 #else /* NGE_DEBUGGING */ 925 5574 mx205022 #define NGE_DDB(command) 926 5574 mx205022 /* 927 5574 mx205022 * Old way of debugging. This is a poor way, as it leeaves empty 928 5574 mx205022 * statements that cause lint to croak. 929 5574 mx205022 * #define NGE_DDB(command) do { \ 930 5574 mx205022 * { _NOTE(EMPTY); } \ 931 5574 mx205022 * _NOTE(CONSTANTCONDITION) \ 932 5574 mx205022 * } while (0) 933 5574 mx205022 */ 934 5574 mx205022 #endif /* NGE_DEBUGGING */ 935 5574 mx205022 936 5574 mx205022 /* 937 5574 mx205022 * 'Internal' macros used to construct the TRACE/DEBUG macros below. 938 5574 mx205022 * These provide the primitive conditional-call capability required. 939 5574 mx205022 * Note: the parameter <args> is a parenthesised list of the actual 940 5574 mx205022 * printf-style arguments to be passed to the debug function ... 941 5574 mx205022 */ 942 5574 mx205022 #define NGE_XDB(b, w, f, args) NGE_DDB(if ((b) & (w)) f args) 943 5574 mx205022 #define NGE_GDB(b, args) NGE_XDB(b, nge_debug, (*nge_gdb()), args) 944 5574 mx205022 #define NGE_LDB(b, args) NGE_XDB(b, ngep->debug, \ 945 5574 mx205022 (*nge_db(ngep)), args) 946 5574 mx205022 #define NGE_CDB(f, args) NGE_XDB(NGE_DBG, ngep->debug, f, args) 947 5574 mx205022 948 5574 mx205022 /* 949 5574 mx205022 * Conditional-print macros. 950 5574 mx205022 * 951 5574 mx205022 * Define NGE_DBG to be the relevant member of the set of NGE_DBG_* values 952 5574 mx205022 * above before using the NGE_GDEBUG() or NGE_DEBUG() macros. The 'G' 953 5574 mx205022 * versions look at the Global debug flag word (nge_debug); the non-G 954 5574 mx205022 * versions look in the per-instance data (ngep->debug) and so require a 955 5574 mx205022 * variable called 'ngep' to be in scope (and initialised!) before use. 956 5574 mx205022 * 957 5574 mx205022 * You could redefine NGE_TRC too if you really need two different 958 5574 mx205022 * flavours of debugging output in the same area of code, but I don't 959 5574 mx205022 * really recommend it. 960 5574 mx205022 * 961 5574 mx205022 * Note: the parameter <args> is a parenthesised list of the actual 962 5574 mx205022 * arguments to be passed to the debug function, usually a printf-style 963 5574 mx205022 * format string and corresponding values to be formatted. 964 5574 mx205022 */ 965 5574 mx205022 966 5574 mx205022 #define NGE_TRC NGE_DBG_TRACE 967 5574 mx205022 968 5574 mx205022 #define NGE_GTRACE(args) NGE_GDB(NGE_TRC, args) 969 5574 mx205022 #define NGE_GDEBUG(args) NGE_GDB(NGE_DBG, args) 970 5574 mx205022 #define NGE_TRACE(args) NGE_LDB(NGE_TRC, args) 971 5574 mx205022 #define NGE_DEBUG(args) NGE_LDB(NGE_DBG, args) 972 5574 mx205022 973 5574 mx205022 /* 974 5574 mx205022 * Debug-only action macros 975 5574 mx205022 */ 976 5574 mx205022 977 5574 mx205022 978 5574 mx205022 #define NGE_REPORT(args) NGE_DDB(nge_log args) 979 5574 mx205022 980 5574 mx205022 boolean_t nge_atomic_decrease(uint64_t *count_p, uint64_t n); 981 5574 mx205022 void nge_atomic_increase(uint64_t *count_p, uint64_t n); 982 5574 mx205022 983 5574 mx205022 int nge_alloc_dma_mem(nge_t *ngep, size_t memsize, 984 5574 mx205022 ddi_device_acc_attr_t *attr_p, uint_t dma_flags, dma_area_t *dma_p); 985 5574 mx205022 void nge_free_dma_mem(dma_area_t *dma_p); 986 5574 mx205022 int nge_restart(nge_t *ngep); 987 5574 mx205022 void nge_wake_factotum(nge_t *ngep); 988 5574 mx205022 989 5574 mx205022 uint8_t nge_reg_get8(nge_t *ngep, nge_regno_t regno); 990 5574 mx205022 void nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data); 991 5574 mx205022 uint16_t nge_reg_get16(nge_t *ngep, nge_regno_t regno); 992 5574 mx205022 void nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data); 993 5574 mx205022 uint32_t nge_reg_get32(nge_t *ngep, nge_regno_t regno); 994 5574 mx205022 void nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data); 995 5574 mx205022 uint_t nge_chip_factotum(caddr_t args1, caddr_t args2); 996 5574 mx205022 void nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset); 997 5574 mx205022 void nge_init_dev_spec_param(nge_t *ngep); 998 5574 mx205022 int nge_chip_stop(nge_t *ngep, boolean_t fault); 999 5574 mx205022 void nge_restore_mac_addr(nge_t *ngep); 1000 5574 mx205022 int nge_chip_reset(nge_t *ngep); 1001 5574 mx205022 int nge_chip_start(nge_t *ngep); 1002 5574 mx205022 void nge_chip_sync(nge_t *ngep); 1003 5574 mx205022 1004 5574 mx205022 uint_t nge_chip_intr(caddr_t arg1, caddr_t arg2); 1005 5574 mx205022 enum ioc_reply nge_chip_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp); 1006 5574 mx205022 1007 5574 mx205022 void nge_phys_init(nge_t *ngep); 1008 5574 mx205022 boolean_t nge_phy_reset(nge_t *ngep); 1009 5574 mx205022 uint16_t nge_mii_get16(nge_t *ngep, nge_regno_t regno); 1010 5574 mx205022 void nge_mii_put16(nge_t *ngep, nge_regno_t regno, uint16_t data); 1011 5574 mx205022 1012 5574 mx205022 void nge_recv_recycle(caddr_t arg); 1013 5574 mx205022 void nge_receive(nge_t *ngep); 1014 5574 mx205022 1015 5574 mx205022 uint_t nge_reschedule(caddr_t args1, caddr_t args2); 1016 5574 mx205022 mblk_t *nge_m_tx(void *arg, mblk_t *mp); 1017 5574 mx205022 1018 5574 mx205022 void nge_tx_recycle(nge_t *ngep, boolean_t is_intr); 1019 5574 mx205022 void nge_tx_recycle_all(nge_t *ngep); 1020 5574 mx205022 1021 5574 mx205022 int nge_nd_init(nge_t *ngep); 1022 5574 mx205022 void nge_nd_cleanup(nge_t *ngep); 1023 5574 mx205022 1024 5574 mx205022 1025 5574 mx205022 void nge_init_kstats(nge_t *ngep, int instance); 1026 5574 mx205022 void nge_fini_kstats(nge_t *ngep); 1027 5574 mx205022 int nge_m_stat(void *arg, uint_t stat, uint64_t *val); 1028 5574 mx205022 1029 5574 mx205022 uint32_t nge_atomic_shl32(uint32_t *sp, uint_t count); 1030 5574 mx205022 1031 5574 mx205022 void nge_log(nge_t *ngep, const char *fmt, ...); 1032 5574 mx205022 void nge_problem(nge_t *ngep, const char *fmt, ...); 1033 5574 mx205022 void nge_error(nge_t *ngep, const char *fmt, ...); 1034 5574 mx205022 void 1035 5574 mx205022 nge_report(nge_t *ngep, uint8_t error_id); 1036 5574 mx205022 1037 5574 mx205022 void (*nge_db(nge_t *ngep))(const char *fmt, ...); 1038 5574 mx205022 void (*nge_gdb(void))(const char *fmt, ...); 1039 5574 mx205022 extern uint32_t nge_debug; 1040 5574 mx205022 1041 5574 mx205022 /* 1042 5574 mx205022 * DESC MODE 2 1043 5574 mx205022 */ 1044 5574 mx205022 1045 5574 mx205022 extern void nge_sum_rxd_fill(void *, const ddi_dma_cookie_t *, size_t); 1046 5574 mx205022 extern uint32_t nge_sum_rxd_check(const void *, size_t *); 1047 5574 mx205022 1048 5574 mx205022 extern void nge_sum_txd_fill(void *, const ddi_dma_cookie_t *, 1049 10615 Zhen size_t, uint32_t, boolean_t, boolean_t); 1050 9906 Zhen extern uint32_t nge_sum_txd_check(const void *); 1051 5574 mx205022 1052 5574 mx205022 /* 1053 5574 mx205022 * DESC MODE 3 1054 5574 mx205022 */ 1055 5574 mx205022 1056 5574 mx205022 extern void nge_hot_rxd_fill(void *, const ddi_dma_cookie_t *, size_t); 1057 5574 mx205022 extern uint32_t nge_hot_rxd_check(const void *, size_t *); 1058 5574 mx205022 1059 5574 mx205022 extern void nge_hot_txd_fill(void *, const ddi_dma_cookie_t *, 1060 10615 Zhen size_t, uint32_t, boolean_t, boolean_t); 1061 9906 Zhen extern uint32_t nge_hot_txd_check(const void *); 1062 5574 mx205022 1063 5574 mx205022 #ifdef __cplusplus 1064 5574 mx205022 } 1065 5574 mx205022 #endif 1066 5574 mx205022 1067 5574 mx205022 #endif /* _SYS_NGE_H */ 1068
Indexes created Fri Nov 27 18:53:17 UTC 2009
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