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      1 /*
      2  * CDDL HEADER START
      3  *
      4  * Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
      5  * The contents of this file are subject to the terms of the
      6  * Common Development and Distribution License (the "License").
      7  * You may not use this file except in compliance with the License.
      8  *
      9  * You can obtain a copy of the license at:
     10  *	http://www.opensolaris.org/os/licensing.
     11  * See the License for the specific language governing permissions
     12  * and limitations under the License.
     13  *
     14  * When using or redistributing this file, you may do so under the
     15  * License only. No other modification of this header is permitted.
     16  *
     17  * If applicable, add the following below this CDDL HEADER, with the
     18  * fields enclosed by brackets "[]" replaced with your own identifying
     19  * information: Portions Copyright [yyyy] [name of copyright owner]
     20  *
     21  * CDDL HEADER END
     22  */
     23 
     24 /*
     25  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
     26  * Use is subject to license terms of the CDDL.
     27  */
     28 
     29 /* IntelVersion: 1.69 v2-9-8_2009-6-12 */
     30 
     31 #ifndef _IGB_PHY_H
     32 #define	_IGB_PHY_H
     33 
     34 #ifdef __cplusplus
     35 extern "C" {
     36 #endif
     37 
     38 void e1000_init_phy_ops_generic(struct e1000_hw *hw);
     39 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
     40 void e1000_null_phy_generic(struct e1000_hw *hw);
     41 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active);
     42 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
     43 s32 e1000_check_downshift_generic(struct e1000_hw *hw);
     44 s32 e1000_check_polarity_m88(struct e1000_hw *hw);
     45 s32 e1000_check_polarity_igp(struct e1000_hw *hw);
     46 s32 e1000_check_polarity_ife(struct e1000_hw *hw);
     47 s32 e1000_check_reset_block_generic(struct e1000_hw *hw);
     48 s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
     49 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw);
     50 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw);
     51 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
     52 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
     53 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
     54 s32 e1000_get_cable_length_m88(struct e1000_hw *hw);
     55 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw);
     56 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw);
     57 s32 e1000_get_phy_id(struct e1000_hw *hw);
     58 s32 e1000_get_phy_info_igp(struct e1000_hw *hw);
     59 s32 e1000_get_phy_info_m88(struct e1000_hw *hw);
     60 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw);
     61 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
     62 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw);
     63 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
     64 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
     65 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
     66 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
     67 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
     68 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw);
     69 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw);
     70 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
     71 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
     72 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
     73 s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
     74 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
     75     u32 usec_interval, bool *success);
     76 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
     77 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
     78 s32 e1000_determine_phy_address(struct e1000_hw *hw);
     79 void e1000_power_up_phy_copper(struct e1000_hw *hw);
     80 void e1000_power_down_phy_copper(struct e1000_hw *hw);
     81 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
     82 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
     83 
     84 #define	E1000_MAX_PHY_ADDR		4
     85 
     86 /* IGP01E1000 Specific Registers */
     87 #define	IGP01E1000_PHY_PORT_CONFIG	0x10	/* Port Config */
     88 #define	IGP01E1000_PHY_PORT_STATUS	0x11	/* Status */
     89 #define	IGP01E1000_PHY_PORT_CTRL	0x12	/* Control */
     90 #define	IGP01E1000_PHY_LINK_HEALTH	0x13	/* PHY Link Health */
     91 #define	IGP01E1000_GMII_FIFO		0x14	/* GMII FIFO */
     92 #define	IGP01E1000_PHY_CHANNEL_QUALITY	0x15	/* PHY Channel Quality */
     93 #define	IGP02E1000_PHY_POWER_MGMT	0x19	/* Power Management */
     94 #define	IGP01E1000_PHY_PAGE_SELECT	0x1F	/* Page Select */
     95 #define	BM_PHY_PAGE_SELECT		22	/* Page Select for BM */
     96 #define	IGP_PAGE_SHIFT			5
     97 #define	PHY_REG_MASK			0x1F
     98 
     99 #define	IGP01E1000_PHY_PCS_INIT_REG	0x00B4
    100 #define	IGP01E1000_PHY_POLARITY_MASK	0x0078
    101 
    102 #define	IGP01E1000_PSCR_AUTO_MDIX	0x1000
    103 #define	IGP01E1000_PSCR_FORCE_MDI_MDIX	0x2000 /* 0=MDI, 1=MDIX */
    104 
    105 #define	IGP01E1000_PSCFR_SMART_SPEED	0x0080
    106 
    107 /* Enable flexible speed on link-up */
    108 #define	IGP01E1000_GMII_FLEX_SPD	0x0010
    109 #define	IGP01E1000_GMII_SPD		0x0020 /* Enable SPD */
    110 
    111 #define	IGP02E1000_PM_SPD		0x0001 /* Smart Power Down */
    112 #define	IGP02E1000_PM_D0_LPLU		0x0002 /* For D0a states */
    113 #define	IGP02E1000_PM_D3_LPLU		0x0004 /* For all other states */
    114 
    115 #define	IGP01E1000_PLHR_SS_DOWNGRADE	0x8000
    116 
    117 #define	IGP01E1000_PSSR_POLARITY_REVERSED	0x0002
    118 #define	IGP01E1000_PSSR_MDIX			0x0800
    119 #define	IGP01E1000_PSSR_SPEED_MASK		0xC000
    120 #define	IGP01E1000_PSSR_SPEED_1000MBPS		0xC000
    121 
    122 #define	IGP02E1000_PHY_CHANNEL_NUM		4
    123 #define	IGP02E1000_PHY_AGC_A			0x11B1
    124 #define	IGP02E1000_PHY_AGC_B			0x12B1
    125 #define	IGP02E1000_PHY_AGC_C			0x14B1
    126 #define	IGP02E1000_PHY_AGC_D			0x18B1
    127 
    128 #define	IGP02E1000_AGC_LENGTH_SHIFT	9 /* Course - 15:13, Fine - 12:9 */
    129 #define	IGP02E1000_AGC_LENGTH_MASK	0x7F
    130 #define	IGP02E1000_AGC_RANGE		15
    131 
    132 #define	IGP03E1000_PHY_MISC_CTRL	0x1B
    133 #define	IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET	0x1000 /* Manually Set Duplex */
    134 
    135 #define	E1000_CABLE_LENGTH_UNDEFINED	0xFF
    136 
    137 #define	E1000_KMRNCTRLSTA_OFFSET	0x001F0000
    138 #define	E1000_KMRNCTRLSTA_OFFSET_SHIFT	16
    139 #define	E1000_KMRNCTRLSTA_REN		0x00200000
    140 #define	E1000_KMRNCTRLSTA_DIAG_OFFSET	0x3	/* Kumeran Diagnostic */
    141 #define	E1000_KMRNCTRLSTA_TIMEOUTS	0x4	/* Kumeran Timeouts */
    142 #define	E1000_KMRNCTRLSTA_INBAND_PARAM	0x9	/* Kumeran InBand Parameters */
    143 #define	E1000_KMRNCTRLSTA_DIAG_NELPBK	0x1000	/* Nearend Loopback mode */
    144 
    145 #define	IFE_PHY_EXTENDED_STATUS_CONTROL	0x10
    146 #define	IFE_PHY_SPECIAL_CONTROL	0x11 /* 100BaseTx PHY Special Control */
    147 #define	IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
    148 #define	IFE_PHY_MDIX_CONTROL	0x1C /* MDI/MDI-X Control */
    149 
    150 /* IFE PHY Extended Status Control */
    151 #define	IFE_PESC_POLARITY_REVERSED	0x0100
    152 
    153 /* IFE PHY Special Control */
    154 #define	IFE_PSC_AUTO_POLARITY_DISABLE	0x0010
    155 #define	IFE_PSC_FORCE_POLARITY		0x0020
    156 #define	IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
    157 
    158 /* IFE PHY Special Control and LED Control */
    159 #define	IFE_PSCL_PROBE_MODE		0x0020
    160 #define	IFE_PSCL_PROBE_LEDS_OFF		0x0006 /* Force LEDs 0 and 2 off */
    161 #define	IFE_PSCL_PROBE_LEDS_ON		0x0007 /* Force LEDs 0 and 2 on */
    162 
    163 /* IFE PHY MDIX Control */
    164 #define	IFE_PMC_MDIX_STATUS	0x0020 /* 1=MDI-X, 0=MDI */
    165 #define	IFE_PMC_FORCE_MDIX	0x0040 /* 1=force MDI-X, 0=force MDI */
    166 #define	IFE_PMC_AUTO_MDIX	0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
    167 
    168 #ifdef __cplusplus
    169 }
    170 #endif
    171 
    172 #endif	/* _IGB_PHY_H */
    173