1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #include "igb_sw.h" 30 31 static char ident[] = "Intel 1Gb Ethernet"; 32 static char igb_version[] = "igb 1.1.8"; 33 34 /* 35 * Local function protoypes 36 */ 37 static int igb_register_mac(igb_t *); 38 static int igb_identify_hardware(igb_t *); 39 static int igb_regs_map(igb_t *); 40 static void igb_init_properties(igb_t *); 41 static int igb_init_driver_settings(igb_t *); 42 static void igb_init_locks(igb_t *); 43 static void igb_destroy_locks(igb_t *); 44 static int igb_init_mac_address(igb_t *); 45 static int igb_init(igb_t *); 46 static int igb_init_adapter(igb_t *); 47 static void igb_stop_adapter(igb_t *); 48 static int igb_reset(igb_t *); 49 static void igb_tx_clean(igb_t *); 50 static boolean_t igb_tx_drain(igb_t *); 51 static boolean_t igb_rx_drain(igb_t *); 52 static int igb_alloc_rings(igb_t *); 53 static void igb_free_rings(igb_t *); 54 static void igb_setup_rings(igb_t *); 55 static void igb_setup_rx(igb_t *); 56 static void igb_setup_tx(igb_t *); 57 static void igb_setup_rx_ring(igb_rx_ring_t *); 58 static void igb_setup_tx_ring(igb_tx_ring_t *); 59 static void igb_setup_rss(igb_t *); 60 static void igb_setup_mac_rss_classify(igb_t *); 61 static void igb_setup_mac_classify(igb_t *); 62 static void igb_init_unicst(igb_t *); 63 static void igb_setup_multicst(igb_t *); 64 static void igb_get_phy_state(igb_t *); 65 static void igb_get_conf(igb_t *); 66 static int igb_get_prop(igb_t *, char *, int, int, int); 67 static boolean_t igb_is_link_up(igb_t *); 68 static boolean_t igb_link_check(igb_t *); 69 static void igb_local_timer(void *); 70 static void igb_arm_watchdog_timer(igb_t *); 71 static void igb_start_watchdog_timer(igb_t *); 72 static void igb_restart_watchdog_timer(igb_t *); 73 static void igb_stop_watchdog_timer(igb_t *); 74 static void igb_disable_adapter_interrupts(igb_t *); 75 static void igb_enable_adapter_interrupts_82575(igb_t *); 76 static void igb_enable_adapter_interrupts_82576(igb_t *); 77 static boolean_t is_valid_mac_addr(uint8_t *); 78 static boolean_t igb_stall_check(igb_t *); 79 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t); 80 static void igb_set_external_loopback(igb_t *); 81 static void igb_set_internal_mac_loopback(igb_t *); 82 static void igb_set_internal_phy_loopback(igb_t *); 83 static void igb_set_internal_serdes_loopback(igb_t *); 84 static boolean_t igb_find_mac_address(igb_t *); 85 static int igb_alloc_intrs(igb_t *); 86 static int igb_alloc_intr_handles(igb_t *, int); 87 static int igb_add_intr_handlers(igb_t *); 88 static void igb_rem_intr_handlers(igb_t *); 89 static void igb_rem_intrs(igb_t *); 90 static int igb_enable_intrs(igb_t *); 91 static int igb_disable_intrs(igb_t *); 92 static void igb_setup_msix_82575(igb_t *); 93 static void igb_setup_msix_82576(igb_t *); 94 static uint_t igb_intr_legacy(void *, void *); 95 static uint_t igb_intr_msi(void *, void *); 96 static uint_t igb_intr_rx(void *, void *); 97 static uint_t igb_intr_tx(void *, void *); 98 static uint_t igb_intr_tx_other(void *, void *); 99 static void igb_intr_rx_work(igb_rx_ring_t *); 100 static void igb_intr_tx_work(igb_tx_ring_t *); 101 static void igb_intr_link_work(igb_t *); 102 static void igb_get_driver_control(struct e1000_hw *); 103 static void igb_release_driver_control(struct e1000_hw *); 104 105 static int igb_attach(dev_info_t *, ddi_attach_cmd_t); 106 static int igb_detach(dev_info_t *, ddi_detach_cmd_t); 107 static int igb_resume(dev_info_t *); 108 static int igb_suspend(dev_info_t *); 109 static int igb_quiesce(dev_info_t *); 110 static void igb_unconfigure(dev_info_t *, igb_t *); 111 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 112 const void *); 113 static void igb_fm_init(igb_t *); 114 static void igb_fm_fini(igb_t *); 115 static void igb_release_multicast(igb_t *); 116 117 static struct cb_ops igb_cb_ops = { 118 nulldev, /* cb_open */ 119 nulldev, /* cb_close */ 120 nodev, /* cb_strategy */ 121 nodev, /* cb_print */ 122 nodev, /* cb_dump */ 123 nodev, /* cb_read */ 124 nodev, /* cb_write */ 125 nodev, /* cb_ioctl */ 126 nodev, /* cb_devmap */ 127 nodev, /* cb_mmap */ 128 nodev, /* cb_segmap */ 129 nochpoll, /* cb_chpoll */ 130 ddi_prop_op, /* cb_prop_op */ 131 NULL, /* cb_stream */ 132 D_MP | D_HOTPLUG, /* cb_flag */ 133 CB_REV, /* cb_rev */ 134 nodev, /* cb_aread */ 135 nodev /* cb_awrite */ 136 }; 137 138 static struct dev_ops igb_dev_ops = { 139 DEVO_REV, /* devo_rev */ 140 0, /* devo_refcnt */ 141 NULL, /* devo_getinfo */ 142 nulldev, /* devo_identify */ 143 nulldev, /* devo_probe */ 144 igb_attach, /* devo_attach */ 145 igb_detach, /* devo_detach */ 146 nodev, /* devo_reset */ 147 &igb_cb_ops, /* devo_cb_ops */ 148 NULL, /* devo_bus_ops */ 149 ddi_power, /* devo_power */ 150 igb_quiesce, /* devo_quiesce */ 151 }; 152 153 static struct modldrv igb_modldrv = { 154 &mod_driverops, /* Type of module. This one is a driver */ 155 ident, /* Discription string */ 156 &igb_dev_ops, /* driver ops */ 157 }; 158 159 static struct modlinkage igb_modlinkage = { 160 MODREV_1, &igb_modldrv, NULL 161 }; 162 163 /* Access attributes for register mapping */ 164 ddi_device_acc_attr_t igb_regs_acc_attr = { 165 DDI_DEVICE_ATTR_V0, 166 DDI_STRUCTURE_LE_ACC, 167 DDI_STRICTORDER_ACC, 168 DDI_FLAGERR_ACC 169 }; 170 171 #define IGB_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB) 172 173 static mac_callbacks_t igb_m_callbacks = { 174 IGB_M_CALLBACK_FLAGS, 175 igb_m_stat, 176 igb_m_start, 177 igb_m_stop, 178 igb_m_promisc, 179 igb_m_multicst, 180 NULL, 181 NULL, 182 igb_m_ioctl, 183 igb_m_getcapab 184 }; 185 186 /* 187 * Initialize capabilities of each supported adapter type 188 */ 189 static adapter_info_t igb_82575_cap = { 190 /* limits */ 191 4, /* maximum number of rx queues */ 192 1, /* minimum number of rx queues */ 193 4, /* default number of rx queues */ 194 4, /* maximum number of tx queues */ 195 1, /* minimum number of tx queues */ 196 4, /* default number of tx queues */ 197 65535, /* maximum interrupt throttle rate */ 198 0, /* minimum interrupt throttle rate */ 199 200, /* default interrupt throttle rate */ 200 201 /* function pointers */ 202 igb_enable_adapter_interrupts_82575, 203 igb_setup_msix_82575, 204 205 /* capabilities */ 206 (IGB_FLAG_HAS_DCA | /* capability flags */ 207 IGB_FLAG_VMDQ_POOL), 208 209 0xffc00000 /* mask for RXDCTL register */ 210 }; 211 212 static adapter_info_t igb_82576_cap = { 213 /* limits */ 214 16, /* maximum number of rx queues */ 215 1, /* minimum number of rx queues */ 216 4, /* default number of rx queues */ 217 16, /* maximum number of tx queues */ 218 1, /* minimum number of tx queues */ 219 4, /* default number of tx queues */ 220 65535, /* maximum interrupt throttle rate */ 221 0, /* minimum interrupt throttle rate */ 222 200, /* default interrupt throttle rate */ 223 224 /* function pointers */ 225 igb_enable_adapter_interrupts_82576, 226 igb_setup_msix_82576, 227 228 /* capabilities */ 229 (IGB_FLAG_HAS_DCA | /* capability flags */ 230 IGB_FLAG_VMDQ_POOL | 231 IGB_FLAG_NEED_CTX_IDX), 232 233 0xffe00000 /* mask for RXDCTL register */ 234 }; 235 236 /* 237 * Module Initialization Functions 238 */ 239 240 int 241 _init(void) 242 { 243 int status; 244 245 mac_init_ops(&igb_dev_ops, MODULE_NAME); 246 247 status = mod_install(&igb_modlinkage); 248 249 if (status != DDI_SUCCESS) { 250 mac_fini_ops(&igb_dev_ops); 251 } 252 253 return (status); 254 } 255 256 int 257 _fini(void) 258 { 259 int status; 260 261 status = mod_remove(&igb_modlinkage); 262 263 if (status == DDI_SUCCESS) { 264 mac_fini_ops(&igb_dev_ops); 265 } 266 267 return (status); 268 269 } 270 271 int 272 _info(struct modinfo *modinfop) 273 { 274 int status; 275 276 status = mod_info(&igb_modlinkage, modinfop); 277 278 return (status); 279 } 280 281 /* 282 * igb_attach - driver attach 283 * 284 * This function is the device specific initialization entry 285 * point. This entry point is required and must be written. 286 * The DDI_ATTACH command must be provided in the attach entry 287 * point. When attach() is called with cmd set to DDI_ATTACH, 288 * all normal kernel services (such as kmem_alloc(9F)) are 289 * available for use by the driver. 290 * 291 * The attach() function will be called once for each instance 292 * of the device on the system with cmd set to DDI_ATTACH. 293 * Until attach() succeeds, the only driver entry points which 294 * may be called are open(9E) and getinfo(9E). 295 */ 296 static int 297 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 298 { 299 igb_t *igb; 300 struct igb_osdep *osdep; 301 struct e1000_hw *hw; 302 int instance; 303 304 /* 305 * Check the command and perform corresponding operations 306 */ 307 switch (cmd) { 308 default: 309 return (DDI_FAILURE); 310 311 case DDI_RESUME: 312 return (igb_resume(devinfo)); 313 314 case DDI_ATTACH: 315 break; 316 } 317 318 /* Get the device instance */ 319 instance = ddi_get_instance(devinfo); 320 321 /* Allocate memory for the instance data structure */ 322 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP); 323 324 igb->dip = devinfo; 325 igb->instance = instance; 326 327 hw = &igb->hw; 328 osdep = &igb->osdep; 329 hw->back = osdep; 330 osdep->igb = igb; 331 332 /* Attach the instance pointer to the dev_info data structure */ 333 ddi_set_driver_private(devinfo, igb); 334 335 336 /* Initialize for fma support */ 337 igb->fm_capabilities = igb_get_prop(igb, "fm-capable", 338 0, 0x0f, 339 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 340 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 341 igb_fm_init(igb); 342 igb->attach_progress |= ATTACH_PROGRESS_FMINIT; 343 344 /* 345 * Map PCI config space registers 346 */ 347 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 348 igb_error(igb, "Failed to map PCI configurations"); 349 goto attach_fail; 350 } 351 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 352 353 /* 354 * Identify the chipset family 355 */ 356 if (igb_identify_hardware(igb) != IGB_SUCCESS) { 357 igb_error(igb, "Failed to identify hardware"); 358 goto attach_fail; 359 } 360 361 /* 362 * Map device registers 363 */ 364 if (igb_regs_map(igb) != IGB_SUCCESS) { 365 igb_error(igb, "Failed to map device registers"); 366 goto attach_fail; 367 } 368 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 369 370 /* 371 * Initialize driver parameters 372 */ 373 igb_init_properties(igb); 374 igb->attach_progress |= ATTACH_PROGRESS_PROPS; 375 376 /* 377 * Allocate interrupts 378 */ 379 if (igb_alloc_intrs(igb) != IGB_SUCCESS) { 380 igb_error(igb, "Failed to allocate interrupts"); 381 goto attach_fail; 382 } 383 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 384 385 /* 386 * Allocate rx/tx rings based on the ring numbers. 387 * The actual numbers of rx/tx rings are decided by the number of 388 * allocated interrupt vectors, so we should allocate the rings after 389 * interrupts are allocated. 390 */ 391 if (igb_alloc_rings(igb) != IGB_SUCCESS) { 392 igb_error(igb, "Failed to allocate rx/tx rings or groups"); 393 goto attach_fail; 394 } 395 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 396 397 /* 398 * Add interrupt handlers 399 */ 400 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) { 401 igb_error(igb, "Failed to add interrupt handlers"); 402 goto attach_fail; 403 } 404 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 405 406 /* 407 * Initialize driver parameters 408 */ 409 if (igb_init_driver_settings(igb) != IGB_SUCCESS) { 410 igb_error(igb, "Failed to initialize driver settings"); 411 goto attach_fail; 412 } 413 414 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 415 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 416 goto attach_fail; 417 } 418 419 /* 420 * Initialize mutexes for this device. 421 * Do this before enabling the interrupt handler and 422 * register the softint to avoid the condition where 423 * interrupt handler can try using uninitialized mutex 424 */ 425 igb_init_locks(igb); 426 igb->attach_progress |= ATTACH_PROGRESS_LOCKS; 427 428 /* 429 * Allocate DMA resources 430 */ 431 if (igb_alloc_dma(igb) != IGB_SUCCESS) { 432 igb_error(igb, "Failed to allocate DMA resources"); 433 goto attach_fail; 434 } 435 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_DMA; 436 437 /* 438 * Initialize the adapter and setup the rx/tx rings 439 */ 440 if (igb_init(igb) != IGB_SUCCESS) { 441 igb_error(igb, "Failed to initialize adapter"); 442 goto attach_fail; 443 } 444 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 445 446 /* 447 * Initialize statistics 448 */ 449 if (igb_init_stats(igb) != IGB_SUCCESS) { 450 igb_error(igb, "Failed to initialize statistics"); 451 goto attach_fail; 452 } 453 igb->attach_progress |= ATTACH_PROGRESS_STATS; 454 455 /* 456 * Initialize NDD parameters 457 */ 458 if (igb_nd_init(igb) != IGB_SUCCESS) { 459 igb_error(igb, "Failed to initialize ndd"); 460 goto attach_fail; 461 } 462 igb->attach_progress |= ATTACH_PROGRESS_NDD; 463 464 /* 465 * Register the driver to the MAC 466 */ 467 if (igb_register_mac(igb) != IGB_SUCCESS) { 468 igb_error(igb, "Failed to register MAC"); 469 goto attach_fail; 470 } 471 igb->attach_progress |= ATTACH_PROGRESS_MAC; 472 473 /* 474 * Now that mutex locks are initialized, and the chip is also 475 * initialized, enable interrupts. 476 */ 477 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 478 igb_error(igb, "Failed to enable DDI interrupts"); 479 goto attach_fail; 480 } 481 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 482 483 igb_log(igb, "%s", igb_version); 484 igb->igb_state |= IGB_INITIALIZED; 485 486 return (DDI_SUCCESS); 487 488 attach_fail: 489 igb_unconfigure(devinfo, igb); 490 return (DDI_FAILURE); 491 } 492 493 /* 494 * igb_detach - driver detach 495 * 496 * The detach() function is the complement of the attach routine. 497 * If cmd is set to DDI_DETACH, detach() is used to remove the 498 * state associated with a given instance of a device node 499 * prior to the removal of that instance from the system. 500 * 501 * The detach() function will be called once for each instance 502 * of the device for which there has been a successful attach() 503 * once there are no longer any opens on the device. 504 * 505 * Interrupts routine are disabled, All memory allocated by this 506 * driver are freed. 507 */ 508 static int 509 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 510 { 511 igb_t *igb; 512 513 /* 514 * Check detach command 515 */ 516 switch (cmd) { 517 default: 518 return (DDI_FAILURE); 519 520 case DDI_SUSPEND: 521 return (igb_suspend(devinfo)); 522 523 case DDI_DETACH: 524 break; 525 } 526 527 528 /* 529 * Get the pointer to the driver private data structure 530 */ 531 igb = (igb_t *)ddi_get_driver_private(devinfo); 532 if (igb == NULL) 533 return (DDI_FAILURE); 534 535 /* 536 * Unregister MAC. If failed, we have to fail the detach 537 */ 538 if (mac_unregister(igb->mac_hdl) != 0) { 539 igb_error(igb, "Failed to unregister MAC"); 540 return (DDI_FAILURE); 541 } 542 igb->attach_progress &= ~ATTACH_PROGRESS_MAC; 543 544 /* 545 * If the device is still running, it needs to be stopped first. 546 * This check is necessary because under some specific circumstances, 547 * the detach routine can be called without stopping the interface 548 * first. 549 */ 550 mutex_enter(&igb->gen_lock); 551 if (igb->igb_state & IGB_STARTED) { 552 igb->igb_state &= ~IGB_STARTED; 553 igb_stop(igb); 554 mutex_exit(&igb->gen_lock); 555 /* Disable and stop the watchdog timer */ 556 igb_disable_watchdog_timer(igb); 557 } else 558 mutex_exit(&igb->gen_lock); 559 560 /* 561 * Check if there are still rx buffers held by the upper layer. 562 * If so, fail the detach. 563 */ 564 if (!igb_rx_drain(igb)) 565 return (DDI_FAILURE); 566 567 /* 568 * Do the remaining unconfigure routines 569 */ 570 igb_unconfigure(devinfo, igb); 571 572 return (DDI_SUCCESS); 573 } 574 575 /* 576 * quiesce(9E) entry point. 577 * 578 * This function is called when the system is single-threaded at high 579 * PIL with preemption disabled. Therefore, this function must not be 580 * blocked. 581 * 582 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 583 * DDI_FAILURE indicates an error condition and should almost never happen. 584 */ 585 static int 586 igb_quiesce(dev_info_t *devinfo) 587 { 588 igb_t *igb; 589 struct e1000_hw *hw; 590 591 igb = (igb_t *)ddi_get_driver_private(devinfo); 592 593 if (igb == NULL) 594 return (DDI_FAILURE); 595 596 hw = &igb->hw; 597 598 /* 599 * Disable the adapter interrupts 600 */ 601 igb_disable_adapter_interrupts(igb); 602 603 /* Tell firmware driver is no longer in control */ 604 igb_release_driver_control(hw); 605 606 /* 607 * Reset the chipset 608 */ 609 (void) e1000_reset_hw(hw); 610 611 /* 612 * Reset PHY if possible 613 */ 614 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 615 (void) e1000_phy_hw_reset(hw); 616 617 return (DDI_SUCCESS); 618 } 619 620 /* 621 * igb_unconfigure - release all resources held by this instance 622 */ 623 static void 624 igb_unconfigure(dev_info_t *devinfo, igb_t *igb) 625 { 626 /* 627 * Disable interrupt 628 */ 629 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 630 (void) igb_disable_intrs(igb); 631 } 632 633 /* 634 * Unregister MAC 635 */ 636 if (igb->attach_progress & ATTACH_PROGRESS_MAC) { 637 (void) mac_unregister(igb->mac_hdl); 638 } 639 640 /* 641 * Free ndd parameters 642 */ 643 if (igb->attach_progress & ATTACH_PROGRESS_NDD) { 644 igb_nd_cleanup(igb); 645 } 646 647 /* 648 * Free statistics 649 */ 650 if (igb->attach_progress & ATTACH_PROGRESS_STATS) { 651 kstat_delete((kstat_t *)igb->igb_ks); 652 } 653 654 /* 655 * Remove interrupt handlers 656 */ 657 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 658 igb_rem_intr_handlers(igb); 659 } 660 661 /* 662 * Remove interrupts 663 */ 664 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 665 igb_rem_intrs(igb); 666 } 667 668 /* 669 * Remove driver properties 670 */ 671 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) { 672 (void) ddi_prop_remove_all(devinfo); 673 } 674 675 /* 676 * Release the DMA resources of rx/tx rings 677 */ 678 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_DMA) { 679 igb_free_dma(igb); 680 } 681 682 /* 683 * Stop the adapter 684 */ 685 if (igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) { 686 mutex_enter(&igb->gen_lock); 687 igb_stop_adapter(igb); 688 mutex_exit(&igb->gen_lock); 689 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 690 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED); 691 } 692 693 /* 694 * Free multicast table 695 */ 696 igb_release_multicast(igb); 697 698 /* 699 * Free register handle 700 */ 701 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 702 if (igb->osdep.reg_handle != NULL) 703 ddi_regs_map_free(&igb->osdep.reg_handle); 704 } 705 706 /* 707 * Free PCI config handle 708 */ 709 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 710 if (igb->osdep.cfg_handle != NULL) 711 pci_config_teardown(&igb->osdep.cfg_handle); 712 } 713 714 /* 715 * Free locks 716 */ 717 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) { 718 igb_destroy_locks(igb); 719 } 720 721 /* 722 * Free the rx/tx rings 723 */ 724 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 725 igb_free_rings(igb); 726 } 727 728 /* 729 * Remove FMA 730 */ 731 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) { 732 igb_fm_fini(igb); 733 } 734 735 /* 736 * Free the driver data structure 737 */ 738 kmem_free(igb, sizeof (igb_t)); 739 740 ddi_set_driver_private(devinfo, NULL); 741 } 742 743 /* 744 * igb_register_mac - Register the driver and its function pointers with 745 * the GLD interface 746 */ 747 static int 748 igb_register_mac(igb_t *igb) 749 { 750 struct e1000_hw *hw = &igb->hw; 751 mac_register_t *mac; 752 int status; 753 754 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 755 return (IGB_FAILURE); 756 757 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 758 mac->m_driver = igb; 759 mac->m_dip = igb->dip; 760 mac->m_src_addr = hw->mac.addr; 761 mac->m_callbacks = &igb_m_callbacks; 762 mac->m_min_sdu = 0; 763 mac->m_max_sdu = igb->max_frame_size - 764 sizeof (struct ether_vlan_header) - ETHERFCSL; 765 mac->m_margin = VLAN_TAGSZ; 766 mac->m_v12n = MAC_VIRT_LEVEL1; 767 768 status = mac_register(mac, &igb->mac_hdl); 769 770 mac_free(mac); 771 772 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE); 773 } 774 775 /* 776 * igb_identify_hardware - Identify the type of the chipset 777 */ 778 static int 779 igb_identify_hardware(igb_t *igb) 780 { 781 struct e1000_hw *hw = &igb->hw; 782 struct igb_osdep *osdep = &igb->osdep; 783 784 /* 785 * Get the device id 786 */ 787 hw->vendor_id = 788 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 789 hw->device_id = 790 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 791 hw->revision_id = 792 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 793 hw->subsystem_device_id = 794 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 795 hw->subsystem_vendor_id = 796 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 797 798 /* 799 * Set the mac type of the adapter based on the device id 800 */ 801 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 802 return (IGB_FAILURE); 803 } 804 805 /* 806 * Install adapter capabilities based on mac type 807 */ 808 switch (hw->mac.type) { 809 case e1000_82575: 810 igb->capab = &igb_82575_cap; 811 break; 812 case e1000_82576: 813 igb->capab = &igb_82576_cap; 814 break; 815 default: 816 return (IGB_FAILURE); 817 } 818 819 return (IGB_SUCCESS); 820 } 821 822 /* 823 * igb_regs_map - Map the device registers 824 */ 825 static int 826 igb_regs_map(igb_t *igb) 827 { 828 dev_info_t *devinfo = igb->dip; 829 struct e1000_hw *hw = &igb->hw; 830 struct igb_osdep *osdep = &igb->osdep; 831 off_t mem_size; 832 833 /* 834 * First get the size of device registers to be mapped. 835 */ 836 if (ddi_dev_regsize(devinfo, IGB_ADAPTER_REGSET, &mem_size) != 837 DDI_SUCCESS) { 838 return (IGB_FAILURE); 839 } 840 841 /* 842 * Call ddi_regs_map_setup() to map registers 843 */ 844 if ((ddi_regs_map_setup(devinfo, IGB_ADAPTER_REGSET, 845 (caddr_t *)&hw->hw_addr, 0, 846 mem_size, &igb_regs_acc_attr, 847 &osdep->reg_handle)) != DDI_SUCCESS) { 848 return (IGB_FAILURE); 849 } 850 851 return (IGB_SUCCESS); 852 } 853 854 /* 855 * igb_init_properties - Initialize driver properties 856 */ 857 static void 858 igb_init_properties(igb_t *igb) 859 { 860 /* 861 * Get conf file properties, including link settings 862 * jumbo frames, ring number, descriptor number, etc. 863 */ 864 igb_get_conf(igb); 865 } 866 867 /* 868 * igb_init_driver_settings - Initialize driver settings 869 * 870 * The settings include hardware function pointers, bus information, 871 * rx/tx rings settings, link state, and any other parameters that 872 * need to be setup during driver initialization. 873 */ 874 static int 875 igb_init_driver_settings(igb_t *igb) 876 { 877 struct e1000_hw *hw = &igb->hw; 878 igb_rx_ring_t *rx_ring; 879 igb_tx_ring_t *tx_ring; 880 uint32_t rx_size; 881 uint32_t tx_size; 882 int i; 883 884 /* 885 * Initialize chipset specific hardware function pointers 886 */ 887 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 888 return (IGB_FAILURE); 889 } 890 891 /* 892 * Get bus information 893 */ 894 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 895 return (IGB_FAILURE); 896 } 897 898 /* 899 * Get the system page size 900 */ 901 igb->page_size = ddi_ptob(igb->dip, (ulong_t)1); 902 903 /* 904 * Set rx buffer size 905 * The IP header alignment room is counted in the calculation. 906 * The rx buffer size is in unit of 1K that is required by the 907 * chipset hardware. 908 */ 909 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM; 910 igb->rx_buf_size = ((rx_size >> 10) + 911 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 912 913 /* 914 * Set tx buffer size 915 */ 916 tx_size = igb->max_frame_size; 917 igb->tx_buf_size = ((tx_size >> 10) + 918 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 919 920 /* 921 * Initialize rx/tx rings parameters 922 */ 923 for (i = 0; i < igb->num_rx_rings; i++) { 924 rx_ring = &igb->rx_rings[i]; 925 rx_ring->index = i; 926 rx_ring->igb = igb; 927 928 rx_ring->ring_size = igb->rx_ring_size; 929 rx_ring->free_list_size = igb->rx_ring_size; 930 rx_ring->copy_thresh = igb->rx_copy_thresh; 931 rx_ring->limit_per_intr = igb->rx_limit_per_intr; 932 } 933 934 for (i = 0; i < igb->num_tx_rings; i++) { 935 tx_ring = &igb->tx_rings[i]; 936 tx_ring->index = i; 937 tx_ring->igb = igb; 938 if (igb->tx_head_wb_enable) 939 tx_ring->tx_recycle = igb_tx_recycle_head_wb; 940 else 941 tx_ring->tx_recycle = igb_tx_recycle_legacy; 942 943 tx_ring->ring_size = igb->tx_ring_size; 944 tx_ring->free_list_size = igb->tx_ring_size + 945 (igb->tx_ring_size >> 1); 946 tx_ring->copy_thresh = igb->tx_copy_thresh; 947 tx_ring->recycle_thresh = igb->tx_recycle_thresh; 948 tx_ring->overload_thresh = igb->tx_overload_thresh; 949 tx_ring->resched_thresh = igb->tx_resched_thresh; 950 } 951 952 /* 953 * Initialize values of interrupt throttling rates 954 */ 955 for (i = 1; i < MAX_NUM_EITR; i++) 956 igb->intr_throttling[i] = igb->intr_throttling[0]; 957 958 /* 959 * The initial link state should be "unknown" 960 */ 961 igb->link_state = LINK_STATE_UNKNOWN; 962 963 return (IGB_SUCCESS); 964 } 965 966 /* 967 * igb_init_locks - Initialize locks 968 */ 969 static void 970 igb_init_locks(igb_t *igb) 971 { 972 igb_rx_ring_t *rx_ring; 973 igb_tx_ring_t *tx_ring; 974 int i; 975 976 for (i = 0; i < igb->num_rx_rings; i++) { 977 rx_ring = &igb->rx_rings[i]; 978 mutex_init(&rx_ring->rx_lock, NULL, 979 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 980 mutex_init(&rx_ring->recycle_lock, NULL, 981 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 982 } 983 984 for (i = 0; i < igb->num_tx_rings; i++) { 985 tx_ring = &igb->tx_rings[i]; 986 mutex_init(&tx_ring->tx_lock, NULL, 987 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 988 mutex_init(&tx_ring->recycle_lock, NULL, 989 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 990 mutex_init(&tx_ring->tcb_head_lock, NULL, 991 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 992 mutex_init(&tx_ring->tcb_tail_lock, NULL, 993 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 994 } 995 996 mutex_init(&igb->gen_lock, NULL, 997 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 998 999 mutex_init(&igb->watchdog_lock, NULL, 1000 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1001 } 1002 1003 /* 1004 * igb_destroy_locks - Destroy locks 1005 */ 1006 static void 1007 igb_destroy_locks(igb_t *igb) 1008 { 1009 igb_rx_ring_t *rx_ring; 1010 igb_tx_ring_t *tx_ring; 1011 int i; 1012 1013 for (i = 0; i < igb->num_rx_rings; i++) { 1014 rx_ring = &igb->rx_rings[i]; 1015 mutex_destroy(&rx_ring->rx_lock); 1016 mutex_destroy(&rx_ring->recycle_lock); 1017 } 1018 1019 for (i = 0; i < igb->num_tx_rings; i++) { 1020 tx_ring = &igb->tx_rings[i]; 1021 mutex_destroy(&tx_ring->tx_lock); 1022 mutex_destroy(&tx_ring->recycle_lock); 1023 mutex_destroy(&tx_ring->tcb_head_lock); 1024 mutex_destroy(&tx_ring->tcb_tail_lock); 1025 } 1026 1027 mutex_destroy(&igb->gen_lock); 1028 mutex_destroy(&igb->watchdog_lock); 1029 } 1030 1031 static int 1032 igb_resume(dev_info_t *devinfo) 1033 { 1034 igb_t *igb; 1035 1036 igb = (igb_t *)ddi_get_driver_private(devinfo); 1037 if (igb == NULL) 1038 return (DDI_FAILURE); 1039 1040 mutex_enter(&igb->gen_lock); 1041 1042 if (igb->igb_state & IGB_STARTED) { 1043 if (igb_start(igb) != IGB_SUCCESS) { 1044 mutex_exit(&igb->gen_lock); 1045 return (DDI_FAILURE); 1046 } 1047 1048 /* 1049 * Enable and start the watchdog timer 1050 */ 1051 igb_enable_watchdog_timer(igb); 1052 } 1053 1054 igb->igb_state &= ~IGB_SUSPENDED; 1055 1056 mutex_exit(&igb->gen_lock); 1057 1058 return (DDI_SUCCESS); 1059 } 1060 1061 static int 1062 igb_suspend(dev_info_t *devinfo) 1063 { 1064 igb_t *igb; 1065 1066 igb = (igb_t *)ddi_get_driver_private(devinfo); 1067 if (igb == NULL) 1068 return (DDI_FAILURE); 1069 1070 mutex_enter(&igb->gen_lock); 1071 1072 igb->igb_state |= IGB_SUSPENDED; 1073 1074 if (!(igb->igb_state & IGB_STARTED)) { 1075 mutex_exit(&igb->gen_lock); 1076 return (DDI_SUCCESS); 1077 } 1078 1079 igb_stop(igb); 1080 1081 mutex_exit(&igb->gen_lock); 1082 1083 /* 1084 * Disable and stop the watchdog timer 1085 */ 1086 igb_disable_watchdog_timer(igb); 1087 1088 return (DDI_SUCCESS); 1089 } 1090 1091 static int 1092 igb_init(igb_t *igb) 1093 { 1094 int i; 1095 1096 mutex_enter(&igb->gen_lock); 1097 1098 /* 1099 * Initilize the adapter 1100 */ 1101 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1102 mutex_exit(&igb->gen_lock); 1103 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1104 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1105 return (IGB_FAILURE); 1106 } 1107 1108 /* 1109 * Setup the rx/tx rings 1110 */ 1111 for (i = 0; i < igb->num_rx_rings; i++) 1112 mutex_enter(&igb->rx_rings[i].rx_lock); 1113 for (i = 0; i < igb->num_tx_rings; i++) 1114 mutex_enter(&igb->tx_rings[i].tx_lock); 1115 1116 igb_setup_rings(igb); 1117 1118 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1119 mutex_exit(&igb->tx_rings[i].tx_lock); 1120 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1121 mutex_exit(&igb->rx_rings[i].rx_lock); 1122 1123 mutex_exit(&igb->gen_lock); 1124 1125 return (IGB_SUCCESS); 1126 } 1127 1128 /* 1129 * igb_init_mac_address - Initialize the default MAC address 1130 * 1131 * On success, the MAC address is entered in the igb->hw.mac.addr 1132 * and hw->mac.perm_addr fields and the adapter's RAR(0) receive 1133 * address register. 1134 * 1135 * Important side effects: 1136 * 1. adapter is reset - this is required to put it in a known state. 1137 * 2. all of non-volatile memory (NVM) is read & checksummed - NVM is where 1138 * MAC address and all default settings are stored, so a valid checksum 1139 * is required. 1140 */ 1141 static int 1142 igb_init_mac_address(igb_t *igb) 1143 { 1144 struct e1000_hw *hw = &igb->hw; 1145 1146 ASSERT(mutex_owned(&igb->gen_lock)); 1147 1148 /* 1149 * Reset chipset to put the hardware in a known state 1150 * before we try to get MAC address from NVM. 1151 */ 1152 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1153 igb_error(igb, "Adapter reset failed."); 1154 goto init_mac_fail; 1155 } 1156 1157 /* 1158 * NVM validation 1159 */ 1160 if (e1000_validate_nvm_checksum(hw) < 0) { 1161 /* 1162 * Some PCI-E parts fail the first check due to 1163 * the link being in sleep state. Call it again, 1164 * if it fails a second time its a real issue. 1165 */ 1166 if (e1000_validate_nvm_checksum(hw) < 0) { 1167 igb_error(igb, 1168 "Invalid NVM checksum. Please contact " 1169 "the vendor to update the NVM."); 1170 goto init_mac_fail; 1171 } 1172 } 1173 1174 /* 1175 * Get the mac address 1176 * This function should handle SPARC case correctly. 1177 */ 1178 if (!igb_find_mac_address(igb)) { 1179 igb_error(igb, "Failed to get the mac address"); 1180 goto init_mac_fail; 1181 } 1182 1183 /* Validate mac address */ 1184 if (!is_valid_mac_addr(hw->mac.addr)) { 1185 igb_error(igb, "Invalid mac address"); 1186 goto init_mac_fail; 1187 } 1188 1189 return (IGB_SUCCESS); 1190 1191 init_mac_fail: 1192 return (IGB_FAILURE); 1193 } 1194 1195 /* 1196 * igb_init_adapter - Initialize the adapter 1197 */ 1198 static int 1199 igb_init_adapter(igb_t *igb) 1200 { 1201 struct e1000_hw *hw = &igb->hw; 1202 uint32_t pba; 1203 uint32_t high_water; 1204 int i; 1205 1206 ASSERT(mutex_owned(&igb->gen_lock)); 1207 1208 /* 1209 * In order to obtain the default MAC address, this will reset the 1210 * adapter and validate the NVM that the address and many other 1211 * default settings come from. 1212 */ 1213 if (igb_init_mac_address(igb) != IGB_SUCCESS) { 1214 igb_error(igb, "Failed to initialize MAC address"); 1215 goto init_adapter_fail; 1216 } 1217 1218 /* 1219 * Setup flow control 1220 * 1221 * These parameters set thresholds for the adapter's generation(Tx) 1222 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1223 * settings. Flow control is enabled or disabled in the configuration 1224 * file. 1225 * High-water mark is set down from the top of the rx fifo (not 1226 * sensitive to max_frame_size) and low-water is set just below 1227 * high-water mark. 1228 * The high water mark must be low enough to fit one full frame above 1229 * it in the rx FIFO. Should be the lower of: 1230 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full 1231 * frame. 1232 */ 1233 /* 1234 * The default setting of PBA is correct for 82575 and other supported 1235 * adapters do not have the E1000_PBA register, so PBA value is only 1236 * used for calculation here and is never written to the adapter. 1237 */ 1238 if (hw->mac.type == e1000_82575) { 1239 pba = E1000_PBA_34K; 1240 } else { 1241 pba = E1000_PBA_64K; 1242 } 1243 1244 high_water = min(((pba << 10) * 9 / 10), 1245 ((pba << 10) - igb->max_frame_size)); 1246 1247 if (hw->mac.type == e1000_82575) { 1248 /* 8-byte granularity */ 1249 hw->fc.high_water = high_water & 0xFFF8; 1250 hw->fc.low_water = hw->fc.high_water - 8; 1251 } else { 1252 /* 16-byte granularity */ 1253 hw->fc.high_water = high_water & 0xFFF0; 1254 hw->fc.low_water = hw->fc.high_water - 16; 1255 } 1256 1257 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1258 hw->fc.send_xon = B_TRUE; 1259 1260 e1000_validate_mdi_setting(hw); 1261 1262 /* 1263 * Reset the chipset hardware the second time to put PBA settings 1264 * into effect. 1265 */ 1266 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1267 igb_error(igb, "Second reset failed"); 1268 goto init_adapter_fail; 1269 } 1270 1271 /* 1272 * Don't wait for auto-negotiation to complete 1273 */ 1274 hw->phy.autoneg_wait_to_complete = B_FALSE; 1275 1276 /* 1277 * Copper options 1278 */ 1279 if (hw->phy.media_type == e1000_media_type_copper) { 1280 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1281 hw->phy.disable_polarity_correction = B_FALSE; 1282 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 1283 } 1284 1285 /* 1286 * Initialize link settings 1287 */ 1288 (void) igb_setup_link(igb, B_FALSE); 1289 1290 /* 1291 * Configure/Initialize hardware 1292 */ 1293 if (e1000_init_hw(hw) != E1000_SUCCESS) { 1294 igb_error(igb, "Failed to initialize hardware"); 1295 goto init_adapter_fail; 1296 } 1297 1298 /* 1299 * Disable wakeup control by default 1300 */ 1301 E1000_WRITE_REG(hw, E1000_WUC, 0); 1302 1303 /* 1304 * Record phy info in hw struct 1305 */ 1306 (void) e1000_get_phy_info(hw); 1307 1308 /* 1309 * Make sure driver has control 1310 */ 1311 igb_get_driver_control(hw); 1312 1313 /* 1314 * Restore LED settings to the default from EEPROM 1315 * to meet the standard for Sun platforms. 1316 */ 1317 (void) e1000_cleanup_led(hw); 1318 1319 /* 1320 * Setup MSI-X interrupts 1321 */ 1322 if (igb->intr_type == DDI_INTR_TYPE_MSIX) 1323 igb->capab->setup_msix(igb); 1324 1325 /* 1326 * Initialize unicast addresses. 1327 */ 1328 igb_init_unicst(igb); 1329 1330 /* 1331 * Setup and initialize the mctable structures. 1332 */ 1333 igb_setup_multicst(igb); 1334 1335 /* 1336 * Set interrupt throttling rate 1337 */ 1338 for (i = 0; i < igb->intr_cnt; i++) 1339 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]); 1340 1341 /* 1342 * Save the state of the phy 1343 */ 1344 igb_get_phy_state(igb); 1345 1346 return (IGB_SUCCESS); 1347 1348 init_adapter_fail: 1349 /* 1350 * Reset PHY if possible 1351 */ 1352 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1353 (void) e1000_phy_hw_reset(hw); 1354 1355 return (IGB_FAILURE); 1356 } 1357 1358 /* 1359 * igb_stop_adapter - Stop the adapter 1360 */ 1361 static void 1362 igb_stop_adapter(igb_t *igb) 1363 { 1364 struct e1000_hw *hw = &igb->hw; 1365 1366 ASSERT(mutex_owned(&igb->gen_lock)); 1367 1368 /* Tell firmware driver is no longer in control */ 1369 igb_release_driver_control(hw); 1370 1371 /* 1372 * Reset the chipset 1373 */ 1374 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1375 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1376 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1377 } 1378 1379 /* 1380 * e1000_phy_hw_reset is not needed here, MAC reset above is sufficient 1381 */ 1382 } 1383 1384 /* 1385 * igb_reset - Reset the chipset and restart the driver. 1386 * 1387 * It involves stopping and re-starting the chipset, 1388 * and re-configuring the rx/tx rings. 1389 */ 1390 static int 1391 igb_reset(igb_t *igb) 1392 { 1393 int i; 1394 1395 mutex_enter(&igb->gen_lock); 1396 1397 ASSERT(igb->igb_state & IGB_STARTED); 1398 1399 /* 1400 * Disable the adapter interrupts to stop any rx/tx activities 1401 * before draining pending data and resetting hardware. 1402 */ 1403 igb_disable_adapter_interrupts(igb); 1404 1405 /* 1406 * Drain the pending transmit packets 1407 */ 1408 (void) igb_tx_drain(igb); 1409 1410 for (i = 0; i < igb->num_rx_rings; i++) 1411 mutex_enter(&igb->rx_rings[i].rx_lock); 1412 for (i = 0; i < igb->num_tx_rings; i++) 1413 mutex_enter(&igb->tx_rings[i].tx_lock); 1414 1415 /* 1416 * Stop the adapter 1417 */ 1418 igb_stop_adapter(igb); 1419 1420 /* 1421 * Clean the pending tx data/resources 1422 */ 1423 igb_tx_clean(igb); 1424 1425 /* 1426 * Start the adapter 1427 */ 1428 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1429 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1430 goto reset_failure; 1431 } 1432 1433 /* 1434 * Setup the rx/tx rings 1435 */ 1436 igb_setup_rings(igb); 1437 1438 /* 1439 * Enable adapter interrupts 1440 * The interrupts must be enabled after the driver state is START 1441 */ 1442 igb->capab->enable_intr(igb); 1443 1444 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1445 goto reset_failure; 1446 1447 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1448 goto reset_failure; 1449 1450 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1451 mutex_exit(&igb->tx_rings[i].tx_lock); 1452 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1453 mutex_exit(&igb->rx_rings[i].rx_lock); 1454 1455 mutex_exit(&igb->gen_lock); 1456 1457 return (IGB_SUCCESS); 1458 1459 reset_failure: 1460 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1461 mutex_exit(&igb->tx_rings[i].tx_lock); 1462 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1463 mutex_exit(&igb->rx_rings[i].rx_lock); 1464 1465 mutex_exit(&igb->gen_lock); 1466 1467 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1468 1469 return (IGB_FAILURE); 1470 } 1471 1472 /* 1473 * igb_tx_clean - Clean the pending transmit packets and DMA resources 1474 */ 1475 static void 1476 igb_tx_clean(igb_t *igb) 1477 { 1478 igb_tx_ring_t *tx_ring; 1479 tx_control_block_t *tcb; 1480 link_list_t pending_list; 1481 uint32_t desc_num; 1482 int i, j; 1483 1484 LINK_LIST_INIT(&pending_list); 1485 1486 for (i = 0; i < igb->num_tx_rings; i++) { 1487 tx_ring = &igb->tx_rings[i]; 1488 1489 mutex_enter(&tx_ring->recycle_lock); 1490 1491 /* 1492 * Clean the pending tx data - the pending packets in the 1493 * work_list that have no chances to be transmitted again. 1494 * 1495 * We must ensure the chipset is stopped or the link is down 1496 * before cleaning the transmit packets. 1497 */ 1498 desc_num = 0; 1499 for (j = 0; j < tx_ring->ring_size; j++) { 1500 tcb = tx_ring->work_list[j]; 1501 if (tcb != NULL) { 1502 desc_num += tcb->desc_num; 1503 1504 tx_ring->work_list[j] = NULL; 1505 1506 igb_free_tcb(tcb); 1507 1508 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1509 } 1510 } 1511 1512 if (desc_num > 0) { 1513 atomic_add_32(&tx_ring->tbd_free, desc_num); 1514 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1515 1516 /* 1517 * Reset the head and tail pointers of the tbd ring; 1518 * Reset the head write-back if it is enabled. 1519 */ 1520 tx_ring->tbd_head = 0; 1521 tx_ring->tbd_tail = 0; 1522 if (igb->tx_head_wb_enable) 1523 *tx_ring->tbd_head_wb = 0; 1524 1525 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0); 1526 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0); 1527 } 1528 1529 mutex_exit(&tx_ring->recycle_lock); 1530 1531 /* 1532 * Add the tx control blocks in the pending list to 1533 * the free list. 1534 */ 1535 igb_put_free_list(tx_ring, &pending_list); 1536 } 1537 } 1538 1539 /* 1540 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted 1541 */ 1542 static boolean_t 1543 igb_tx_drain(igb_t *igb) 1544 { 1545 igb_tx_ring_t *tx_ring; 1546 boolean_t done; 1547 int i, j; 1548 1549 /* 1550 * Wait for a specific time to allow pending tx packets 1551 * to be transmitted. 1552 * 1553 * Check the counter tbd_free to see if transmission is done. 1554 * No lock protection is needed here. 1555 * 1556 * Return B_TRUE if all pending packets have been transmitted; 1557 * Otherwise return B_FALSE; 1558 */ 1559 for (i = 0; i < TX_DRAIN_TIME; i++) { 1560 1561 done = B_TRUE; 1562 for (j = 0; j < igb->num_tx_rings; j++) { 1563 tx_ring = &igb->tx_rings[j]; 1564 done = done && 1565 (tx_ring->tbd_free == tx_ring->ring_size); 1566 } 1567 1568 if (done) 1569 break; 1570 1571 msec_delay(1); 1572 } 1573 1574 return (done); 1575 } 1576 1577 /* 1578 * igb_rx_drain - Wait for all rx buffers to be released by upper layer 1579 */ 1580 static boolean_t 1581 igb_rx_drain(igb_t *igb) 1582 { 1583 igb_rx_ring_t *rx_ring; 1584 boolean_t done; 1585 int i, j; 1586 1587 /* 1588 * Polling the rx free list to check if those rx buffers held by 1589 * the upper layer are released. 1590 * 1591 * Check the counter rcb_free to see if all pending buffers are 1592 * released. No lock protection is needed here. 1593 * 1594 * Return B_TRUE if all pending buffers have been released; 1595 * Otherwise return B_FALSE; 1596 */ 1597 for (i = 0; i < RX_DRAIN_TIME; i++) { 1598 1599 done = B_TRUE; 1600 for (j = 0; j < igb->num_rx_rings; j++) { 1601 rx_ring = &igb->rx_rings[j]; 1602 done = done && 1603 (rx_ring->rcb_free == rx_ring->free_list_size); 1604 } 1605 1606 if (done) 1607 break; 1608 1609 msec_delay(1); 1610 } 1611 1612 return (done); 1613 } 1614 1615 /* 1616 * igb_start - Start the driver/chipset 1617 */ 1618 int 1619 igb_start(igb_t *igb) 1620 { 1621 int i; 1622 1623 ASSERT(mutex_owned(&igb->gen_lock)); 1624 1625 for (i = 0; i < igb->num_rx_rings; i++) 1626 mutex_enter(&igb->rx_rings[i].rx_lock); 1627 for (i = 0; i < igb->num_tx_rings; i++) 1628 mutex_enter(&igb->tx_rings[i].tx_lock); 1629 1630 /* 1631 * Start the adapter 1632 */ 1633 if ((igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) == 0) { 1634 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1635 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1636 goto start_failure; 1637 } 1638 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 1639 1640 /* 1641 * Setup the rx/tx rings 1642 */ 1643 igb_setup_rings(igb); 1644 } 1645 1646 /* 1647 * Enable adapter interrupts 1648 * The interrupts must be enabled after the driver state is START 1649 */ 1650 igb->capab->enable_intr(igb); 1651 1652 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1653 goto start_failure; 1654 1655 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1656 goto start_failure; 1657 1658 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1659 mutex_exit(&igb->tx_rings[i].tx_lock); 1660 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1661 mutex_exit(&igb->rx_rings[i].rx_lock); 1662 1663 return (IGB_SUCCESS); 1664 1665 start_failure: 1666 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1667 mutex_exit(&igb->tx_rings[i].tx_lock); 1668 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1669 mutex_exit(&igb->rx_rings[i].rx_lock); 1670 1671 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1672 1673 return (IGB_FAILURE); 1674 } 1675 1676 /* 1677 * igb_stop - Stop the driver/chipset 1678 */ 1679 void 1680 igb_stop(igb_t *igb) 1681 { 1682 int i; 1683 1684 ASSERT(mutex_owned(&igb->gen_lock)); 1685 1686 igb->attach_progress &= ~ATTACH_PROGRESS_INIT_ADAPTER; 1687 1688 /* 1689 * Disable the adapter interrupts 1690 */ 1691 igb_disable_adapter_interrupts(igb); 1692 1693 /* 1694 * Drain the pending tx packets 1695 */ 1696 (void) igb_tx_drain(igb); 1697 1698 for (i = 0; i < igb->num_rx_rings; i++) 1699 mutex_enter(&igb->rx_rings[i].rx_lock); 1700 for (i = 0; i < igb->num_tx_rings; i++) 1701 mutex_enter(&igb->tx_rings[i].tx_lock); 1702 1703 /* 1704 * Stop the adapter 1705 */ 1706 igb_stop_adapter(igb); 1707 1708 /* 1709 * Clean the pending tx data/resources 1710 */ 1711 igb_tx_clean(igb); 1712 1713 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1714 mutex_exit(&igb->tx_rings[i].tx_lock); 1715 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1716 mutex_exit(&igb->rx_rings[i].rx_lock); 1717 1718 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1719 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1720 } 1721 1722 /* 1723 * igb_alloc_rings - Allocate memory space for rx/tx rings 1724 */ 1725 static int 1726 igb_alloc_rings(igb_t *igb) 1727 { 1728 /* 1729 * Allocate memory space for rx rings 1730 */ 1731 igb->rx_rings = kmem_zalloc( 1732 sizeof (igb_rx_ring_t) * igb->num_rx_rings, 1733 KM_NOSLEEP); 1734 1735 if (igb->rx_rings == NULL) { 1736 return (IGB_FAILURE); 1737 } 1738 1739 /* 1740 * Allocate memory space for tx rings 1741 */ 1742 igb->tx_rings = kmem_zalloc( 1743 sizeof (igb_tx_ring_t) * igb->num_tx_rings, 1744 KM_NOSLEEP); 1745 1746 if (igb->tx_rings == NULL) { 1747 kmem_free(igb->rx_rings, 1748 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1749 igb->rx_rings = NULL; 1750 return (IGB_FAILURE); 1751 } 1752 1753 /* 1754 * Allocate memory space for rx ring groups 1755 */ 1756 igb->rx_groups = kmem_zalloc( 1757 sizeof (igb_rx_group_t) * igb->num_rx_groups, 1758 KM_NOSLEEP); 1759 1760 if (igb->rx_groups == NULL) { 1761 kmem_free(igb->rx_rings, 1762 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1763 kmem_free(igb->tx_rings, 1764 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1765 igb->rx_rings = NULL; 1766 igb->tx_rings = NULL; 1767 return (IGB_FAILURE); 1768 } 1769 1770 return (IGB_SUCCESS); 1771 } 1772 1773 /* 1774 * igb_free_rings - Free the memory space of rx/tx rings. 1775 */ 1776 static void 1777 igb_free_rings(igb_t *igb) 1778 { 1779 if (igb->rx_rings != NULL) { 1780 kmem_free(igb->rx_rings, 1781 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1782 igb->rx_rings = NULL; 1783 } 1784 1785 if (igb->tx_rings != NULL) { 1786 kmem_free(igb->tx_rings, 1787 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1788 igb->tx_rings = NULL; 1789 } 1790 1791 if (igb->rx_groups != NULL) { 1792 kmem_free(igb->rx_groups, 1793 sizeof (igb_rx_group_t) * igb->num_rx_groups); 1794 igb->rx_groups = NULL; 1795 } 1796 } 1797 1798 /* 1799 * igb_setup_rings - Setup rx/tx rings 1800 */ 1801 static void 1802 igb_setup_rings(igb_t *igb) 1803 { 1804 /* 1805 * Setup the rx/tx rings, including the following: 1806 * 1807 * 1. Setup the descriptor ring and the control block buffers; 1808 * 2. Initialize necessary registers for receive/transmit; 1809 * 3. Initialize software pointers/parameters for receive/transmit; 1810 */ 1811 igb_setup_rx(igb); 1812 1813 igb_setup_tx(igb); 1814 1815 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1816 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1817 } 1818 1819 static void 1820 igb_setup_rx_ring(igb_rx_ring_t *rx_ring) 1821 { 1822 igb_t *igb = rx_ring->igb; 1823 struct e1000_hw *hw = &igb->hw; 1824 rx_control_block_t *rcb; 1825 union e1000_adv_rx_desc *rbd; 1826 uint32_t size; 1827 uint32_t buf_low; 1828 uint32_t buf_high; 1829 uint32_t rxdctl; 1830 int i; 1831 1832 ASSERT(mutex_owned(&rx_ring->rx_lock)); 1833 ASSERT(mutex_owned(&igb->gen_lock)); 1834 1835 /* 1836 * Initialize descriptor ring with buffer addresses 1837 */ 1838 for (i = 0; i < igb->rx_ring_size; i++) { 1839 rcb = rx_ring->work_list[i]; 1840 rbd = &rx_ring->rbd_ring[i]; 1841 1842 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 1843 rbd->read.hdr_addr = NULL; 1844 } 1845 1846 /* 1847 * Initialize the base address registers 1848 */ 1849 buf_low = (uint32_t)rx_ring->rbd_area.dma_address; 1850 buf_high = (uint32_t)(rx_ring->rbd_area.dma_address >> 32); 1851 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high); 1852 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low); 1853 1854 /* 1855 * Initialize the length register 1856 */ 1857 size = rx_ring->ring_size * sizeof (union e1000_adv_rx_desc); 1858 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size); 1859 1860 /* 1861 * Initialize buffer size & descriptor type 1862 */ 1863 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index), 1864 ((igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) | 1865 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF)); 1866 1867 /* 1868 * Setup the Receive Descriptor Control Register (RXDCTL) 1869 */ 1870 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index)); 1871 rxdctl &= igb->capab->rxdctl_mask; 1872 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 1873 rxdctl |= 16; /* pthresh */ 1874 rxdctl |= 8 << 8; /* hthresh */ 1875 rxdctl |= 1 << 16; /* wthresh */ 1876 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), rxdctl); 1877 1878 rx_ring->rbd_next = 0; 1879 1880 /* 1881 * Note: Considering the case that the chipset is being reset 1882 * and there are still some buffers held by the upper layer, 1883 * we should not reset the values of rcb_head, rcb_tail and 1884 * rcb_free; 1885 */ 1886 if (igb->igb_state == IGB_UNKNOWN) { 1887 rx_ring->rcb_head = 0; 1888 rx_ring->rcb_tail = 0; 1889 rx_ring->rcb_free = rx_ring->free_list_size; 1890 } 1891 } 1892 1893 static void 1894 igb_setup_rx(igb_t *igb) 1895 { 1896 igb_rx_ring_t *rx_ring; 1897 igb_rx_group_t *rx_group; 1898 struct e1000_hw *hw = &igb->hw; 1899 uint32_t rctl, rxcsum; 1900 uint32_t ring_per_group; 1901 int i; 1902 1903 /* 1904 * Setup the Receive Control Register (RCTL), and enable the 1905 * receiver. The initial configuration is to: enable the receiver, 1906 * accept broadcasts, discard bad packets, accept long packets, 1907 * disable VLAN filter checking, and set receive buffer size to 1908 * 2k. For 82575, also set the receive descriptor minimum 1909 * threshold size to 1/2 the ring. 1910 */ 1911 rctl = E1000_READ_REG(hw, E1000_RCTL); 1912 1913 /* 1914 * Clear the field used for wakeup control. This driver doesn't do 1915 * wakeup but leave this here for completeness. 1916 */ 1917 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 1918 1919 switch (hw->mac.type) { 1920 case e1000_82575: 1921 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */ 1922 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 1923 E1000_RCTL_LPE | /* Large Packet Enable */ 1924 /* Multicast filter offset */ 1925 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 1926 E1000_RCTL_RDMTS_HALF | /* rx descriptor threshold */ 1927 E1000_RCTL_SECRC); /* Strip Ethernet CRC */ 1928 break; 1929 1930 case e1000_82576: 1931 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */ 1932 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 1933 E1000_RCTL_LPE | /* Large Packet Enable */ 1934 /* Multicast filter offset */ 1935 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 1936 E1000_RCTL_SECRC); /* Strip Ethernet CRC */ 1937 break; 1938 1939 default: 1940 igb_log(igb, "unsupported MAC type: %d", hw->mac.type); 1941 return; /* should never come here; this will cause rx failure */ 1942 } 1943 1944 for (i = 0; i < igb->num_rx_groups; i++) { 1945 rx_group = &igb->rx_groups[i]; 1946 rx_group->index = i; 1947 rx_group->igb = igb; 1948 } 1949 1950 /* 1951 * Set up all rx descriptor rings - must be called before receive unit 1952 * enabled. 1953 */ 1954 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 1955 for (i = 0; i < igb->num_rx_rings; i++) { 1956 rx_ring = &igb->rx_rings[i]; 1957 igb_setup_rx_ring(rx_ring); 1958 1959 /* 1960 * Map a ring to a group by assigning a group index 1961 */ 1962 rx_ring->group_index = i / ring_per_group; 1963 } 1964 1965 /* 1966 * Setup the Rx Long Packet Max Length register 1967 */ 1968 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size); 1969 1970 /* 1971 * Hardware checksum settings 1972 */ 1973 if (igb->rx_hcksum_enable) { 1974 rxcsum = 1975 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */ 1976 E1000_RXCSUM_IPOFL; /* IP checksum */ 1977 1978 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 1979 } 1980 1981 /* 1982 * Setup classify and RSS for multiple receive queues 1983 */ 1984 switch (igb->vmdq_mode) { 1985 case E1000_VMDQ_OFF: 1986 /* 1987 * One ring group, only RSS is needed when more than 1988 * one ring enabled. 1989 */ 1990 if (igb->num_rx_rings > 1) 1991 igb_setup_rss(igb); 1992 break; 1993 case E1000_VMDQ_MAC: 1994 /* 1995 * Multiple groups, each group has one ring, 1996 * only the MAC classification is needed. 1997 */ 1998 igb_setup_mac_classify(igb); 1999 break; 2000 case E1000_VMDQ_MAC_RSS: 2001 /* 2002 * Multiple groups and multiple rings, both 2003 * MAC classification and RSS are needed. 2004 */ 2005 igb_setup_mac_rss_classify(igb); 2006 break; 2007 } 2008 2009 /* 2010 * Enable the receive unit - must be done after all 2011 * the rx setup above. 2012 */ 2013 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2014 2015 /* 2016 * Initialize all adapter ring head & tail pointers - must 2017 * be done after receive unit is enabled 2018 */ 2019 for (i = 0; i < igb->num_rx_rings; i++) { 2020 rx_ring = &igb->rx_rings[i]; 2021 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 2022 E1000_WRITE_REG(hw, E1000_RDT(i), rx_ring->ring_size - 1); 2023 } 2024 2025 /* 2026 * 82575 with manageability enabled needs a special flush to make 2027 * sure the fifos start clean. 2028 */ 2029 if ((hw->mac.type == e1000_82575) && 2030 (E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) { 2031 e1000_rx_fifo_flush_82575(hw); 2032 } 2033 } 2034 2035 static void 2036 igb_setup_tx_ring(igb_tx_ring_t *tx_ring) 2037 { 2038 igb_t *igb = tx_ring->igb; 2039 struct e1000_hw *hw = &igb->hw; 2040 uint32_t size; 2041 uint32_t buf_low; 2042 uint32_t buf_high; 2043 uint32_t reg_val; 2044 2045 ASSERT(mutex_owned(&tx_ring->tx_lock)); 2046 ASSERT(mutex_owned(&igb->gen_lock)); 2047 2048 2049 /* 2050 * Initialize the length register 2051 */ 2052 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc); 2053 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size); 2054 2055 /* 2056 * Initialize the base address registers 2057 */ 2058 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 2059 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 2060 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low); 2061 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high); 2062 2063 /* 2064 * Setup head & tail pointers 2065 */ 2066 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0); 2067 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0); 2068 2069 /* 2070 * Setup head write-back 2071 */ 2072 if (igb->tx_head_wb_enable) { 2073 /* 2074 * The memory of the head write-back is allocated using 2075 * the extra tbd beyond the tail of the tbd ring. 2076 */ 2077 tx_ring->tbd_head_wb = (uint32_t *) 2078 ((uintptr_t)tx_ring->tbd_area.address + size); 2079 *tx_ring->tbd_head_wb = 0; 2080 2081 buf_low = (uint32_t) 2082 (tx_ring->tbd_area.dma_address + size); 2083 buf_high = (uint32_t) 2084 ((tx_ring->tbd_area.dma_address + size) >> 32); 2085 2086 /* Set the head write-back enable bit */ 2087 buf_low |= E1000_TX_HEAD_WB_ENABLE; 2088 2089 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low); 2090 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high); 2091 2092 /* 2093 * Turn off relaxed ordering for head write back or it will 2094 * cause problems with the tx recycling 2095 */ 2096 reg_val = E1000_READ_REG(hw, 2097 E1000_DCA_TXCTRL(tx_ring->index)); 2098 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; 2099 E1000_WRITE_REG(hw, 2100 E1000_DCA_TXCTRL(tx_ring->index), reg_val); 2101 } else { 2102 tx_ring->tbd_head_wb = NULL; 2103 } 2104 2105 tx_ring->tbd_head = 0; 2106 tx_ring->tbd_tail = 0; 2107 tx_ring->tbd_free = tx_ring->ring_size; 2108 2109 /* 2110 * Note: for the case that the chipset is being reset, we should not 2111 * reset the values of tcb_head, tcb_tail. And considering there might 2112 * still be some packets kept in the pending_list, we should not assert 2113 * (tcb_free == free_list_size) here. 2114 */ 2115 if (igb->igb_state == IGB_UNKNOWN) { 2116 tx_ring->tcb_head = 0; 2117 tx_ring->tcb_tail = 0; 2118 tx_ring->tcb_free = tx_ring->free_list_size; 2119 } 2120 2121 /* 2122 * Enable TXDCTL per queue 2123 */ 2124 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index)); 2125 reg_val |= E1000_TXDCTL_QUEUE_ENABLE; 2126 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val); 2127 2128 /* 2129 * Initialize hardware checksum offload settings 2130 */ 2131 bzero(&tx_ring->tx_context, sizeof (tx_context_t)); 2132 } 2133 2134 static void 2135 igb_setup_tx(igb_t *igb) 2136 { 2137 igb_tx_ring_t *tx_ring; 2138 struct e1000_hw *hw = &igb->hw; 2139 uint32_t reg_val; 2140 int i; 2141 2142 for (i = 0; i < igb->num_tx_rings; i++) { 2143 tx_ring = &igb->tx_rings[i]; 2144 igb_setup_tx_ring(tx_ring); 2145 } 2146 2147 /* 2148 * Setup the Transmit Control Register (TCTL) 2149 */ 2150 reg_val = E1000_READ_REG(hw, E1000_TCTL); 2151 reg_val &= ~E1000_TCTL_CT; 2152 reg_val |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2153 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2154 2155 /* Enable transmits */ 2156 reg_val |= E1000_TCTL_EN; 2157 2158 E1000_WRITE_REG(hw, E1000_TCTL, reg_val); 2159 } 2160 2161 /* 2162 * igb_setup_rss - Setup receive-side scaling feature 2163 */ 2164 static void 2165 igb_setup_rss(igb_t *igb) 2166 { 2167 struct e1000_hw *hw = &igb->hw; 2168 uint32_t i, mrqc, rxcsum; 2169 int shift = 0; 2170 uint32_t random; 2171 union e1000_reta { 2172 uint32_t dword; 2173 uint8_t bytes[4]; 2174 } reta; 2175 2176 /* Setup the Redirection Table */ 2177 if (hw->mac.type == e1000_82576) { 2178 shift = 0; 2179 } else if (hw->mac.type == e1000_82575) { 2180 shift = 6; 2181 } 2182 for (i = 0; i < (32 * 4); i++) { 2183 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift; 2184 if ((i & 3) == 3) { 2185 E1000_WRITE_REG(hw, 2186 (E1000_RETA(0) + (i & ~3)), reta.dword); 2187 } 2188 } 2189 2190 /* Fill out hash function seeds */ 2191 for (i = 0; i < 10; i++) { 2192 (void) random_get_pseudo_bytes((uint8_t *)&random, 2193 sizeof (uint32_t)); 2194 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2195 } 2196 2197 /* Setup the Multiple Receive Queue Control register */ 2198 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 2199 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2200 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2201 E1000_MRQC_RSS_FIELD_IPV6 | 2202 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2203 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2204 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2205 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2206 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2207 2208 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2209 2210 /* 2211 * Disable Packet Checksum to enable RSS for multiple receive queues. 2212 * 2213 * The Packet Checksum is not ethernet CRC. It is another kind of 2214 * checksum offloading provided by the 82575 chipset besides the IP 2215 * header checksum offloading and the TCP/UDP checksum offloading. 2216 * The Packet Checksum is by default computed over the entire packet 2217 * from the first byte of the DA through the last byte of the CRC, 2218 * including the Ethernet and IP headers. 2219 * 2220 * It is a hardware limitation that Packet Checksum is mutually 2221 * exclusive with RSS. 2222 */ 2223 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2224 rxcsum |= E1000_RXCSUM_PCSD; 2225 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2226 } 2227 2228 /* 2229 * igb_setup_mac_rss_classify - Setup MAC classification and rss 2230 */ 2231 static void 2232 igb_setup_mac_rss_classify(igb_t *igb) 2233 { 2234 struct e1000_hw *hw = &igb->hw; 2235 uint32_t i, mrqc, vmdctl, rxcsum; 2236 uint32_t ring_per_group; 2237 int shift_group0, shift_group1; 2238 uint32_t random; 2239 union e1000_reta { 2240 uint32_t dword; 2241 uint8_t bytes[4]; 2242 } reta; 2243 2244 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2245 2246 /* Setup the Redirection Table, it is shared between two groups */ 2247 shift_group0 = 2; 2248 shift_group1 = 6; 2249 for (i = 0; i < (32 * 4); i++) { 2250 reta.bytes[i & 3] = ((i % ring_per_group) << shift_group0) | 2251 ((ring_per_group + (i % ring_per_group)) << shift_group1); 2252 if ((i & 3) == 3) { 2253 E1000_WRITE_REG(hw, 2254 (E1000_RETA(0) + (i & ~3)), reta.dword); 2255 } 2256 } 2257 2258 /* Fill out hash function seeds */ 2259 for (i = 0; i < 10; i++) { 2260 (void) random_get_pseudo_bytes((uint8_t *)&random, 2261 sizeof (uint32_t)); 2262 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2263 } 2264 2265 /* 2266 * Setup the Multiple Receive Queue Control register, 2267 * enable VMDq based on packet destination MAC address and RSS. 2268 */ 2269 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP; 2270 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2271 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2272 E1000_MRQC_RSS_FIELD_IPV6 | 2273 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2274 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2275 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2276 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2277 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2278 2279 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2280 2281 2282 /* Define the default group and default queues */ 2283 vmdctl = E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE; 2284 E1000_WRITE_REG(hw, E1000_VT_CTL, vmdctl); 2285 2286 /* 2287 * Disable Packet Checksum to enable RSS for multiple receive queues. 2288 * 2289 * The Packet Checksum is not ethernet CRC. It is another kind of 2290 * checksum offloading provided by the 82575 chipset besides the IP 2291 * header checksum offloading and the TCP/UDP checksum offloading. 2292 * The Packet Checksum is by default computed over the entire packet 2293 * from the first byte of the DA through the last byte of the CRC, 2294 * including the Ethernet and IP headers. 2295 * 2296 * It is a hardware limitation that Packet Checksum is mutually 2297 * exclusive with RSS. 2298 */ 2299 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2300 rxcsum |= E1000_RXCSUM_PCSD; 2301 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2302 } 2303 2304 /* 2305 * igb_setup_mac_classify - Setup MAC classification feature 2306 */ 2307 static void 2308 igb_setup_mac_classify(igb_t *igb) 2309 { 2310 struct e1000_hw *hw = &igb->hw; 2311 uint32_t mrqc, rxcsum; 2312 2313 /* 2314 * Setup the Multiple Receive Queue Control register, 2315 * enable VMDq based on packet destination MAC address. 2316 */ 2317 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_GROUP; 2318 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2319 2320 /* 2321 * Disable Packet Checksum to enable RSS for multiple receive queues. 2322 * 2323 * The Packet Checksum is not ethernet CRC. It is another kind of 2324 * checksum offloading provided by the 82575 chipset besides the IP 2325 * header checksum offloading and the TCP/UDP checksum offloading. 2326 * The Packet Checksum is by default computed over the entire packet 2327 * from the first byte of the DA through the last byte of the CRC, 2328 * including the Ethernet and IP headers. 2329 * 2330 * It is a hardware limitation that Packet Checksum is mutually 2331 * exclusive with RSS. 2332 */ 2333 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2334 rxcsum |= E1000_RXCSUM_PCSD; 2335 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2336 2337 } 2338 2339 /* 2340 * igb_init_unicst - Initialize the unicast addresses 2341 */ 2342 static void 2343 igb_init_unicst(igb_t *igb) 2344 { 2345 struct e1000_hw *hw = &igb->hw; 2346 int slot; 2347 2348 /* 2349 * Here we should consider two situations: 2350 * 2351 * 1. Chipset is initialized the first time 2352 * Initialize the multiple unicast addresses, and 2353 * save the default MAC address. 2354 * 2355 * 2. Chipset is reset 2356 * Recover the multiple unicast addresses from the 2357 * software data structure to the RAR registers. 2358 */ 2359 2360 /* 2361 * Clear the default MAC address in the RAR0 rgister, 2362 * which is loaded from EEPROM when system boot or chipreset, 2363 * this will cause the conficts with add_mac/rem_mac entry 2364 * points when VMDq is enabled. For this reason, the RAR0 2365 * must be cleared for both cases mentioned above. 2366 */ 2367 e1000_rar_clear(hw, 0); 2368 2369 if (!igb->unicst_init) { 2370 2371 /* Initialize the multiple unicast addresses */ 2372 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2373 igb->unicst_avail = igb->unicst_total; 2374 2375 for (slot = 0; slot < igb->unicst_total; slot++) 2376 igb->unicst_addr[slot].mac.set = 0; 2377 2378 igb->unicst_init = B_TRUE; 2379 } else { 2380 /* Re-configure the RAR registers */ 2381 for (slot = 0; slot < igb->unicst_total; slot++) { 2382 e1000_rar_set_vmdq(hw, igb->unicst_addr[slot].mac.addr, 2383 slot, igb->vmdq_mode, 2384 igb->unicst_addr[slot].mac.group_index); 2385 } 2386 } 2387 2388 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2389 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2390 } 2391 2392 /* 2393 * igb_unicst_find - Find the slot for the specified unicast address 2394 */ 2395 int 2396 igb_unicst_find(igb_t *igb, const uint8_t *mac_addr) 2397 { 2398 int slot; 2399 2400 ASSERT(mutex_owned(&igb->gen_lock)); 2401 2402 for (slot = 0; slot < igb->unicst_total; slot++) { 2403 if (bcmp(igb->unicst_addr[slot].mac.addr, 2404 mac_addr, ETHERADDRL) == 0) 2405 return (slot); 2406 } 2407 2408 return (-1); 2409 } 2410 2411 /* 2412 * igb_unicst_set - Set the unicast address to the specified slot 2413 */ 2414 int 2415 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr, 2416 int slot) 2417 { 2418 struct e1000_hw *hw = &igb->hw; 2419 2420 ASSERT(mutex_owned(&igb->gen_lock)); 2421 2422 /* 2423 * Save the unicast address in the software data structure 2424 */ 2425 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL); 2426 2427 /* 2428 * Set the unicast address to the RAR register 2429 */ 2430 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2431 2432 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2433 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2434 return (EIO); 2435 } 2436 2437 return (0); 2438 } 2439 2440 /* 2441 * igb_multicst_add - Add a multicst address 2442 */ 2443 int 2444 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr) 2445 { 2446 struct ether_addr *new_table; 2447 size_t new_len; 2448 size_t old_len; 2449 2450 ASSERT(mutex_owned(&igb->gen_lock)); 2451 2452 if ((multiaddr[0] & 01) == 0) { 2453 igb_error(igb, "Illegal multicast address"); 2454 return (EINVAL); 2455 } 2456 2457 if (igb->mcast_count >= igb->mcast_max_num) { 2458 igb_error(igb, "Adapter requested more than %d mcast addresses", 2459 igb->mcast_max_num); 2460 return (ENOENT); 2461 } 2462 2463 if (igb->mcast_count == igb->mcast_alloc_count) { 2464 old_len = igb->mcast_alloc_count * 2465 sizeof (struct ether_addr); 2466 new_len = (igb->mcast_alloc_count + MCAST_ALLOC_COUNT) * 2467 sizeof (struct ether_addr); 2468 2469 new_table = kmem_alloc(new_len, KM_NOSLEEP); 2470 if (new_table == NULL) { 2471 igb_error(igb, 2472 "Not enough memory to alloc mcast table"); 2473 return (ENOMEM); 2474 } 2475 2476 if (igb->mcast_table != NULL) { 2477 bcopy(igb->mcast_table, new_table, old_len); 2478 kmem_free(igb->mcast_table, old_len); 2479 } 2480 igb->mcast_alloc_count += MCAST_ALLOC_COUNT; 2481 igb->mcast_table = new_table; 2482 } 2483 2484 bcopy(multiaddr, 2485 &igb->mcast_table[igb->mcast_count], ETHERADDRL); 2486 igb->mcast_count++; 2487 2488 /* 2489 * Update the multicast table in the hardware 2490 */ 2491 igb_setup_multicst(igb); 2492 2493 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2494 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2495 return (EIO); 2496 } 2497 2498 return (0); 2499 } 2500 2501 /* 2502 * igb_multicst_remove - Remove a multicst address 2503 */ 2504 int 2505 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr) 2506 { 2507 struct ether_addr *new_table; 2508 size_t new_len; 2509 size_t old_len; 2510 int i; 2511 2512 ASSERT(mutex_owned(&igb->gen_lock)); 2513 2514 for (i = 0; i < igb->mcast_count; i++) { 2515 if (bcmp(multiaddr, &igb->mcast_table[i], 2516 ETHERADDRL) == 0) { 2517 for (i++; i < igb->mcast_count; i++) { 2518 igb->mcast_table[i - 1] = 2519 igb->mcast_table[i]; 2520 } 2521 igb->mcast_count--; 2522 break; 2523 } 2524 } 2525 2526 if ((igb->mcast_alloc_count - igb->mcast_count) > 2527 MCAST_ALLOC_COUNT) { 2528 old_len = igb->mcast_alloc_count * 2529 sizeof (struct ether_addr); 2530 new_len = (igb->mcast_alloc_count - MCAST_ALLOC_COUNT) * 2531 sizeof (struct ether_addr); 2532 2533 new_table = kmem_alloc(new_len, KM_NOSLEEP); 2534 if (new_table != NULL) { 2535 bcopy(igb->mcast_table, new_table, new_len); 2536 kmem_free(igb->mcast_table, old_len); 2537 igb->mcast_alloc_count -= MCAST_ALLOC_COUNT; 2538 igb->mcast_table = new_table; 2539 } 2540 } 2541 2542 /* 2543 * Update the multicast table in the hardware 2544 */ 2545 igb_setup_multicst(igb); 2546 2547 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2548 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2549 return (EIO); 2550 } 2551 2552 return (0); 2553 } 2554 2555 static void 2556 igb_release_multicast(igb_t *igb) 2557 { 2558 if (igb->mcast_table != NULL) { 2559 kmem_free(igb->mcast_table, 2560 igb->mcast_alloc_count * sizeof (struct ether_addr)); 2561 igb->mcast_table = NULL; 2562 } 2563 } 2564 2565 /* 2566 * igb_setup_multicast - setup multicast data structures 2567 * 2568 * This routine initializes all of the multicast related structures 2569 * and save them in the hardware registers. 2570 */ 2571 static void 2572 igb_setup_multicst(igb_t *igb) 2573 { 2574 uint8_t *mc_addr_list; 2575 uint32_t mc_addr_count; 2576 struct e1000_hw *hw = &igb->hw; 2577 2578 ASSERT(mutex_owned(&igb->gen_lock)); 2579 ASSERT(igb->mcast_count <= igb->mcast_max_num); 2580 2581 mc_addr_list = (uint8_t *)igb->mcast_table; 2582 mc_addr_count = igb->mcast_count; 2583 2584 /* 2585 * Update the multicase addresses to the MTA registers 2586 */ 2587 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count); 2588 } 2589 2590 /* 2591 * igb_get_conf - Get driver configurations set in driver.conf 2592 * 2593 * This routine gets user-configured values out of the configuration 2594 * file igb.conf. 2595 * 2596 * For each configurable value, there is a minimum, a maximum, and a 2597 * default. 2598 * If user does not configure a value, use the default. 2599 * If user configures below the minimum, use the minumum. 2600 * If user configures above the maximum, use the maxumum. 2601 */ 2602 static void 2603 igb_get_conf(igb_t *igb) 2604 { 2605 struct e1000_hw *hw = &igb->hw; 2606 uint32_t default_mtu; 2607 uint32_t flow_control; 2608 uint32_t ring_per_group; 2609 int i; 2610 2611 /* 2612 * igb driver supports the following user configurations: 2613 * 2614 * Link configurations: 2615 * adv_autoneg_cap 2616 * adv_1000fdx_cap 2617 * adv_100fdx_cap 2618 * adv_100hdx_cap 2619 * adv_10fdx_cap 2620 * adv_10hdx_cap 2621 * Note: 1000hdx is not supported. 2622 * 2623 * Jumbo frame configuration: 2624 * default_mtu 2625 * 2626 * Ethernet flow control configuration: 2627 * flow_control 2628 * 2629 * Multiple rings configurations: 2630 * tx_queue_number 2631 * tx_ring_size 2632 * rx_queue_number 2633 * rx_ring_size 2634 * 2635 * Call igb_get_prop() to get the value for a specific 2636 * configuration parameter. 2637 */ 2638 2639 /* 2640 * Link configurations 2641 */ 2642 igb->param_adv_autoneg_cap = igb_get_prop(igb, 2643 PROP_ADV_AUTONEG_CAP, 0, 1, 1); 2644 igb->param_adv_1000fdx_cap = igb_get_prop(igb, 2645 PROP_ADV_1000FDX_CAP, 0, 1, 1); 2646 igb->param_adv_100fdx_cap = igb_get_prop(igb, 2647 PROP_ADV_100FDX_CAP, 0, 1, 1); 2648 igb->param_adv_100hdx_cap = igb_get_prop(igb, 2649 PROP_ADV_100HDX_CAP, 0, 1, 1); 2650 igb->param_adv_10fdx_cap = igb_get_prop(igb, 2651 PROP_ADV_10FDX_CAP, 0, 1, 1); 2652 igb->param_adv_10hdx_cap = igb_get_prop(igb, 2653 PROP_ADV_10HDX_CAP, 0, 1, 1); 2654 2655 /* 2656 * Jumbo frame configurations 2657 */ 2658 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 2659 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2660 2661 igb->max_frame_size = default_mtu + 2662 sizeof (struct ether_vlan_header) + ETHERFCSL; 2663 2664 /* 2665 * Ethernet flow control configuration 2666 */ 2667 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL, 2668 e1000_fc_none, 4, e1000_fc_full); 2669 if (flow_control == 4) 2670 flow_control = e1000_fc_default; 2671 2672 hw->fc.requested_mode = flow_control; 2673 2674 /* 2675 * Multiple rings configurations 2676 */ 2677 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE, 2678 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2679 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE, 2680 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2681 2682 igb->mr_enable = igb_get_prop(igb, PROP_MR_ENABLE, 0, 1, 0); 2683 igb->num_rx_groups = igb_get_prop(igb, PROP_RX_GROUP_NUM, 2684 MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM); 2685 /* 2686 * Currently we do not support VMDq for 82576. 2687 * If it is e1000_82576, set num_rx_groups to 1. 2688 */ 2689 if (hw->mac.type == e1000_82576) 2690 igb->num_rx_groups = 1; 2691 2692 if (igb->mr_enable) { 2693 igb->num_tx_rings = igb->capab->def_tx_que_num; 2694 igb->num_rx_rings = igb->capab->def_rx_que_num; 2695 } else { 2696 igb->num_tx_rings = 1; 2697 igb->num_rx_rings = 1; 2698 2699 if (igb->num_rx_groups > 1) { 2700 igb_error(igb, 2701 "Invalid rx groups number. Please enable multiple " 2702 "rings first"); 2703 igb->num_rx_groups = 1; 2704 } 2705 } 2706 2707 /* 2708 * Check the divisibility between rx rings and rx groups. 2709 */ 2710 for (i = igb->num_rx_groups; i > 0; i--) { 2711 if ((igb->num_rx_rings % i) == 0) 2712 break; 2713 } 2714 if (i != igb->num_rx_groups) { 2715 igb_error(igb, 2716 "Invalid rx groups number. Downgrade the rx group " 2717 "number to %d.", i); 2718 igb->num_rx_groups = i; 2719 } 2720 2721 /* 2722 * Get the ring number per group. 2723 */ 2724 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2725 2726 if (igb->num_rx_groups == 1) { 2727 /* 2728 * One rx ring group, the rx ring number is num_rx_rings. 2729 */ 2730 igb->vmdq_mode = E1000_VMDQ_OFF; 2731 } else if (ring_per_group == 1) { 2732 /* 2733 * Multiple rx groups, each group has one rx ring. 2734 */ 2735 igb->vmdq_mode = E1000_VMDQ_MAC; 2736 } else { 2737 /* 2738 * Multiple groups and multiple rings. 2739 */ 2740 igb->vmdq_mode = E1000_VMDQ_MAC_RSS; 2741 } 2742 2743 /* 2744 * Tunable used to force an interrupt type. The only use is 2745 * for testing of the lesser interrupt types. 2746 * 0 = don't force interrupt type 2747 * 1 = force interrupt type MSIX 2748 * 2 = force interrupt type MSI 2749 * 3 = force interrupt type Legacy 2750 */ 2751 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE, 2752 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE); 2753 2754 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE, 2755 0, 1, 1); 2756 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE, 2757 0, 1, 1); 2758 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE, 2759 0, 1, 1); 2760 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE, 2761 0, 1, 1); 2762 2763 /* 2764 * igb LSO needs the tx h/w checksum support. 2765 * Here LSO will be disabled if tx h/w checksum has been disabled. 2766 */ 2767 if (igb->tx_hcksum_enable == B_FALSE) 2768 igb->lso_enable = B_FALSE; 2769 2770 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD, 2771 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 2772 DEFAULT_TX_COPY_THRESHOLD); 2773 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD, 2774 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 2775 DEFAULT_TX_RECYCLE_THRESHOLD); 2776 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD, 2777 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD, 2778 DEFAULT_TX_OVERLOAD_THRESHOLD); 2779 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD, 2780 MIN_TX_RESCHED_THRESHOLD, MAX_TX_RESCHED_THRESHOLD, 2781 DEFAULT_TX_RESCHED_THRESHOLD); 2782 2783 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD, 2784 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 2785 DEFAULT_RX_COPY_THRESHOLD); 2786 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR, 2787 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 2788 DEFAULT_RX_LIMIT_PER_INTR); 2789 2790 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING, 2791 igb->capab->min_intr_throttle, 2792 igb->capab->max_intr_throttle, 2793 igb->capab->def_intr_throttle); 2794 2795 /* 2796 * Max number of multicast addresses 2797 */ 2798 igb->mcast_max_num = 2799 igb_get_prop(igb, PROP_MCAST_MAX_NUM, 2800 MIN_MCAST_NUM, MAX_MCAST_NUM, DEFAULT_MCAST_NUM); 2801 } 2802 2803 /* 2804 * igb_get_prop - Get a property value out of the configuration file igb.conf 2805 * 2806 * Caller provides the name of the property, a default value, a minimum 2807 * value, and a maximum value. 2808 * 2809 * Return configured value of the property, with default, minimum and 2810 * maximum properly applied. 2811 */ 2812 static int 2813 igb_get_prop(igb_t *igb, 2814 char *propname, /* name of the property */ 2815 int minval, /* minimum acceptable value */ 2816 int maxval, /* maximim acceptable value */ 2817 int defval) /* default value */ 2818 { 2819 int value; 2820 2821 /* 2822 * Call ddi_prop_get_int() to read the conf settings 2823 */ 2824 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip, 2825 DDI_PROP_DONTPASS, propname, defval); 2826 2827 if (value > maxval) 2828 value = maxval; 2829 2830 if (value < minval) 2831 value = minval; 2832 2833 return (value); 2834 } 2835 2836 /* 2837 * igb_setup_link - Using the link properties to setup the link 2838 */ 2839 int 2840 igb_setup_link(igb_t *igb, boolean_t setup_hw) 2841 { 2842 struct e1000_mac_info *mac; 2843 struct e1000_phy_info *phy; 2844 boolean_t invalid; 2845 2846 mac = &igb->hw.mac; 2847 phy = &igb->hw.phy; 2848 invalid = B_FALSE; 2849 2850 if (igb->param_adv_autoneg_cap == 1) { 2851 mac->autoneg = B_TRUE; 2852 phy->autoneg_advertised = 0; 2853 2854 /* 2855 * 1000hdx is not supported for autonegotiation 2856 */ 2857 if (igb->param_adv_1000fdx_cap == 1) 2858 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 2859 2860 if (igb->param_adv_100fdx_cap == 1) 2861 phy->autoneg_advertised |= ADVERTISE_100_FULL; 2862 2863 if (igb->param_adv_100hdx_cap == 1) 2864 phy->autoneg_advertised |= ADVERTISE_100_HALF; 2865 2866 if (igb->param_adv_10fdx_cap == 1) 2867 phy->autoneg_advertised |= ADVERTISE_10_FULL; 2868 2869 if (igb->param_adv_10hdx_cap == 1) 2870 phy->autoneg_advertised |= ADVERTISE_10_HALF; 2871 2872 if (phy->autoneg_advertised == 0) 2873 invalid = B_TRUE; 2874 } else { 2875 mac->autoneg = B_FALSE; 2876 2877 /* 2878 * 1000fdx and 1000hdx are not supported for forced link 2879 */ 2880 if (igb->param_adv_100fdx_cap == 1) 2881 mac->forced_speed_duplex = ADVERTISE_100_FULL; 2882 else if (igb->param_adv_100hdx_cap == 1) 2883 mac->forced_speed_duplex = ADVERTISE_100_HALF; 2884 else if (igb->param_adv_10fdx_cap == 1) 2885 mac->forced_speed_duplex = ADVERTISE_10_FULL; 2886 else if (igb->param_adv_10hdx_cap == 1) 2887 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2888 else 2889 invalid = B_TRUE; 2890 } 2891 2892 if (invalid) { 2893 igb_notice(igb, "Invalid link settings. Setup link to " 2894 "autonegotiation with full link capabilities."); 2895 mac->autoneg = B_TRUE; 2896 phy->autoneg_advertised = ADVERTISE_1000_FULL | 2897 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 2898 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 2899 } 2900 2901 if (setup_hw) { 2902 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS) 2903 return (IGB_FAILURE); 2904 } 2905 2906 return (IGB_SUCCESS); 2907 } 2908 2909 2910 /* 2911 * igb_is_link_up - Check if the link is up 2912 */ 2913 static boolean_t 2914 igb_is_link_up(igb_t *igb) 2915 { 2916 struct e1000_hw *hw = &igb->hw; 2917 boolean_t link_up = B_FALSE; 2918 2919 ASSERT(mutex_owned(&igb->gen_lock)); 2920 2921 /* 2922 * get_link_status is set in the interrupt handler on link-status-change 2923 * or rx sequence error interrupt. get_link_status will stay 2924 * false until the e1000_check_for_link establishes link only 2925 * for copper adapters. 2926 */ 2927 switch (hw->phy.media_type) { 2928 case e1000_media_type_copper: 2929 if (hw->mac.get_link_status) { 2930 (void) e1000_check_for_link(hw); 2931 link_up = !hw->mac.get_link_status; 2932 } else { 2933 link_up = B_TRUE; 2934 } 2935 break; 2936 case e1000_media_type_fiber: 2937 (void) e1000_check_for_link(hw); 2938 link_up = (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 2939 break; 2940 case e1000_media_type_internal_serdes: 2941 (void) e1000_check_for_link(hw); 2942 link_up = hw->mac.serdes_has_link; 2943 break; 2944 } 2945 2946 return (link_up); 2947 } 2948 2949 /* 2950 * igb_link_check - Link status processing 2951 */ 2952 static boolean_t 2953 igb_link_check(igb_t *igb) 2954 { 2955 struct e1000_hw *hw = &igb->hw; 2956 uint16_t speed = 0, duplex = 0; 2957 boolean_t link_changed = B_FALSE; 2958 2959 ASSERT(mutex_owned(&igb->gen_lock)); 2960 2961 if (igb_is_link_up(igb)) { 2962 /* 2963 * The Link is up, check whether it was marked as down earlier 2964 */ 2965 if (igb->link_state != LINK_STATE_UP) { 2966 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 2967 igb->link_speed = speed; 2968 igb->link_duplex = duplex; 2969 igb->link_state = LINK_STATE_UP; 2970 igb->link_down_timeout = 0; 2971 link_changed = B_TRUE; 2972 } 2973 } else { 2974 if (igb->link_state != LINK_STATE_DOWN) { 2975 igb->link_speed = 0; 2976 igb->link_duplex = 0; 2977 igb->link_state = LINK_STATE_DOWN; 2978 link_changed = B_TRUE; 2979 } 2980 2981 if (igb->igb_state & IGB_STARTED) { 2982 if (igb->link_down_timeout < MAX_LINK_DOWN_TIMEOUT) { 2983 igb->link_down_timeout++; 2984 } else if (igb->link_down_timeout == 2985 MAX_LINK_DOWN_TIMEOUT) { 2986 igb_tx_clean(igb); 2987 igb->link_down_timeout++; 2988 } 2989 } 2990 } 2991 2992 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2993 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2994 2995 return (link_changed); 2996 } 2997 2998 /* 2999 * igb_local_timer - driver watchdog function 3000 * 3001 * This function will handle the transmit stall check, link status check and 3002 * other routines. 3003 */ 3004 static void 3005 igb_local_timer(void *arg) 3006 { 3007 igb_t *igb = (igb_t *)arg; 3008 boolean_t link_changed = B_FALSE; 3009 3010 if (igb_stall_check(igb)) { 3011 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL); 3012 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 3013 igb->reset_count++; 3014 if (igb_reset(igb) == IGB_SUCCESS) 3015 ddi_fm_service_impact(igb->dip, 3016 DDI_SERVICE_RESTORED); 3017 } 3018 3019 mutex_enter(&igb->gen_lock); 3020 if (!(igb->igb_state & IGB_SUSPENDED) && (igb->igb_state & IGB_STARTED)) 3021 link_changed = igb_link_check(igb); 3022 mutex_exit(&igb->gen_lock); 3023 3024 if (link_changed) 3025 mac_link_update(igb->mac_hdl, igb->link_state); 3026 3027 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 3028 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3029 3030 igb_restart_watchdog_timer(igb); 3031 } 3032 3033 /* 3034 * igb_stall_check - check for transmit stall 3035 * 3036 * This function checks if the adapter is stalled (in transmit). 3037 * 3038 * It is called each time the watchdog timeout is invoked. 3039 * If the transmit descriptor reclaim continuously fails, 3040 * the watchdog value will increment by 1. If the watchdog 3041 * value exceeds the threshold, the igb is assumed to 3042 * have stalled and need to be reset. 3043 */ 3044 static boolean_t 3045 igb_stall_check(igb_t *igb) 3046 { 3047 igb_tx_ring_t *tx_ring; 3048 boolean_t result; 3049 int i; 3050 3051 if (igb->link_state != LINK_STATE_UP) 3052 return (B_FALSE); 3053 3054 /* 3055 * If any tx ring is stalled, we'll reset the chipset 3056 */ 3057 result = B_FALSE; 3058 for (i = 0; i < igb->num_tx_rings; i++) { 3059 tx_ring = &igb->tx_rings[i]; 3060 3061 if (tx_ring->recycle_fail > 0) 3062 tx_ring->stall_watchdog++; 3063 else 3064 tx_ring->stall_watchdog = 0; 3065 3066 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 3067 result = B_TRUE; 3068 break; 3069 } 3070 } 3071 3072 if (result) { 3073 tx_ring->stall_watchdog = 0; 3074 tx_ring->recycle_fail = 0; 3075 } 3076 3077 return (result); 3078 } 3079 3080 3081 /* 3082 * is_valid_mac_addr - Check if the mac address is valid 3083 */ 3084 static boolean_t 3085 is_valid_mac_addr(uint8_t *mac_addr) 3086 { 3087 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3088 const uint8_t addr_test2[6] = 3089 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3090 3091 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3092 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3093 return (B_FALSE); 3094 3095 return (B_TRUE); 3096 } 3097 3098 static boolean_t 3099 igb_find_mac_address(igb_t *igb) 3100 { 3101 struct e1000_hw *hw = &igb->hw; 3102 #ifdef __sparc 3103 uchar_t *bytes; 3104 struct ether_addr sysaddr; 3105 uint_t nelts; 3106 int err; 3107 boolean_t found = B_FALSE; 3108 3109 /* 3110 * The "vendor's factory-set address" may already have 3111 * been extracted from the chip, but if the property 3112 * "local-mac-address" is set we use that instead. 3113 * 3114 * We check whether it looks like an array of 6 3115 * bytes (which it should, if OBP set it). If we can't 3116 * make sense of it this way, we'll ignore it. 3117 */ 3118 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3119 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 3120 if (err == DDI_PROP_SUCCESS) { 3121 if (nelts == ETHERADDRL) { 3122 while (nelts--) 3123 hw->mac.addr[nelts] = bytes[nelts]; 3124 found = B_TRUE; 3125 } 3126 ddi_prop_free(bytes); 3127 } 3128 3129 /* 3130 * Look up the OBP property "local-mac-address?". If the user has set 3131 * 'local-mac-address? = false', use "the system address" instead. 3132 */ 3133 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0, 3134 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 3135 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 3136 if (localetheraddr(NULL, &sysaddr) != 0) { 3137 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 3138 found = B_TRUE; 3139 } 3140 } 3141 ddi_prop_free(bytes); 3142 } 3143 3144 /* 3145 * Finally(!), if there's a valid "mac-address" property (created 3146 * if we netbooted from this interface), we must use this instead 3147 * of any of the above to ensure that the NFS/install server doesn't 3148 * get confused by the address changing as Solaris takes over! 3149 */ 3150 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3151 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 3152 if (err == DDI_PROP_SUCCESS) { 3153 if (nelts == ETHERADDRL) { 3154 while (nelts--) 3155 hw->mac.addr[nelts] = bytes[nelts]; 3156 found = B_TRUE; 3157 } 3158 ddi_prop_free(bytes); 3159 } 3160 3161 if (found) { 3162 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 3163 return (B_TRUE); 3164 } 3165 #endif 3166 3167 /* 3168 * Read the device MAC address from the EEPROM 3169 */ 3170 if (e1000_read_mac_addr(hw) != E1000_SUCCESS) 3171 return (B_FALSE); 3172 3173 return (B_TRUE); 3174 } 3175 3176 #pragma inline(igb_arm_watchdog_timer) 3177 3178 static void 3179 igb_arm_watchdog_timer(igb_t *igb) 3180 { 3181 /* 3182 * Fire a watchdog timer 3183 */ 3184 igb->watchdog_tid = 3185 timeout(igb_local_timer, 3186 (void *)igb, 1 * drv_usectohz(1000000)); 3187 3188 } 3189 3190 /* 3191 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer 3192 */ 3193 void 3194 igb_enable_watchdog_timer(igb_t *igb) 3195 { 3196 mutex_enter(&igb->watchdog_lock); 3197 3198 if (!igb->watchdog_enable) { 3199 igb->watchdog_enable = B_TRUE; 3200 igb->watchdog_start = B_TRUE; 3201 igb_arm_watchdog_timer(igb); 3202 } 3203 3204 mutex_exit(&igb->watchdog_lock); 3205 3206 } 3207 3208 /* 3209 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer 3210 */ 3211 void 3212 igb_disable_watchdog_timer(igb_t *igb) 3213 { 3214 timeout_id_t tid; 3215 3216 mutex_enter(&igb->watchdog_lock); 3217 3218 igb->watchdog_enable = B_FALSE; 3219 igb->watchdog_start = B_FALSE; 3220 tid = igb->watchdog_tid; 3221 igb->watchdog_tid = 0; 3222 3223 mutex_exit(&igb->watchdog_lock); 3224 3225 if (tid != 0) 3226 (void) untimeout(tid); 3227 3228 } 3229 3230 /* 3231 * igb_start_watchdog_timer - Start the driver watchdog timer 3232 */ 3233 static void 3234 igb_start_watchdog_timer(igb_t *igb) 3235 { 3236 mutex_enter(&igb->watchdog_lock); 3237 3238 if (igb->watchdog_enable) { 3239 if (!igb->watchdog_start) { 3240 igb->watchdog_start = B_TRUE; 3241 igb_arm_watchdog_timer(igb); 3242 } 3243 } 3244 3245 mutex_exit(&igb->watchdog_lock); 3246 } 3247 3248 /* 3249 * igb_restart_watchdog_timer - Restart the driver watchdog timer 3250 */ 3251 static void 3252 igb_restart_watchdog_timer(igb_t *igb) 3253 { 3254 mutex_enter(&igb->watchdog_lock); 3255 3256 if (igb->watchdog_start) 3257 igb_arm_watchdog_timer(igb); 3258 3259 mutex_exit(&igb->watchdog_lock); 3260 } 3261 3262 /* 3263 * igb_stop_watchdog_timer - Stop the driver watchdog timer 3264 */ 3265 static void 3266 igb_stop_watchdog_timer(igb_t *igb) 3267 { 3268 timeout_id_t tid; 3269 3270 mutex_enter(&igb->watchdog_lock); 3271 3272 igb->watchdog_start = B_FALSE; 3273 tid = igb->watchdog_tid; 3274 igb->watchdog_tid = 0; 3275 3276 mutex_exit(&igb->watchdog_lock); 3277 3278 if (tid != 0) 3279 (void) untimeout(tid); 3280 } 3281 3282 /* 3283 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts 3284 */ 3285 static void 3286 igb_disable_adapter_interrupts(igb_t *igb) 3287 { 3288 struct e1000_hw *hw = &igb->hw; 3289 3290 /* 3291 * Set the IMC register to mask all the interrupts, 3292 * including the tx interrupts. 3293 */ 3294 E1000_WRITE_REG(hw, E1000_IMC, ~0); 3295 E1000_WRITE_REG(hw, E1000_IAM, 0); 3296 3297 /* 3298 * Additional disabling for MSI-X 3299 */ 3300 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3301 E1000_WRITE_REG(hw, E1000_EIMC, ~0); 3302 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3303 E1000_WRITE_REG(hw, E1000_EIAM, 0); 3304 } 3305 3306 E1000_WRITE_FLUSH(hw); 3307 } 3308 3309 /* 3310 * igb_enable_adapter_interrupts_82576 - Enable NIC interrupts for 82576 3311 */ 3312 static void 3313 igb_enable_adapter_interrupts_82576(igb_t *igb) 3314 { 3315 struct e1000_hw *hw = &igb->hw; 3316 3317 /* Clear any pending interrupts */ 3318 (void) E1000_READ_REG(hw, E1000_ICR); 3319 3320 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3321 3322 /* Interrupt enabling for MSI-X */ 3323 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3324 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3325 igb->ims_mask = E1000_IMS_LSC; 3326 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3327 } else { 3328 /* Interrupt enabling for MSI and legacy */ 3329 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID); 3330 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE; 3331 E1000_WRITE_REG(hw, E1000_IMS, 3332 (IMS_ENABLE_MASK | E1000_IMS_TXQE)); 3333 } 3334 3335 /* Disable auto-mask for ICR interrupt bits */ 3336 E1000_WRITE_REG(hw, E1000_IAM, 0); 3337 3338 E1000_WRITE_FLUSH(hw); 3339 } 3340 3341 /* 3342 * igb_enable_adapter_interrupts_82575 - Enable NIC interrupts for 82575 3343 */ 3344 static void 3345 igb_enable_adapter_interrupts_82575(igb_t *igb) 3346 { 3347 struct e1000_hw *hw = &igb->hw; 3348 uint32_t reg; 3349 3350 /* Clear any pending interrupts */ 3351 (void) E1000_READ_REG(hw, E1000_ICR); 3352 3353 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3354 /* Interrupt enabling for MSI-X */ 3355 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3356 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3357 igb->ims_mask = E1000_IMS_LSC; 3358 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3359 3360 /* Enable MSI-X PBA support */ 3361 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 3362 reg |= E1000_CTRL_EXT_PBA_CLR; 3363 3364 /* Non-selective interrupt clear-on-read */ 3365 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */ 3366 3367 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 3368 } else { 3369 /* Interrupt enabling for MSI and legacy */ 3370 igb->ims_mask = IMS_ENABLE_MASK; 3371 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3372 } 3373 3374 E1000_WRITE_FLUSH(hw); 3375 } 3376 3377 /* 3378 * Loopback Support 3379 */ 3380 static lb_property_t lb_normal = 3381 { normal, "normal", IGB_LB_NONE }; 3382 static lb_property_t lb_external = 3383 { external, "External", IGB_LB_EXTERNAL }; 3384 static lb_property_t lb_mac = 3385 { internal, "MAC", IGB_LB_INTERNAL_MAC }; 3386 static lb_property_t lb_phy = 3387 { internal, "PHY", IGB_LB_INTERNAL_PHY }; 3388 static lb_property_t lb_serdes = 3389 { internal, "SerDes", IGB_LB_INTERNAL_SERDES }; 3390 3391 enum ioc_reply 3392 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp) 3393 { 3394 lb_info_sz_t *lbsp; 3395 lb_property_t *lbpp; 3396 struct e1000_hw *hw; 3397 uint32_t *lbmp; 3398 uint32_t size; 3399 uint32_t value; 3400 3401 hw = &igb->hw; 3402 3403 if (mp->b_cont == NULL) 3404 return (IOC_INVAL); 3405 3406 switch (iocp->ioc_cmd) { 3407 default: 3408 return (IOC_INVAL); 3409 3410 case LB_GET_INFO_SIZE: 3411 size = sizeof (lb_info_sz_t); 3412 if (iocp->ioc_count != size) 3413 return (IOC_INVAL); 3414 3415 value = sizeof (lb_normal); 3416 value += sizeof (lb_mac); 3417 if (hw->phy.media_type == e1000_media_type_copper) 3418 value += sizeof (lb_phy); 3419 else 3420 value += sizeof (lb_serdes); 3421 value += sizeof (lb_external); 3422 3423 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 3424 *lbsp = value; 3425 break; 3426 3427 case LB_GET_INFO: 3428 value = sizeof (lb_normal); 3429 value += sizeof (lb_mac); 3430 if (hw->phy.media_type == e1000_media_type_copper) 3431 value += sizeof (lb_phy); 3432 else 3433 value += sizeof (lb_serdes); 3434 value += sizeof (lb_external); 3435 3436 size = value; 3437 if (iocp->ioc_count != size) 3438 return (IOC_INVAL); 3439 3440 value = 0; 3441 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 3442 3443 lbpp[value++] = lb_normal; 3444 lbpp[value++] = lb_mac; 3445 if (hw->phy.media_type == e1000_media_type_copper) 3446 lbpp[value++] = lb_phy; 3447 else 3448 lbpp[value++] = lb_serdes; 3449 lbpp[value++] = lb_external; 3450 break; 3451 3452 case LB_GET_MODE: 3453 size = sizeof (uint32_t); 3454 if (iocp->ioc_count != size) 3455 return (IOC_INVAL); 3456 3457 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3458 *lbmp = igb->loopback_mode; 3459 break; 3460 3461 case LB_SET_MODE: 3462 size = 0; 3463 if (iocp->ioc_count != sizeof (uint32_t)) 3464 return (IOC_INVAL); 3465 3466 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3467 if (!igb_set_loopback_mode(igb, *lbmp)) 3468 return (IOC_INVAL); 3469 break; 3470 } 3471 3472 iocp->ioc_count = size; 3473 iocp->ioc_error = 0; 3474 3475 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 3476 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3477 return (IOC_INVAL); 3478 } 3479 3480 return (IOC_REPLY); 3481 } 3482 3483 /* 3484 * igb_set_loopback_mode - Setup loopback based on the loopback mode 3485 */ 3486 static boolean_t 3487 igb_set_loopback_mode(igb_t *igb, uint32_t mode) 3488 { 3489 struct e1000_hw *hw; 3490 3491 if (mode == igb->loopback_mode) 3492 return (B_TRUE); 3493 3494 hw = &igb->hw; 3495 3496 igb->loopback_mode = mode; 3497 3498 if (mode == IGB_LB_NONE) { 3499 /* Reset the chip */ 3500 hw->phy.autoneg_wait_to_complete = B_TRUE; 3501 (void) igb_reset(igb); 3502 hw->phy.autoneg_wait_to_complete = B_FALSE; 3503 return (B_TRUE); 3504 } 3505 3506 mutex_enter(&igb->gen_lock); 3507 3508 switch (mode) { 3509 default: 3510 mutex_exit(&igb->gen_lock); 3511 return (B_FALSE); 3512 3513 case IGB_LB_EXTERNAL: 3514 igb_set_external_loopback(igb); 3515 break; 3516 3517 case IGB_LB_INTERNAL_MAC: 3518 igb_set_internal_mac_loopback(igb); 3519 break; 3520 3521 case IGB_LB_INTERNAL_PHY: 3522 igb_set_internal_phy_loopback(igb); 3523 break; 3524 3525 case IGB_LB_INTERNAL_SERDES: 3526 igb_set_internal_serdes_loopback(igb); 3527 break; 3528 } 3529 3530 mutex_exit(&igb->gen_lock); 3531 3532 return (B_TRUE); 3533 } 3534 3535 /* 3536 * igb_set_external_loopback - Set the external loopback mode 3537 */ 3538 static void 3539 igb_set_external_loopback(igb_t *igb) 3540 { 3541 struct e1000_hw *hw; 3542 3543 hw = &igb->hw; 3544 3545 /* Set phy to known state */ 3546 (void) e1000_phy_hw_reset(hw); 3547 3548 (void) e1000_write_phy_reg(hw, 0x0, 0x0140); 3549 (void) e1000_write_phy_reg(hw, 0x9, 0x1b00); 3550 (void) e1000_write_phy_reg(hw, 0x12, 0x1610); 3551 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c); 3552 } 3553 3554 /* 3555 * igb_set_internal_mac_loopback - Set the internal MAC loopback mode 3556 */ 3557 static void 3558 igb_set_internal_mac_loopback(igb_t *igb) 3559 { 3560 struct e1000_hw *hw; 3561 uint32_t ctrl; 3562 uint32_t rctl; 3563 uint32_t ctrl_ext; 3564 uint16_t phy_ctrl; 3565 uint16_t phy_status; 3566 3567 hw = &igb->hw; 3568 3569 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 3570 phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 3571 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3572 3573 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3574 3575 /* Set link mode to PHY (00b) in the Extended Control register */ 3576 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3577 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3578 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3579 3580 /* Set the Device Control register */ 3581 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3582 if (!(phy_status & MII_SR_LINK_STATUS)) 3583 ctrl |= E1000_CTRL_ILOS; /* Set ILOS when the link is down */ 3584 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3585 ctrl |= (E1000_CTRL_SLU | /* Force link up */ 3586 E1000_CTRL_FRCSPD | /* Force speed */ 3587 E1000_CTRL_FRCDPX | /* Force duplex */ 3588 E1000_CTRL_SPD_1000 | /* Force speed to 1000 */ 3589 E1000_CTRL_FD); /* Force full duplex */ 3590 3591 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3592 3593 /* Set the Receive Control register */ 3594 rctl = E1000_READ_REG(hw, E1000_RCTL); 3595 rctl &= ~E1000_RCTL_LBM_TCVR; 3596 rctl |= E1000_RCTL_LBM_MAC; 3597 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3598 } 3599 3600 /* 3601 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode 3602 */ 3603 static void 3604 igb_set_internal_phy_loopback(igb_t *igb) 3605 { 3606 struct e1000_hw *hw; 3607 uint32_t ctrl_ext; 3608 uint16_t phy_ctrl; 3609 uint16_t phy_pconf; 3610 3611 hw = &igb->hw; 3612 3613 /* Set link mode to PHY (00b) in the Extended Control register */ 3614 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3615 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3616 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3617 3618 /* 3619 * Set PHY control register (0x4140): 3620 * Set full duplex mode 3621 * Set loopback bit 3622 * Clear auto-neg enable bit 3623 * Set PHY speed 3624 */ 3625 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK; 3626 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3627 3628 /* Set the link disable bit in the Port Configuration register */ 3629 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf); 3630 phy_pconf |= (uint16_t)1 << 14; 3631 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf); 3632 } 3633 3634 /* 3635 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode 3636 */ 3637 static void 3638 igb_set_internal_serdes_loopback(igb_t *igb) 3639 { 3640 struct e1000_hw *hw; 3641 uint32_t ctrl_ext; 3642 uint32_t ctrl; 3643 uint32_t pcs_lctl; 3644 uint32_t connsw; 3645 3646 hw = &igb->hw; 3647 3648 /* Set link mode to SerDes (11b) in the Extended Control register */ 3649 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3650 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 3651 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3652 3653 /* Configure the SerDes to loopback */ 3654 E1000_WRITE_REG(hw, E1000_SCTL, 0x410); 3655 3656 /* Set Device Control register */ 3657 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3658 ctrl |= (E1000_CTRL_FD | /* Force full duplex */ 3659 E1000_CTRL_SLU); /* Force link up */ 3660 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */ 3661 E1000_CTRL_TFCE | /* Disable transmit flow control */ 3662 E1000_CTRL_LRST); /* Clear link reset */ 3663 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3664 3665 /* Set PCS Link Control register */ 3666 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL); 3667 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK | 3668 E1000_PCS_LCTL_FSD | 3669 E1000_PCS_LCTL_FDV_FULL | 3670 E1000_PCS_LCTL_FLV_LINK_UP); 3671 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE; 3672 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl); 3673 3674 /* Set the Copper/Fiber Switch Control - CONNSW register */ 3675 connsw = E1000_READ_REG(hw, E1000_CONNSW); 3676 connsw &= ~E1000_CONNSW_ENRGSRC; 3677 E1000_WRITE_REG(hw, E1000_CONNSW, connsw); 3678 } 3679 3680 #pragma inline(igb_intr_rx_work) 3681 /* 3682 * igb_intr_rx_work - rx processing of ISR 3683 */ 3684 static void 3685 igb_intr_rx_work(igb_rx_ring_t *rx_ring) 3686 { 3687 mblk_t *mp; 3688 3689 mutex_enter(&rx_ring->rx_lock); 3690 mp = igb_rx(rx_ring, IGB_NO_POLL); 3691 mutex_exit(&rx_ring->rx_lock); 3692 3693 if (mp != NULL) 3694 mac_rx_ring(rx_ring->igb->mac_hdl, rx_ring->ring_handle, mp, 3695 rx_ring->ring_gen_num); 3696 } 3697 3698 #pragma inline(igb_intr_tx_work) 3699 /* 3700 * igb_intr_tx_work - tx processing of ISR 3701 */ 3702 static void 3703 igb_intr_tx_work(igb_tx_ring_t *tx_ring) 3704 { 3705 /* Recycle the tx descriptors */ 3706 tx_ring->tx_recycle(tx_ring); 3707 3708 /* Schedule the re-transmit */ 3709 if (tx_ring->reschedule && 3710 (tx_ring->tbd_free >= tx_ring->resched_thresh)) { 3711 tx_ring->reschedule = B_FALSE; 3712 mac_tx_ring_update(tx_ring->igb->mac_hdl, tx_ring->ring_handle); 3713 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3714 } 3715 } 3716 3717 #pragma inline(igb_intr_link_work) 3718 /* 3719 * igb_intr_link_work - link-status-change processing of ISR 3720 */ 3721 static void 3722 igb_intr_link_work(igb_t *igb) 3723 { 3724 boolean_t link_changed; 3725 3726 igb_stop_watchdog_timer(igb); 3727 3728 mutex_enter(&igb->gen_lock); 3729 3730 /* 3731 * Because we got a link-status-change interrupt, force 3732 * e1000_check_for_link() to look at phy 3733 */ 3734 igb->hw.mac.get_link_status = B_TRUE; 3735 3736 /* igb_link_check takes care of link status change */ 3737 link_changed = igb_link_check(igb); 3738 3739 /* Get new phy state */ 3740 igb_get_phy_state(igb); 3741 3742 mutex_exit(&igb->gen_lock); 3743 3744 if (link_changed) 3745 mac_link_update(igb->mac_hdl, igb->link_state); 3746 3747 igb_start_watchdog_timer(igb); 3748 } 3749 3750 /* 3751 * igb_intr_legacy - Interrupt handler for legacy interrupts 3752 */ 3753 static uint_t 3754 igb_intr_legacy(void *arg1, void *arg2) 3755 { 3756 igb_t *igb = (igb_t *)arg1; 3757 igb_tx_ring_t *tx_ring; 3758 uint32_t icr; 3759 mblk_t *mp; 3760 boolean_t tx_reschedule; 3761 boolean_t link_changed; 3762 uint_t result; 3763 3764 _NOTE(ARGUNUSED(arg2)); 3765 3766 mutex_enter(&igb->gen_lock); 3767 3768 if (igb->igb_state & IGB_SUSPENDED) { 3769 mutex_exit(&igb->gen_lock); 3770 return (DDI_INTR_UNCLAIMED); 3771 } 3772 3773 mp = NULL; 3774 tx_reschedule = B_FALSE; 3775 link_changed = B_FALSE; 3776 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3777 3778 if (icr & E1000_ICR_INT_ASSERTED) { 3779 /* 3780 * E1000_ICR_INT_ASSERTED bit was set: 3781 * Read(Clear) the ICR, claim this interrupt, 3782 * look for work to do. 3783 */ 3784 ASSERT(igb->num_rx_rings == 1); 3785 ASSERT(igb->num_tx_rings == 1); 3786 3787 /* Make sure all interrupt causes cleared */ 3788 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 3789 3790 if (icr & E1000_ICR_RXT0) { 3791 mp = igb_rx(&igb->rx_rings[0], IGB_NO_POLL); 3792 } 3793 3794 if (icr & E1000_ICR_TXDW) { 3795 tx_ring = &igb->tx_rings[0]; 3796 3797 /* Recycle the tx descriptors */ 3798 tx_ring->tx_recycle(tx_ring); 3799 3800 /* Schedule the re-transmit */ 3801 tx_reschedule = (tx_ring->reschedule && 3802 (tx_ring->tbd_free >= tx_ring->resched_thresh)); 3803 } 3804 3805 if (icr & E1000_ICR_LSC) { 3806 /* 3807 * Because we got a link-status-change interrupt, force 3808 * e1000_check_for_link() to look at phy 3809 */ 3810 igb->hw.mac.get_link_status = B_TRUE; 3811 3812 /* igb_link_check takes care of link status change */ 3813 link_changed = igb_link_check(igb); 3814 3815 /* Get new phy state */ 3816 igb_get_phy_state(igb); 3817 } 3818 3819 result = DDI_INTR_CLAIMED; 3820 } else { 3821 /* 3822 * E1000_ICR_INT_ASSERTED bit was not set: 3823 * Don't claim this interrupt. 3824 */ 3825 result = DDI_INTR_UNCLAIMED; 3826 } 3827 3828 mutex_exit(&igb->gen_lock); 3829 3830 /* 3831 * Do the following work outside of the gen_lock 3832 */ 3833 if (mp != NULL) 3834 mac_rx(igb->mac_hdl, NULL, mp); 3835 3836 if (tx_reschedule) { 3837 tx_ring->reschedule = B_FALSE; 3838 mac_tx_ring_update(igb->mac_hdl, tx_ring->ring_handle); 3839 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3840 } 3841 3842 if (link_changed) 3843 mac_link_update(igb->mac_hdl, igb->link_state); 3844 3845 return (result); 3846 } 3847 3848 /* 3849 * igb_intr_msi - Interrupt handler for MSI 3850 */ 3851 static uint_t 3852 igb_intr_msi(void *arg1, void *arg2) 3853 { 3854 igb_t *igb = (igb_t *)arg1; 3855 uint32_t icr; 3856 3857 _NOTE(ARGUNUSED(arg2)); 3858 3859 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3860 3861 /* Make sure all interrupt causes cleared */ 3862 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 3863 3864 /* 3865 * For MSI interrupt, we have only one vector, 3866 * so we have only one rx ring and one tx ring enabled. 3867 */ 3868 ASSERT(igb->num_rx_rings == 1); 3869 ASSERT(igb->num_tx_rings == 1); 3870 3871 if (icr & E1000_ICR_RXT0) { 3872 igb_intr_rx_work(&igb->rx_rings[0]); 3873 } 3874 3875 if (icr & E1000_ICR_TXDW) { 3876 igb_intr_tx_work(&igb->tx_rings[0]); 3877 } 3878 3879 if (icr & E1000_ICR_LSC) { 3880 igb_intr_link_work(igb); 3881 } 3882 3883 return (DDI_INTR_CLAIMED); 3884 } 3885 3886 /* 3887 * igb_intr_rx - Interrupt handler for rx 3888 */ 3889 static uint_t 3890 igb_intr_rx(void *arg1, void *arg2) 3891 { 3892 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1; 3893 3894 _NOTE(ARGUNUSED(arg2)); 3895 3896 /* 3897 * Only used via MSI-X vector so don't check cause bits 3898 * and only clean the given ring. 3899 */ 3900 igb_intr_rx_work(rx_ring); 3901 3902 return (DDI_INTR_CLAIMED); 3903 } 3904 3905 /* 3906 * igb_intr_tx - Interrupt handler for tx 3907 */ 3908 static uint_t 3909 igb_intr_tx(void *arg1, void *arg2) 3910 { 3911 igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg1; 3912 3913 _NOTE(ARGUNUSED(arg2)); 3914 3915 /* 3916 * Only used via MSI-X vector so don't check cause bits 3917 * and only clean the given ring. 3918 */ 3919 igb_intr_tx_work(tx_ring); 3920 3921 return (DDI_INTR_CLAIMED); 3922 } 3923 3924 /* 3925 * igb_intr_tx_other - Interrupt handler for both tx and other 3926 * 3927 */ 3928 static uint_t 3929 igb_intr_tx_other(void *arg1, void *arg2) 3930 { 3931 igb_t *igb = (igb_t *)arg1; 3932 uint32_t icr; 3933 3934 _NOTE(ARGUNUSED(arg2)); 3935 3936 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3937 3938 /* 3939 * Look for tx reclaiming work first. Remember, in the 3940 * case of only interrupt sharing, only one tx ring is 3941 * used 3942 */ 3943 igb_intr_tx_work(&igb->tx_rings[0]); 3944 3945 /* 3946 * Check for "other" causes. 3947 */ 3948 if (icr & E1000_ICR_LSC) { 3949 igb_intr_link_work(igb); 3950 } 3951 3952 /* 3953 * The DOUTSYNC bit indicates a tx packet dropped because 3954 * DMA engine gets "out of sync". There isn't a real fix 3955 * for this. The Intel recommendation is to count the number 3956 * of occurrences so user can detect when it is happening. 3957 * The issue is non-fatal and there's no recovery action 3958 * available. 3959 */ 3960 if (icr & E1000_ICR_DOUTSYNC) { 3961 IGB_STAT(igb->dout_sync); 3962 } 3963 3964 return (DDI_INTR_CLAIMED); 3965 } 3966 3967 /* 3968 * igb_alloc_intrs - Allocate interrupts for the driver 3969 * 3970 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 3971 * if not successful, try Legacy. 3972 * igb->intr_force can be used to force sequence to start with 3973 * any of the 3 types. 3974 * If MSI-X is not used, number of tx/rx rings is forced to 1. 3975 */ 3976 static int 3977 igb_alloc_intrs(igb_t *igb) 3978 { 3979 dev_info_t *devinfo; 3980 int intr_types; 3981 int rc; 3982 3983 devinfo = igb->dip; 3984 3985 /* Get supported interrupt types */ 3986 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3987 3988 if (rc != DDI_SUCCESS) { 3989 igb_log(igb, 3990 "Get supported interrupt types failed: %d", rc); 3991 return (IGB_FAILURE); 3992 } 3993 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types); 3994 3995 igb->intr_type = 0; 3996 3997 /* Install MSI-X interrupts */ 3998 if ((intr_types & DDI_INTR_TYPE_MSIX) && 3999 (igb->intr_force <= IGB_INTR_MSIX)) { 4000 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX); 4001 4002 if (rc == IGB_SUCCESS) 4003 return (IGB_SUCCESS); 4004 4005 igb_log(igb, 4006 "Allocate MSI-X failed, trying MSI interrupts..."); 4007 } 4008 4009 /* MSI-X not used, force rings to 1 */ 4010 igb->num_rx_rings = 1; 4011 igb->num_tx_rings = 1; 4012 igb_log(igb, 4013 "MSI-X not used, force rx and tx queue number to 1"); 4014 4015 /* Install MSI interrupts */ 4016 if ((intr_types & DDI_INTR_TYPE_MSI) && 4017 (igb->intr_force <= IGB_INTR_MSI)) { 4018 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI); 4019 4020 if (rc == IGB_SUCCESS) 4021 return (IGB_SUCCESS); 4022 4023 igb_log(igb, 4024 "Allocate MSI failed, trying Legacy interrupts..."); 4025 } 4026 4027 /* Install legacy interrupts */ 4028 if (intr_types & DDI_INTR_TYPE_FIXED) { 4029 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED); 4030 4031 if (rc == IGB_SUCCESS) 4032 return (IGB_SUCCESS); 4033 4034 igb_log(igb, 4035 "Allocate Legacy interrupts failed"); 4036 } 4037 4038 /* If none of the 3 types succeeded, return failure */ 4039 return (IGB_FAILURE); 4040 } 4041 4042 /* 4043 * igb_alloc_intr_handles - Allocate interrupt handles. 4044 * 4045 * For legacy and MSI, only 1 handle is needed. For MSI-X, 4046 * if fewer than 2 handles are available, return failure. 4047 * Upon success, this sets the number of Rx rings to a number that 4048 * matches the handles available for Rx interrupts. 4049 */ 4050 static int 4051 igb_alloc_intr_handles(igb_t *igb, int intr_type) 4052 { 4053 dev_info_t *devinfo; 4054 int orig, request, count, avail, actual; 4055 int diff, minimum; 4056 int rc; 4057 4058 devinfo = igb->dip; 4059 4060 switch (intr_type) { 4061 case DDI_INTR_TYPE_FIXED: 4062 request = 1; /* Request 1 legacy interrupt handle */ 4063 minimum = 1; 4064 IGB_DEBUGLOG_0(igb, "interrupt type: legacy"); 4065 break; 4066 4067 case DDI_INTR_TYPE_MSI: 4068 request = 1; /* Request 1 MSI interrupt handle */ 4069 minimum = 1; 4070 IGB_DEBUGLOG_0(igb, "interrupt type: MSI"); 4071 break; 4072 4073 case DDI_INTR_TYPE_MSIX: 4074 /* 4075 * Number of vectors for the adapter is 4076 * # rx rings + # tx rings 4077 * One of tx vectors is for tx & other 4078 */ 4079 request = igb->num_rx_rings + igb->num_tx_rings; 4080 orig = request; 4081 minimum = 2; 4082 IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X"); 4083 break; 4084 4085 default: 4086 igb_log(igb, 4087 "invalid call to igb_alloc_intr_handles(): %d\n", 4088 intr_type); 4089 return (IGB_FAILURE); 4090 } 4091 IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d minimum: %d", 4092 request, minimum); 4093 4094 /* 4095 * Get number of supported interrupts 4096 */ 4097 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4098 if ((rc != DDI_SUCCESS) || (count < minimum)) { 4099 igb_log(igb, 4100 "Get supported interrupt number failed. " 4101 "Return: %d, count: %d", rc, count); 4102 return (IGB_FAILURE); 4103 } 4104 IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count); 4105 4106 /* 4107 * Get number of available interrupts 4108 */ 4109 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4110 if ((rc != DDI_SUCCESS) || (avail < minimum)) { 4111 igb_log(igb, 4112 "Get available interrupt number failed. " 4113 "Return: %d, available: %d", rc, avail); 4114 return (IGB_FAILURE); 4115 } 4116 IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail); 4117 4118 if (avail < request) { 4119 igb_log(igb, "Request %d handles, %d available", 4120 request, avail); 4121 request = avail; 4122 } 4123 4124 actual = 0; 4125 igb->intr_cnt = 0; 4126 4127 /* 4128 * Allocate an array of interrupt handles 4129 */ 4130 igb->intr_size = request * sizeof (ddi_intr_handle_t); 4131 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 4132 4133 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0, 4134 request, &actual, DDI_INTR_ALLOC_NORMAL); 4135 if (rc != DDI_SUCCESS) { 4136 igb_log(igb, "Allocate interrupts failed. " 4137 "return: %d, request: %d, actual: %d", 4138 rc, request, actual); 4139 goto alloc_handle_fail; 4140 } 4141 IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual); 4142 4143 igb->intr_cnt = actual; 4144 4145 if (actual < minimum) { 4146 igb_log(igb, "Insufficient interrupt handles allocated: %d", 4147 actual); 4148 goto alloc_handle_fail; 4149 } 4150 4151 /* 4152 * For MSI-X, actual might force us to reduce number of tx & rx rings 4153 */ 4154 if ((intr_type == DDI_INTR_TYPE_MSIX) && (orig > actual)) { 4155 diff = orig - actual; 4156 if (diff < igb->num_tx_rings) { 4157 igb_log(igb, 4158 "MSI-X vectors force Tx queue number to %d", 4159 igb->num_tx_rings - diff); 4160 igb->num_tx_rings -= diff; 4161 } else { 4162 igb_log(igb, 4163 "MSI-X vectors force Tx queue number to 1"); 4164 igb->num_tx_rings = 1; 4165 4166 igb_log(igb, 4167 "MSI-X vectors force Rx queue number to %d", 4168 actual - 1); 4169 igb->num_rx_rings = actual - 1; 4170 } 4171 } 4172 4173 /* 4174 * Get priority for first vector, assume remaining are all the same 4175 */ 4176 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 4177 if (rc != DDI_SUCCESS) { 4178 igb_log(igb, 4179 "Get interrupt priority failed: %d", rc); 4180 goto alloc_handle_fail; 4181 } 4182 4183 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 4184 if (rc != DDI_SUCCESS) { 4185 igb_log(igb, 4186 "Get interrupt cap failed: %d", rc); 4187 goto alloc_handle_fail; 4188 } 4189 4190 igb->intr_type = intr_type; 4191 4192 return (IGB_SUCCESS); 4193 4194 alloc_handle_fail: 4195 igb_rem_intrs(igb); 4196 4197 return (IGB_FAILURE); 4198 } 4199 4200 /* 4201 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type 4202 * 4203 * Before adding the interrupt handlers, the interrupt vectors have 4204 * been allocated, and the rx/tx rings have also been allocated. 4205 */ 4206 static int 4207 igb_add_intr_handlers(igb_t *igb) 4208 { 4209 igb_rx_ring_t *rx_ring; 4210 igb_tx_ring_t *tx_ring; 4211 int vector; 4212 int rc; 4213 int i; 4214 4215 vector = 0; 4216 4217 switch (igb->intr_type) { 4218 case DDI_INTR_TYPE_MSIX: 4219 /* Add interrupt handler for tx + other */ 4220 tx_ring = &igb->tx_rings[0]; 4221 rc = ddi_intr_add_handler(igb->htable[vector], 4222 (ddi_intr_handler_t *)igb_intr_tx_other, 4223 (void *)igb, NULL); 4224 4225 if (rc != DDI_SUCCESS) { 4226 igb_log(igb, 4227 "Add tx/other interrupt handler failed: %d", rc); 4228 return (IGB_FAILURE); 4229 } 4230 tx_ring->intr_vector = vector; 4231 vector++; 4232 4233 /* Add interrupt handler for each rx ring */ 4234 for (i = 0; i < igb->num_rx_rings; i++) { 4235 rx_ring = &igb->rx_rings[i]; 4236 4237 rc = ddi_intr_add_handler(igb->htable[vector], 4238 (ddi_intr_handler_t *)igb_intr_rx, 4239 (void *)rx_ring, NULL); 4240 4241 if (rc != DDI_SUCCESS) { 4242 igb_log(igb, 4243 "Add rx interrupt handler failed. " 4244 "return: %d, rx ring: %d", rc, i); 4245 for (vector--; vector >= 0; vector--) { 4246 (void) ddi_intr_remove_handler( 4247 igb->htable[vector]); 4248 } 4249 return (IGB_FAILURE); 4250 } 4251 4252 rx_ring->intr_vector = vector; 4253 4254 vector++; 4255 } 4256 4257 /* Add interrupt handler for each tx ring from 2nd ring */ 4258 for (i = 1; i < igb->num_tx_rings; i++) { 4259 tx_ring = &igb->tx_rings[i]; 4260 4261 rc = ddi_intr_add_handler(igb->htable[vector], 4262 (ddi_intr_handler_t *)igb_intr_tx, 4263 (void *)tx_ring, NULL); 4264 4265 if (rc != DDI_SUCCESS) { 4266 igb_log(igb, 4267 "Add tx interrupt handler failed. " 4268 "return: %d, tx ring: %d", rc, i); 4269 for (vector--; vector >= 0; vector--) { 4270 (void) ddi_intr_remove_handler( 4271 igb->htable[vector]); 4272 } 4273 return (IGB_FAILURE); 4274 } 4275 4276 tx_ring->intr_vector = vector; 4277 4278 vector++; 4279 } 4280 4281 break; 4282 4283 case DDI_INTR_TYPE_MSI: 4284 /* Add interrupt handlers for the only vector */ 4285 rc = ddi_intr_add_handler(igb->htable[vector], 4286 (ddi_intr_handler_t *)igb_intr_msi, 4287 (void *)igb, NULL); 4288 4289 if (rc != DDI_SUCCESS) { 4290 igb_log(igb, 4291 "Add MSI interrupt handler failed: %d", rc); 4292 return (IGB_FAILURE); 4293 } 4294 4295 rx_ring = &igb->rx_rings[0]; 4296 rx_ring->intr_vector = vector; 4297 4298 vector++; 4299 break; 4300 4301 case DDI_INTR_TYPE_FIXED: 4302 /* Add interrupt handlers for the only vector */ 4303 rc = ddi_intr_add_handler(igb->htable[vector], 4304 (ddi_intr_handler_t *)igb_intr_legacy, 4305 (void *)igb, NULL); 4306 4307 if (rc != DDI_SUCCESS) { 4308 igb_log(igb, 4309 "Add legacy interrupt handler failed: %d", rc); 4310 return (IGB_FAILURE); 4311 } 4312 4313 rx_ring = &igb->rx_rings[0]; 4314 rx_ring->intr_vector = vector; 4315 4316 vector++; 4317 break; 4318 4319 default: 4320 return (IGB_FAILURE); 4321 } 4322 4323 ASSERT(vector == igb->intr_cnt); 4324 4325 return (IGB_SUCCESS); 4326 } 4327 4328 /* 4329 * igb_setup_msix_82575 - setup 82575 adapter to use MSI-X interrupts 4330 * 4331 * For each vector enabled on the adapter, Set the MSIXBM register accordingly 4332 */ 4333 static void 4334 igb_setup_msix_82575(igb_t *igb) 4335 { 4336 uint32_t eims = 0; 4337 int i, vector; 4338 struct e1000_hw *hw = &igb->hw; 4339 4340 /* 4341 * Set vector for tx ring 0 and other causes. 4342 * NOTE assumption that it is vector 0. 4343 */ 4344 vector = 0; 4345 4346 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER; 4347 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask); 4348 vector++; 4349 4350 for (i = 0; i < igb->num_rx_rings; i++) { 4351 /* 4352 * Set vector for each rx ring 4353 */ 4354 eims = (E1000_EICR_RX_QUEUE0 << i); 4355 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4356 4357 /* 4358 * Accumulate bits to enable in 4359 * igb_enable_adapter_interrupts_82575() 4360 */ 4361 igb->eims_mask |= eims; 4362 4363 vector++; 4364 } 4365 4366 for (i = 1; i < igb->num_tx_rings; i++) { 4367 /* 4368 * Set vector for each tx ring from 2nd tx ring 4369 */ 4370 eims = (E1000_EICR_TX_QUEUE0 << i); 4371 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4372 4373 /* 4374 * Accumulate bits to enable in 4375 * igb_enable_adapter_interrupts_82575() 4376 */ 4377 igb->eims_mask |= eims; 4378 4379 vector++; 4380 } 4381 4382 ASSERT(vector == igb->intr_cnt); 4383 4384 /* 4385 * Disable IAM for ICR interrupt bits 4386 */ 4387 E1000_WRITE_REG(hw, E1000_IAM, 0); 4388 E1000_WRITE_FLUSH(hw); 4389 } 4390 4391 /* 4392 * igb_setup_msix_82576 - setup 82576 adapter to use MSI-X interrupts 4393 * 4394 * 82576 uses a table based method for assigning vectors. Each queue has a 4395 * single entry in the table to which we write a vector number along with a 4396 * "valid" bit. The entry is a single byte in a 4-byte register. Vectors 4397 * take a different position in the 4-byte register depending on whether 4398 * they are numbered above or below 8. 4399 */ 4400 static void 4401 igb_setup_msix_82576(igb_t *igb) 4402 { 4403 struct e1000_hw *hw = &igb->hw; 4404 uint32_t ivar, index, vector; 4405 int i; 4406 4407 /* must enable msi-x capability before IVAR settings */ 4408 E1000_WRITE_REG(hw, E1000_GPIE, 4409 (E1000_GPIE_MSIX_MODE | E1000_GPIE_PBA | E1000_GPIE_NSICR)); 4410 4411 /* 4412 * Set vector for tx ring 0 and other causes. 4413 * NOTE assumption that it is vector 0. 4414 * This is also interdependent with installation of interrupt service 4415 * routines in igb_add_intr_handlers(). 4416 */ 4417 4418 /* assign "other" causes to vector 0 */ 4419 vector = 0; 4420 ivar = ((vector | E1000_IVAR_VALID) << 8); 4421 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 4422 4423 /* assign tx ring 0 to vector 0 */ 4424 ivar = ((vector | E1000_IVAR_VALID) << 8); 4425 E1000_WRITE_REG(hw, E1000_IVAR0, ivar); 4426 4427 /* prepare to enable tx & other interrupt causes */ 4428 igb->eims_mask = (1 << vector); 4429 4430 vector ++; 4431 for (i = 0; i < igb->num_rx_rings; i++) { 4432 /* 4433 * Set vector for each rx ring 4434 */ 4435 index = (i & 0x7); 4436 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4437 4438 if (i < 8) { 4439 /* vector goes into low byte of register */ 4440 ivar = ivar & 0xFFFFFF00; 4441 ivar |= (vector | E1000_IVAR_VALID); 4442 } else { 4443 /* vector goes into third byte of register */ 4444 ivar = ivar & 0xFF00FFFF; 4445 ivar |= ((vector | E1000_IVAR_VALID) << 16); 4446 } 4447 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4448 4449 /* Accumulate interrupt-cause bits to enable */ 4450 igb->eims_mask |= (1 << vector); 4451 4452 vector ++; 4453 } 4454 4455 for (i = 1; i < igb->num_tx_rings; i++) { 4456 /* 4457 * Set vector for each tx ring from 2nd tx ring. 4458 * Note assumption that tx vectors numericall follow rx vectors. 4459 */ 4460 index = (i & 0x7); 4461 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4462 4463 if (i < 8) { 4464 /* vector goes into second byte of register */ 4465 ivar = ivar & 0xFFFF00FF; 4466 ivar |= ((vector | E1000_IVAR_VALID) << 8); 4467 } else { 4468 /* vector goes into fourth byte of register */ 4469 ivar = ivar & 0x00FFFFFF; 4470 ivar |= (vector | E1000_IVAR_VALID) << 24; 4471 } 4472 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4473 4474 /* Accumulate interrupt-cause bits to enable */ 4475 igb->eims_mask |= (1 << vector); 4476 4477 vector ++; 4478 } 4479 4480 ASSERT(vector == igb->intr_cnt); 4481 } 4482 4483 /* 4484 * igb_rem_intr_handlers - remove the interrupt handlers 4485 */ 4486 static void 4487 igb_rem_intr_handlers(igb_t *igb) 4488 { 4489 int i; 4490 int rc; 4491 4492 for (i = 0; i < igb->intr_cnt; i++) { 4493 rc = ddi_intr_remove_handler(igb->htable[i]); 4494 if (rc != DDI_SUCCESS) { 4495 IGB_DEBUGLOG_1(igb, 4496 "Remove intr handler failed: %d", rc); 4497 } 4498 } 4499 } 4500 4501 /* 4502 * igb_rem_intrs - remove the allocated interrupts 4503 */ 4504 static void 4505 igb_rem_intrs(igb_t *igb) 4506 { 4507 int i; 4508 int rc; 4509 4510 for (i = 0; i < igb->intr_cnt; i++) { 4511 rc = ddi_intr_free(igb->htable[i]); 4512 if (rc != DDI_SUCCESS) { 4513 IGB_DEBUGLOG_1(igb, 4514 "Free intr failed: %d", rc); 4515 } 4516 } 4517 4518 kmem_free(igb->htable, igb->intr_size); 4519 igb->htable = NULL; 4520 } 4521 4522 /* 4523 * igb_enable_intrs - enable all the ddi interrupts 4524 */ 4525 static int 4526 igb_enable_intrs(igb_t *igb) 4527 { 4528 int i; 4529 int rc; 4530 4531 /* Enable interrupts */ 4532 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4533 /* Call ddi_intr_block_enable() for MSI */ 4534 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); 4535 if (rc != DDI_SUCCESS) { 4536 igb_log(igb, 4537 "Enable block intr failed: %d", rc); 4538 return (IGB_FAILURE); 4539 } 4540 } else { 4541 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4542 for (i = 0; i < igb->intr_cnt; i++) { 4543 rc = ddi_intr_enable(igb->htable[i]); 4544 if (rc != DDI_SUCCESS) { 4545 igb_log(igb, 4546 "Enable intr failed: %d", rc); 4547 return (IGB_FAILURE); 4548 } 4549 } 4550 } 4551 4552 return (IGB_SUCCESS); 4553 } 4554 4555 /* 4556 * igb_disable_intrs - disable all the ddi interrupts 4557 */ 4558 static int 4559 igb_disable_intrs(igb_t *igb) 4560 { 4561 int i; 4562 int rc; 4563 4564 /* Disable all interrupts */ 4565 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4566 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt); 4567 if (rc != DDI_SUCCESS) { 4568 igb_log(igb, 4569 "Disable block intr failed: %d", rc); 4570 return (IGB_FAILURE); 4571 } 4572 } else { 4573 for (i = 0; i < igb->intr_cnt; i++) { 4574 rc = ddi_intr_disable(igb->htable[i]); 4575 if (rc != DDI_SUCCESS) { 4576 igb_log(igb, 4577 "Disable intr failed: %d", rc); 4578 return (IGB_FAILURE); 4579 } 4580 } 4581 } 4582 4583 return (IGB_SUCCESS); 4584 } 4585 4586 /* 4587 * igb_get_phy_state - Get and save the parameters read from PHY registers 4588 */ 4589 static void 4590 igb_get_phy_state(igb_t *igb) 4591 { 4592 struct e1000_hw *hw = &igb->hw; 4593 uint16_t phy_ctrl; 4594 uint16_t phy_status; 4595 uint16_t phy_an_adv; 4596 uint16_t phy_an_exp; 4597 uint16_t phy_ext_status; 4598 uint16_t phy_1000t_ctrl; 4599 uint16_t phy_1000t_status; 4600 uint16_t phy_lp_able; 4601 4602 ASSERT(mutex_owned(&igb->gen_lock)); 4603 4604 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4605 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 4606 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv); 4607 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp); 4608 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 4609 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl); 4610 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_1000t_status); 4611 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able); 4612 4613 igb->param_autoneg_cap = 4614 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 4615 igb->param_pause_cap = 4616 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4617 igb->param_asym_pause_cap = 4618 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4619 igb->param_1000fdx_cap = ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4620 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 4621 igb->param_1000hdx_cap = ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 4622 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 4623 igb->param_100t4_cap = 4624 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 4625 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) || 4626 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 4627 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) || 4628 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 4629 igb->param_10fdx_cap = 4630 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 4631 igb->param_10hdx_cap = 4632 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 4633 igb->param_rem_fault = 4634 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0; 4635 4636 igb->param_adv_autoneg_cap = hw->mac.autoneg; 4637 igb->param_adv_pause_cap = 4638 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4639 igb->param_adv_asym_pause_cap = 4640 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4641 igb->param_adv_1000hdx_cap = 4642 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 4643 igb->param_adv_100t4_cap = 4644 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 4645 igb->param_adv_rem_fault = 4646 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0; 4647 if (igb->param_adv_autoneg_cap == 1) { 4648 igb->param_adv_1000fdx_cap = 4649 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 4650 igb->param_adv_100fdx_cap = 4651 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 4652 igb->param_adv_100hdx_cap = 4653 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 4654 igb->param_adv_10fdx_cap = 4655 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 4656 igb->param_adv_10hdx_cap = 4657 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 4658 } 4659 4660 igb->param_lp_autoneg_cap = 4661 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 4662 igb->param_lp_pause_cap = 4663 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 4664 igb->param_lp_asym_pause_cap = 4665 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 4666 igb->param_lp_1000fdx_cap = 4667 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 4668 igb->param_lp_1000hdx_cap = 4669 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 4670 igb->param_lp_100t4_cap = 4671 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 4672 igb->param_lp_100fdx_cap = 4673 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 4674 igb->param_lp_100hdx_cap = 4675 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 4676 igb->param_lp_10fdx_cap = 4677 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 4678 igb->param_lp_10hdx_cap = 4679 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 4680 igb->param_lp_rem_fault = 4681 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0; 4682 } 4683 4684 /* 4685 * igb_get_driver_control 4686 */ 4687 static void 4688 igb_get_driver_control(struct e1000_hw *hw) 4689 { 4690 uint32_t ctrl_ext; 4691 4692 /* Notify firmware that driver is in control of device */ 4693 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4694 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD; 4695 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4696 } 4697 4698 /* 4699 * igb_release_driver_control 4700 */ 4701 static void 4702 igb_release_driver_control(struct e1000_hw *hw) 4703 { 4704 uint32_t ctrl_ext; 4705 4706 /* Notify firmware that driver is no longer in control of device */ 4707 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4708 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD; 4709 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4710 } 4711 4712 /* 4713 * igb_atomic_reserve - Atomic decrease operation 4714 */ 4715 int 4716 igb_atomic_reserve(uint32_t *count_p, uint32_t n) 4717 { 4718 uint32_t oldval; 4719 uint32_t newval; 4720 4721 /* ATOMICALLY */ 4722 do { 4723 oldval = *count_p; 4724 if (oldval < n) 4725 return (-1); 4726 newval = oldval - n; 4727 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 4728 4729 return (newval); 4730 } 4731 4732 /* 4733 * FMA support 4734 */ 4735 4736 int 4737 igb_check_acc_handle(ddi_acc_handle_t handle) 4738 { 4739 ddi_fm_error_t de; 4740 4741 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 4742 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 4743 return (de.fme_status); 4744 } 4745 4746 int 4747 igb_check_dma_handle(ddi_dma_handle_t handle) 4748 { 4749 ddi_fm_error_t de; 4750 4751 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 4752 return (de.fme_status); 4753 } 4754 4755 /* 4756 * The IO fault service error handling callback function 4757 */ 4758 /*ARGSUSED*/ 4759 static int 4760 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 4761 { 4762 /* 4763 * as the driver can always deal with an error in any dma or 4764 * access handle, we can just return the fme_status value. 4765 */ 4766 pci_ereport_post(dip, err, NULL); 4767 return (err->fme_status); 4768 } 4769 4770 static void 4771 igb_fm_init(igb_t *igb) 4772 { 4773 ddi_iblock_cookie_t iblk; 4774 int fma_acc_flag, fma_dma_flag; 4775 4776 /* Only register with IO Fault Services if we have some capability */ 4777 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 4778 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 4779 fma_acc_flag = 1; 4780 } else { 4781 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 4782 fma_acc_flag = 0; 4783 } 4784 4785 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 4786 fma_dma_flag = 1; 4787 } else { 4788 fma_dma_flag = 0; 4789 } 4790 4791 (void) igb_set_fma_flags(fma_acc_flag, fma_dma_flag); 4792 4793 if (igb->fm_capabilities) { 4794 4795 /* Register capabilities with IO Fault Services */ 4796 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk); 4797 4798 /* 4799 * Initialize pci ereport capabilities if ereport capable 4800 */ 4801 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4802 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4803 pci_ereport_setup(igb->dip); 4804 4805 /* 4806 * Register error callback if error callback capable 4807 */ 4808 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4809 ddi_fm_handler_register(igb->dip, 4810 igb_fm_error_cb, (void*) igb); 4811 } 4812 } 4813 4814 static void 4815 igb_fm_fini(igb_t *igb) 4816 { 4817 /* Only unregister FMA capabilities if we registered some */ 4818 if (igb->fm_capabilities) { 4819 4820 /* 4821 * Release any resources allocated by pci_ereport_setup() 4822 */ 4823 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4824 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4825 pci_ereport_teardown(igb->dip); 4826 4827 /* 4828 * Un-register error callback if error callback capable 4829 */ 4830 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4831 ddi_fm_handler_unregister(igb->dip); 4832 4833 /* Unregister from IO Fault Services */ 4834 ddi_fm_fini(igb->dip); 4835 } 4836 } 4837 4838 void 4839 igb_fm_ereport(igb_t *igb, char *detail) 4840 { 4841 uint64_t ena; 4842 char buf[FM_MAX_CLASS]; 4843 4844 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 4845 ena = fm_ena_generate(0, FM_ENA_FMT1); 4846 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) { 4847 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP, 4848 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 4849 } 4850 } 4851
Indexes created Sun Nov 22 02:16:54 UTC 2009
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