1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.108 scm_100809_154340 */ 30 31 #include "igb_api.h" 32 33 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw); 34 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw); 35 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw); 36 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 37 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 38 39 /* 40 * e1000_init_mac_ops_generic - Initialize MAC function pointers 41 * @hw: pointer to the HW structure 42 * 43 * Setups up the function pointers to no-op functions 44 */ 45 void 46 e1000_init_mac_ops_generic(struct e1000_hw *hw) 47 { 48 struct e1000_mac_info *mac = &hw->mac; 49 DEBUGFUNC("e1000_init_mac_ops_generic"); 50 51 /* General Setup */ 52 mac->ops.init_params = e1000_null_ops_generic; 53 mac->ops.init_hw = e1000_null_ops_generic; 54 mac->ops.reset_hw = e1000_null_ops_generic; 55 mac->ops.setup_physical_interface = e1000_null_ops_generic; 56 mac->ops.get_bus_info = e1000_null_ops_generic; 57 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 58 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 59 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 60 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 61 /* LED */ 62 mac->ops.cleanup_led = e1000_null_ops_generic; 63 mac->ops.setup_led = e1000_null_ops_generic; 64 mac->ops.blink_led = e1000_null_ops_generic; 65 mac->ops.led_on = e1000_null_ops_generic; 66 mac->ops.led_off = e1000_null_ops_generic; 67 /* LINK */ 68 mac->ops.setup_link = e1000_null_ops_generic; 69 mac->ops.get_link_up_info = e1000_null_link_info; 70 mac->ops.check_for_link = e1000_null_ops_generic; 71 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 72 /* Management */ 73 mac->ops.check_mng_mode = e1000_null_mng_mode; 74 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 75 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 76 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 77 /* VLAN, MC, etc. */ 78 mac->ops.update_mc_addr_list = e1000_null_update_mc; 79 mac->ops.clear_vfta = e1000_null_mac_generic; 80 mac->ops.write_vfta = e1000_null_write_vfta; 81 mac->ops.mta_set = e1000_null_mta_set; 82 mac->ops.rar_set = e1000_rar_set_generic; 83 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 84 } 85 86 /* 87 * e1000_null_ops_generic - No-op function, returns 0 88 * @hw: pointer to the HW structure 89 */ 90 s32 91 e1000_null_ops_generic(struct e1000_hw *hw) 92 { 93 DEBUGFUNC("e1000_null_ops_generic"); 94 UNREFERENCED_1PARAMETER(hw); 95 return (E1000_SUCCESS); 96 } 97 98 /* 99 * e1000_null_mac_generic - No-op function, return void 100 * @hw: pointer to the HW structure 101 */ 102 void 103 e1000_null_mac_generic(struct e1000_hw *hw) 104 { 105 DEBUGFUNC("e1000_null_mac_generic"); 106 UNREFERENCED_1PARAMETER(hw); 107 } 108 109 /* 110 * e1000_null_link_info - No-op function, return 0 111 * @hw: pointer to the HW structure 112 */ 113 s32 114 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 115 { 116 DEBUGFUNC("e1000_null_link_info"); 117 UNREFERENCED_3PARAMETER(hw, s, d); 118 return (E1000_SUCCESS); 119 } 120 121 /* 122 * e1000_null_mng_mode - No-op function, return false 123 * @hw: pointer to the HW structure 124 */ 125 bool 126 e1000_null_mng_mode(struct e1000_hw *hw) 127 { 128 DEBUGFUNC("e1000_null_mng_mode"); 129 UNREFERENCED_1PARAMETER(hw); 130 return (false); 131 } 132 133 /* 134 * e1000_null_update_mc - No-op function, return void 135 * @hw: pointer to the HW structure 136 */ 137 void 138 e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 139 { 140 DEBUGFUNC("e1000_null_update_mc"); 141 UNREFERENCED_3PARAMETER(hw, h, a); 142 } 143 144 /* 145 * e1000_null_write_vfta - No-op function, return void 146 * @hw: pointer to the HW structure 147 */ 148 void 149 e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 150 { 151 DEBUGFUNC("e1000_null_write_vfta"); 152 UNREFERENCED_3PARAMETER(hw, a, b); 153 } 154 155 /* 156 * e1000_null_set_mta - No-op function, return void 157 * @hw: pointer to the HW structure 158 */ 159 void 160 e1000_null_mta_set(struct e1000_hw *hw, u32 a) 161 { 162 DEBUGFUNC("e1000_null_mta_set"); 163 UNREFERENCED_2PARAMETER(hw, a); 164 } 165 166 /* 167 * e1000_null_rar_set - No-op function, return void 168 * @hw: pointer to the HW structure 169 */ 170 void 171 e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 172 { 173 DEBUGFUNC("e1000_null_rar_set"); 174 UNREFERENCED_3PARAMETER(hw, h, a); 175 } 176 177 /* 178 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 179 * @hw: pointer to the HW structure 180 * 181 * Determines and stores the system bus information for a particular 182 * network interface. The following bus information is determined and stored: 183 * bus speed, bus width, type (PCIe), and PCIe function. 184 */ 185 s32 186 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 187 { 188 struct e1000_mac_info *mac = &hw->mac; 189 struct e1000_bus_info *bus = &hw->bus; 190 s32 ret_val; 191 u16 pcie_link_status; 192 193 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 194 195 bus->type = e1000_bus_type_pci_express; 196 bus->speed = e1000_bus_speed_2500; 197 198 ret_val = e1000_read_pcie_cap_reg(hw, 199 PCIE_LINK_STATUS, &pcie_link_status); 200 if (ret_val) 201 bus->width = e1000_bus_width_unknown; 202 else 203 bus->width = (enum e1000_bus_width)((pcie_link_status & 204 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 205 206 mac->ops.set_lan_id(hw); 207 208 return (E1000_SUCCESS); 209 } 210 211 /* 212 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 213 * 214 * @hw: pointer to the HW structure 215 * 216 * Determines the LAN function id by reading memory-mapped registers 217 * and swaps the port value if requested. 218 */ 219 static void 220 e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 221 { 222 struct e1000_bus_info *bus = &hw->bus; 223 u32 reg; 224 225 /* 226 * The status register reports the correct function number 227 * for the device regardless of function swap state. 228 */ 229 reg = E1000_READ_REG(hw, E1000_STATUS); 230 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 231 } 232 233 /* 234 * e1000_set_lan_id_single_port - Set LAN id for a single port device 235 * @hw: pointer to the HW structure 236 * 237 * Sets the LAN function id to zero for a single port device. 238 */ 239 void 240 e1000_set_lan_id_single_port(struct e1000_hw *hw) 241 { 242 struct e1000_bus_info *bus = &hw->bus; 243 244 bus->func = 0; 245 } 246 247 /* 248 * e1000_clear_vfta_generic - Clear VLAN filter table 249 * @hw: pointer to the HW structure 250 * 251 * Clears the register array which contains the VLAN filter table by 252 * setting all the values to 0. 253 */ 254 void 255 e1000_clear_vfta_generic(struct e1000_hw *hw) 256 { 257 u32 offset; 258 259 DEBUGFUNC("e1000_clear_vfta_generic"); 260 261 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 262 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 263 E1000_WRITE_FLUSH(hw); 264 } 265 } 266 267 /* 268 * e1000_write_vfta_generic - Write value to VLAN filter table 269 * @hw: pointer to the HW structure 270 * @offset: register offset in VLAN filter table 271 * @value: register value written to VLAN filter table 272 * 273 * Writes value at the given offset in the register array which stores 274 * the VLAN filter table. 275 */ 276 void 277 e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 278 { 279 DEBUGFUNC("e1000_write_vfta_generic"); 280 281 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 282 E1000_WRITE_FLUSH(hw); 283 } 284 285 /* 286 * e1000_init_rx_addrs_generic - Initialize receive address's 287 * @hw: pointer to the HW structure 288 * @rar_count: receive address registers 289 * 290 * Setups the receive address registers by setting the base receive address 291 * register to the devices MAC address and clearing all the other receive 292 * address registers to 0. 293 */ 294 void 295 e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 296 { 297 u32 i; 298 u8 mac_addr[ETH_ADDR_LEN] = {0}; 299 300 DEBUGFUNC("e1000_init_rx_addrs_generic"); 301 302 /* Setup the receive address */ 303 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 304 305 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 306 307 /* Zero out the other (rar_entry_count - 1) receive addresses */ 308 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 309 for (i = 1; i < rar_count; i++) 310 hw->mac.ops.rar_set(hw, mac_addr, i); 311 } 312 313 /* 314 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 315 * @hw: pointer to the HW structure 316 * 317 * Checks the nvm for an alternate MAC address. An alternate MAC address 318 * can be setup by pre-boot software and must be treated like a permanent 319 * address and must override the actual permanent MAC address. If an 320 * alternate MAC address is found it is programmed into RAR0, replacing 321 * the permanent address that was installed into RAR0 by the Si on reset. 322 * This function will return SUCCESS unless it encounters an error while 323 * reading the EEPROM. 324 */ 325 s32 326 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 327 { 328 u32 i; 329 s32 ret_val = E1000_SUCCESS; 330 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 331 u8 alt_mac_addr[ETH_ADDR_LEN]; 332 333 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 334 335 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 336 &nvm_alt_mac_addr_offset); 337 if (ret_val) { 338 DEBUGOUT("NVM Read Error\n"); 339 goto out; 340 } 341 342 if (nvm_alt_mac_addr_offset == 0xFFFF) { 343 /* There is no Alternate MAC Address */ 344 goto out; 345 } 346 347 if (hw->bus.func == E1000_FUNC_1) 348 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 349 if (hw->bus.func == E1000_FUNC_2) 350 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 351 if (hw->bus.func == E1000_FUNC_3) 352 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 353 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 354 offset = nvm_alt_mac_addr_offset + (i >> 1); 355 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 356 if (ret_val) { 357 DEBUGOUT("NVM Read Error\n"); 358 goto out; 359 } 360 361 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 362 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 363 } 364 365 /* if multicast bit is set, the alternate address will not be used */ 366 if (alt_mac_addr[0] & 0x01) { 367 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 368 goto out; 369 } 370 371 /* 372 * We have a valid alternate MAC address, and we want to treat it the 373 * same as the normal permanent MAC address stored by the HW into the 374 * RAR. Do this by mapping this address into RAR0. 375 */ 376 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 377 378 out: 379 return (ret_val); 380 } 381 382 /* 383 * e1000_rar_set_generic - Set receive address register 384 * @hw: pointer to the HW structure 385 * @addr: pointer to the receive address 386 * @index: receive address array register 387 * 388 * Sets the receive address array register at index to the address passed 389 * in by addr. 390 */ 391 void 392 e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 393 { 394 u32 rar_low, rar_high; 395 396 DEBUGFUNC("e1000_rar_set_generic"); 397 398 /* 399 * HW expects these in little endian so we reverse the byte order 400 * from network order (big endian) to little endian 401 */ 402 rar_low = ((u32) addr[0] | 403 ((u32) addr[1] << 8) | 404 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 405 406 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 407 408 /* If MAC address zero, no need to set the AV bit */ 409 if (rar_low || rar_high) 410 rar_high |= E1000_RAH_AV; 411 412 /* 413 * Some bridges will combine consecutive 32-bit writes into 414 * a single burst write, which will malfunction on some parts. 415 * The flushes avoid this. 416 */ 417 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 418 E1000_WRITE_FLUSH(hw); 419 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 420 E1000_WRITE_FLUSH(hw); 421 } 422 423 /* 424 * e1000_mta_set_generic - Set multicast filter table address 425 * @hw: pointer to the HW structure 426 * @hash_value: determines the MTA register and bit to set 427 * 428 * The multicast table address is a register array of 32-bit registers. 429 * The hash_value is used to determine what register the bit is in, the 430 * current value is read, the new bit is OR'd in and the new value is 431 * written back into the register. 432 */ 433 void 434 e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 435 { 436 u32 hash_bit, hash_reg, mta; 437 438 DEBUGFUNC("e1000_mta_set_generic"); 439 /* 440 * The MTA is a register array of 32-bit registers. It is 441 * treated like an array of (32*mta_reg_count) bits. We want to 442 * set bit BitArray[hash_value]. So we figure out what register 443 * the bit is in, read it, OR in the new bit, then write 444 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 445 * mask to bits 31:5 of the hash value which gives us the 446 * register we're modifying. The hash bit within that register 447 * is determined by the lower 5 bits of the hash value. 448 */ 449 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 450 hash_bit = hash_value & 0x1F; 451 452 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 453 454 mta |= (1 << hash_bit); 455 456 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 457 E1000_WRITE_FLUSH(hw); 458 } 459 460 /* 461 * e1000_update_mc_addr_list_generic - Update Multicast addresses 462 * @hw: pointer to the HW structure 463 * @mc_addr_list: array of multicast addresses to program 464 * @mc_addr_count: number of multicast addresses to program 465 * 466 * Updates the Multicast Table Array. 467 * The caller must have a packed mc_addr_list of multicast addresses. 468 */ 469 void 470 e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 471 u8 *mc_addr_list, u32 mc_addr_count) 472 { 473 u32 hash_value, hash_bit, hash_reg; 474 int i; 475 476 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 477 478 /* clear mta_shadow */ 479 (void) memset(&hw->mac.mta_shadow, 0, sizeof (hw->mac.mta_shadow)); 480 481 /* update mta_shadow from mc_addr_list */ 482 for (i = 0; (u32) i < mc_addr_count; i++) { 483 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 484 485 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 486 hash_bit = hash_value & 0x1F; 487 488 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 489 mc_addr_list += (ETH_ADDR_LEN); 490 } 491 492 /* replace the entire MTA table */ 493 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 494 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 495 E1000_WRITE_FLUSH(hw); 496 } 497 498 /* 499 * e1000_hash_mc_addr_generic - Generate a multicast hash value 500 * @hw: pointer to the HW structure 501 * @mc_addr: pointer to a multicast address 502 * 503 * Generates a multicast address hash value which is used to determine 504 * the multicast filter table array address and new table value. See 505 * e1000_mta_set_generic() 506 */ 507 u32 508 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 509 { 510 u32 hash_value, hash_mask; 511 u8 bit_shift = 0; 512 513 DEBUGFUNC("e1000_hash_mc_addr_generic"); 514 515 /* Register count multiplied by bits per register */ 516 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 517 518 /* 519 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 520 * where 0xFF would still fall within the hash mask. 521 */ 522 while (hash_mask >> bit_shift != 0xFF) 523 bit_shift++; 524 525 /* 526 * The portion of the address that is used for the hash table 527 * is determined by the mc_filter_type setting. 528 * The algorithm is such that there is a total of 8 bits of shifting. 529 * The bit_shift for a mc_filter_type of 0 represents the number of 530 * left-shifts where the MSB of mc_addr[5] would still fall within 531 * the hash_mask. Case 0 does this exactly. Since there are a total 532 * of 8 bits of shifting, then mc_addr[4] will shift right the 533 * remaining number of bits. Thus 8 - bit_shift. The rest of the 534 * cases are a variation of this algorithm...essentially raising the 535 * number of bits to shift mc_addr[5] left, while still keeping the 536 * 8-bit shifting total. 537 * 538 * For example, given the following Destination MAC Address and an 539 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 540 * we can see that the bit_shift for case 0 is 4. These are the hash 541 * values resulting from each mc_filter_type... 542 * [0] [1] [2] [3] [4] [5] 543 * 01 AA 00 12 34 56 544 * LSB MSB 545 * 546 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 547 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 548 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 549 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 550 */ 551 switch (hw->mac.mc_filter_type) { 552 default: 553 case 0: 554 break; 555 case 1: 556 bit_shift += 1; 557 break; 558 case 2: 559 bit_shift += 2; 560 break; 561 case 3: 562 bit_shift += 4; 563 break; 564 } 565 566 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 567 (((u16) mc_addr[5]) << bit_shift))); 568 569 return (hash_value); 570 } 571 572 /* 573 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 574 * @hw: pointer to the HW structure 575 * 576 * Clears the base hardware counters by reading the counter registers. 577 */ 578 void 579 e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 580 { 581 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 582 583 (void) E1000_READ_REG(hw, E1000_CRCERRS); 584 (void) E1000_READ_REG(hw, E1000_SYMERRS); 585 (void) E1000_READ_REG(hw, E1000_MPC); 586 (void) E1000_READ_REG(hw, E1000_SCC); 587 (void) E1000_READ_REG(hw, E1000_ECOL); 588 (void) E1000_READ_REG(hw, E1000_MCC); 589 (void) E1000_READ_REG(hw, E1000_LATECOL); 590 (void) E1000_READ_REG(hw, E1000_COLC); 591 (void) E1000_READ_REG(hw, E1000_DC); 592 (void) E1000_READ_REG(hw, E1000_SEC); 593 (void) E1000_READ_REG(hw, E1000_RLEC); 594 (void) E1000_READ_REG(hw, E1000_XONRXC); 595 (void) E1000_READ_REG(hw, E1000_XONTXC); 596 (void) E1000_READ_REG(hw, E1000_XOFFRXC); 597 (void) E1000_READ_REG(hw, E1000_XOFFTXC); 598 (void) E1000_READ_REG(hw, E1000_FCRUC); 599 (void) E1000_READ_REG(hw, E1000_GPRC); 600 (void) E1000_READ_REG(hw, E1000_BPRC); 601 (void) E1000_READ_REG(hw, E1000_MPRC); 602 (void) E1000_READ_REG(hw, E1000_GPTC); 603 (void) E1000_READ_REG(hw, E1000_GORCL); 604 (void) E1000_READ_REG(hw, E1000_GORCH); 605 (void) E1000_READ_REG(hw, E1000_GOTCL); 606 (void) E1000_READ_REG(hw, E1000_GOTCH); 607 (void) E1000_READ_REG(hw, E1000_RNBC); 608 (void) E1000_READ_REG(hw, E1000_RUC); 609 (void) E1000_READ_REG(hw, E1000_RFC); 610 (void) E1000_READ_REG(hw, E1000_ROC); 611 (void) E1000_READ_REG(hw, E1000_RJC); 612 (void) E1000_READ_REG(hw, E1000_TORL); 613 (void) E1000_READ_REG(hw, E1000_TORH); 614 (void) E1000_READ_REG(hw, E1000_TOTL); 615 (void) E1000_READ_REG(hw, E1000_TOTH); 616 (void) E1000_READ_REG(hw, E1000_TPR); 617 (void) E1000_READ_REG(hw, E1000_TPT); 618 (void) E1000_READ_REG(hw, E1000_MPTC); 619 (void) E1000_READ_REG(hw, E1000_BPTC); 620 } 621 622 /* 623 * e1000_check_for_copper_link_generic - Check for link (Copper) 624 * @hw: pointer to the HW structure 625 * 626 * Checks to see of the link status of the hardware has changed. If a 627 * change in link status has been detected, then we read the PHY registers 628 * to get the current speed/duplex if link exists. 629 */ 630 s32 631 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 632 { 633 struct e1000_mac_info *mac = &hw->mac; 634 s32 ret_val; 635 bool link; 636 637 DEBUGFUNC("e1000_check_for_copper_link"); 638 639 /* 640 * We only want to go out to the PHY registers to see if Auto-Neg 641 * has completed and/or if our link status has changed. The 642 * get_link_status flag is set upon receiving a Link Status 643 * Change or Rx Sequence Error interrupt. 644 */ 645 if (!mac->get_link_status) { 646 ret_val = E1000_SUCCESS; 647 goto out; 648 } 649 650 /* 651 * First we want to see if the MII Status Register reports 652 * link. If so, then we want to get the current speed/duplex 653 * of the PHY. 654 */ 655 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 656 if (ret_val) 657 goto out; 658 659 if (!link) 660 goto out; /* No link detected */ 661 662 mac->get_link_status = false; 663 664 /* 665 * Check if there was DownShift, must be checked 666 * immediately after link-up 667 */ 668 (void) e1000_check_downshift_generic(hw); 669 670 /* 671 * If we are forcing speed/duplex, then we simply return since 672 * we have already determined whether we have link or not. 673 */ 674 if (!mac->autoneg) { 675 ret_val = -E1000_ERR_CONFIG; 676 goto out; 677 } 678 679 /* 680 * Auto-Neg is enabled. Auto Speed Detection takes care 681 * of MAC speed/duplex configuration. So we only need to 682 * configure Collision Distance in the MAC. 683 */ 684 e1000_config_collision_dist_generic(hw); 685 686 /* 687 * Configure Flow Control now that Auto-Neg has completed. 688 * First, we need to restore the desired flow control 689 * settings because we may have had to re-autoneg with a 690 * different link partner. 691 */ 692 ret_val = e1000_config_fc_after_link_up_generic(hw); 693 if (ret_val) 694 DEBUGOUT("Error configuring flow control\n"); 695 696 out: 697 return (ret_val); 698 } 699 700 /* 701 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 702 * @hw: pointer to the HW structure 703 * 704 * Checks for link up on the hardware. If link is not up and we have 705 * a signal, then we need to force link up. 706 */ 707 s32 708 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 709 { 710 struct e1000_mac_info *mac = &hw->mac; 711 u32 rxcw; 712 u32 ctrl; 713 u32 status; 714 s32 ret_val = E1000_SUCCESS; 715 716 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 717 718 ctrl = E1000_READ_REG(hw, E1000_CTRL); 719 status = E1000_READ_REG(hw, E1000_STATUS); 720 rxcw = E1000_READ_REG(hw, E1000_RXCW); 721 722 /* 723 * If we don't have link (auto-negotiation failed or link partner 724 * cannot auto-negotiate), the cable is plugged in (we have signal), 725 * and our link partner is not trying to auto-negotiate with us (we 726 * are receiving idles or data), we need to force link up. We also 727 * need to give auto-negotiation time to complete, in case the cable 728 * was just plugged in. The autoneg_failed flag does this. 729 */ 730 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 731 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 732 (!(rxcw & E1000_RXCW_C))) { 733 if (mac->autoneg_failed == 0) { 734 mac->autoneg_failed = 1; 735 goto out; 736 } 737 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 738 739 /* Disable auto-negotiation in the TXCW register */ 740 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 741 742 /* Force link-up and also force full-duplex. */ 743 ctrl = E1000_READ_REG(hw, E1000_CTRL); 744 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 745 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 746 747 /* Configure Flow Control after forcing link up. */ 748 ret_val = e1000_config_fc_after_link_up_generic(hw); 749 if (ret_val) { 750 DEBUGOUT("Error configuring flow control\n"); 751 goto out; 752 } 753 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 754 /* 755 * If we are forcing link and we are receiving /C/ ordered 756 * sets, re-enable auto-negotiation in the TXCW register 757 * and disable forced link in the Device Control register 758 * in an attempt to auto-negotiate with our link partner. 759 */ 760 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 761 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 762 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 763 764 mac->serdes_has_link = true; 765 } 766 767 out: 768 return (ret_val); 769 } 770 771 /* 772 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 773 * @hw: pointer to the HW structure 774 * 775 * Checks for link up on the hardware. If link is not up and we have 776 * a signal, then we need to force link up. 777 */ 778 s32 779 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 780 { 781 struct e1000_mac_info *mac = &hw->mac; 782 u32 rxcw; 783 u32 ctrl; 784 u32 status; 785 s32 ret_val = E1000_SUCCESS; 786 787 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 788 789 ctrl = E1000_READ_REG(hw, E1000_CTRL); 790 status = E1000_READ_REG(hw, E1000_STATUS); 791 rxcw = E1000_READ_REG(hw, E1000_RXCW); 792 793 /* 794 * If we don't have link (auto-negotiation failed or link partner 795 * cannot auto-negotiate), and our link partner is not trying to 796 * auto-negotiate with us (we are receiving idles or data), 797 * we need to force link up. We also need to give auto-negotiation 798 * time to complete. 799 */ 800 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 801 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 802 if (mac->autoneg_failed == 0) { 803 mac->autoneg_failed = 1; 804 goto out; 805 } 806 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 807 808 /* Disable auto-negotiation in the TXCW register */ 809 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 810 811 /* Force link-up and also force full-duplex. */ 812 ctrl = E1000_READ_REG(hw, E1000_CTRL); 813 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 814 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 815 816 /* Configure Flow Control after forcing link up. */ 817 ret_val = e1000_config_fc_after_link_up_generic(hw); 818 if (ret_val) { 819 DEBUGOUT("Error configuring flow control\n"); 820 goto out; 821 } 822 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 823 /* 824 * If we are forcing link and we are receiving /C/ ordered 825 * sets, re-enable auto-negotiation in the TXCW register 826 * and disable forced link in the Device Control register 827 * in an attempt to auto-negotiate with our link partner. 828 */ 829 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 830 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 831 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 832 833 mac->serdes_has_link = true; 834 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 835 /* 836 * If we force link for non-auto-negotiation switch, check 837 * link status based on MAC synchronization for internal 838 * serdes media type. 839 */ 840 /* SYNCH bit and IV bit are sticky. */ 841 usec_delay(10); 842 rxcw = E1000_READ_REG(hw, E1000_RXCW); 843 if (rxcw & E1000_RXCW_SYNCH) { 844 if (!(rxcw & E1000_RXCW_IV)) { 845 mac->serdes_has_link = true; 846 DEBUGOUT("SERDES: Link up - forced.\n"); 847 } 848 } else { 849 mac->serdes_has_link = false; 850 DEBUGOUT("SERDES: Link down - force failed.\n"); 851 } 852 } 853 854 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 855 status = E1000_READ_REG(hw, E1000_STATUS); 856 if (status & E1000_STATUS_LU) { 857 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 858 usec_delay(10); 859 rxcw = E1000_READ_REG(hw, E1000_RXCW); 860 if (rxcw & E1000_RXCW_SYNCH) { 861 if (!(rxcw & E1000_RXCW_IV)) { 862 mac->serdes_has_link = true; 863 DEBUGOUT("SERDES: Link up - autoneg " 864 "completed sucessfully.\n"); 865 } else { 866 mac->serdes_has_link = false; 867 DEBUGOUT("SERDES: Link down - invalid" 868 "codewords detected in autoneg.\n"); 869 } 870 } else { 871 mac->serdes_has_link = false; 872 DEBUGOUT("SERDES: Link down - no sync.\n"); 873 } 874 } else { 875 mac->serdes_has_link = false; 876 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 877 } 878 } 879 880 out: 881 return (ret_val); 882 } 883 884 /* 885 * e1000_setup_link_generic - Setup flow control and link settings 886 * @hw: pointer to the HW structure 887 * 888 * Determines which flow control settings to use, then configures flow 889 * control. Calls the appropriate media-specific link configuration 890 * function. Assuming the adapter has a valid link partner, a valid link 891 * should be established. Assumes the hardware has previously been reset 892 * and the transmitter and receiver are not enabled. 893 */ 894 s32 895 e1000_setup_link_generic(struct e1000_hw *hw) 896 { 897 s32 ret_val = E1000_SUCCESS; 898 899 DEBUGFUNC("e1000_setup_link_generic"); 900 901 /* 902 * In the case of the phy reset being blocked, we already have a link. 903 * We do not need to set it up again. 904 */ 905 if (hw->phy.ops.check_reset_block) 906 if (hw->phy.ops.check_reset_block(hw)) 907 goto out; 908 909 /* 910 * If requested flow control is set to default, set flow control 911 * based on the EEPROM flow control settings. 912 */ 913 if (hw->fc.requested_mode == e1000_fc_default) { 914 ret_val = e1000_set_default_fc_generic(hw); 915 if (ret_val) 916 goto out; 917 } 918 919 /* 920 * Save off the requested flow control mode for use later. Depending 921 * on the link partner's capabilities, we may or may not use this mode. 922 */ 923 hw->fc.current_mode = hw->fc.requested_mode; 924 925 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 926 hw->fc.current_mode); 927 928 /* Call the necessary media_type subroutine to configure the link. */ 929 ret_val = hw->mac.ops.setup_physical_interface(hw); 930 if (ret_val) 931 goto out; 932 933 /* 934 * Initialize the flow control address, type, and PAUSE timer 935 * registers to their default values. This is done even if flow 936 * control is disabled, because it does not hurt anything to 937 * initialize these registers. 938 */ 939 DEBUGOUT("Initializing the Flow Control address,type and timer regs\n"); 940 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 941 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 942 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 943 944 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 945 946 ret_val = e1000_set_fc_watermarks_generic(hw); 947 948 out: 949 return (ret_val); 950 } 951 952 /* 953 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 954 * @hw: pointer to the HW structure 955 * 956 * Configures collision distance and flow control for fiber and serdes 957 * links. Upon successful setup, poll for link. 958 */ 959 s32 960 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 961 { 962 u32 ctrl; 963 s32 ret_val = E1000_SUCCESS; 964 965 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 966 967 ctrl = E1000_READ_REG(hw, E1000_CTRL); 968 969 /* Take the link out of reset */ 970 ctrl &= ~E1000_CTRL_LRST; 971 972 e1000_config_collision_dist_generic(hw); 973 974 ret_val = e1000_commit_fc_settings_generic(hw); 975 if (ret_val) 976 goto out; 977 978 /* 979 * Since auto-negotiation is enabled, take the link out of reset (the 980 * link will be in reset, because we previously reset the chip). This 981 * will restart auto-negotiation. If auto-negotiation is successful 982 * then the link-up status bit will be set and the flow control enable 983 * bits (RFCE and TFCE) will be set according to their negotiated value. 984 */ 985 DEBUGOUT("Auto-negotiation enabled\n"); 986 987 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 988 E1000_WRITE_FLUSH(hw); 989 msec_delay(1); 990 991 /* 992 * For these adapters, the SW definable pin 1 is set when the optics 993 * detect a signal. If we have a signal, then poll for a "Link-Up" 994 * indication. 995 */ 996 if (hw->phy.media_type == e1000_media_type_internal_serdes || 997 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 998 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 999 } else { 1000 DEBUGOUT("No signal detected\n"); 1001 } 1002 1003 out: 1004 return (ret_val); 1005 } 1006 1007 /* 1008 * e1000_config_collision_dist_generic - Configure collision distance 1009 * @hw: pointer to the HW structure 1010 * 1011 * Configures the collision distance to the default value and is used 1012 * during link setup. Currently no func pointer exists and all 1013 * implementations are handled in the generic version of this function. 1014 */ 1015 void 1016 e1000_config_collision_dist_generic(struct e1000_hw *hw) 1017 { 1018 u32 tctl; 1019 1020 DEBUGFUNC("e1000_config_collision_dist_generic"); 1021 1022 tctl = E1000_READ_REG(hw, E1000_TCTL); 1023 1024 tctl &= ~E1000_TCTL_COLD; 1025 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1026 1027 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1028 E1000_WRITE_FLUSH(hw); 1029 } 1030 1031 /* 1032 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1033 * @hw: pointer to the HW structure 1034 * 1035 * Polls for link up by reading the status register, if link fails to come 1036 * up with auto-negotiation, then the link is forced if a signal is detected. 1037 */ 1038 s32 1039 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1040 { 1041 struct e1000_mac_info *mac = &hw->mac; 1042 u32 i, status; 1043 s32 ret_val = E1000_SUCCESS; 1044 1045 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1046 1047 /* 1048 * If we have a signal (the cable is plugged in, or assumed true for 1049 * serdes media) then poll for a "Link-Up" indication in the Device 1050 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1051 * seconds (Auto-negotiation should complete in less than 500 1052 * milliseconds even if the other end is doing it in SW). 1053 */ 1054 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1055 msec_delay(10); 1056 status = E1000_READ_REG(hw, E1000_STATUS); 1057 if (status & E1000_STATUS_LU) 1058 break; 1059 } 1060 if (i == FIBER_LINK_UP_LIMIT) { 1061 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1062 mac->autoneg_failed = 1; 1063 /* 1064 * AutoNeg failed to achieve a link, so we'll call 1065 * mac->check_for_link. This routine will force the 1066 * link up if we detect a signal. This will allow us to 1067 * communicate with non-autonegotiating link partners. 1068 */ 1069 ret_val = hw->mac.ops.check_for_link(hw); 1070 if (ret_val) { 1071 DEBUGOUT("Error while checking for link\n"); 1072 goto out; 1073 } 1074 mac->autoneg_failed = 0; 1075 } else { 1076 mac->autoneg_failed = 0; 1077 DEBUGOUT("Valid Link Found\n"); 1078 } 1079 1080 out: 1081 return (ret_val); 1082 } 1083 1084 /* 1085 * e1000_commit_fc_settings_generic - Configure flow control 1086 * @hw: pointer to the HW structure 1087 * 1088 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1089 * base on the flow control settings in e1000_mac_info. 1090 */ 1091 s32 1092 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1093 { 1094 struct e1000_mac_info *mac = &hw->mac; 1095 u32 txcw; 1096 s32 ret_val = E1000_SUCCESS; 1097 1098 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1099 1100 /* 1101 * Check for a software override of the flow control settings, and 1102 * setup the device accordingly. If auto-negotiation is enabled, then 1103 * software will have to set the "PAUSE" bits to the correct value in 1104 * the Transmit Config Word Register (TXCW) and re-start auto- 1105 * negotiation. However, if auto-negotiation is disabled, then 1106 * software will have to manually configure the two flow control enable 1107 * bits in the CTRL register. 1108 * 1109 * The possible values of the "fc" parameter are: 1110 * 0: Flow control is completely disabled 1111 * 1: Rx flow control is enabled (we can receive pause frames, 1112 * but not send pause frames). 1113 * 2: Tx flow control is enabled (we can send pause frames but we 1114 * do not support receiving pause frames). 1115 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1116 */ 1117 switch (hw->fc.current_mode) { 1118 case e1000_fc_none: 1119 /* Flow control completely disabled by a software over-ride. */ 1120 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1121 break; 1122 case e1000_fc_rx_pause: 1123 /* 1124 * Rx Flow control is enabled and Tx Flow control is disabled 1125 * by a software over-ride. Since there really isn't a way to 1126 * advertise that we are capable of Rx Pause ONLY, we will 1127 * advertise that we support both symmetric and asymmetric RX 1128 * PAUSE. Later, we will disable the adapter's ability to send 1129 * PAUSE frames. 1130 */ 1131 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1132 break; 1133 case e1000_fc_tx_pause: 1134 /* 1135 * Tx Flow control is enabled, and Rx Flow control is disabled, 1136 * by a software over-ride. 1137 */ 1138 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1139 break; 1140 case e1000_fc_full: 1141 /* 1142 * Flow control (both Rx and Tx) is enabled by a software 1143 * over-ride. 1144 */ 1145 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1146 break; 1147 default: 1148 DEBUGOUT("Flow control param set incorrectly\n"); 1149 ret_val = -E1000_ERR_CONFIG; 1150 goto out; 1151 } 1152 1153 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1154 mac->txcw = txcw; 1155 1156 out: 1157 return (ret_val); 1158 } 1159 1160 /* 1161 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1162 * @hw: pointer to the HW structure 1163 * 1164 * Sets the flow control high/low threshold (watermark) registers. If 1165 * flow control XON frame transmission is enabled, then set XON frame 1166 * transmission as well. 1167 */ 1168 s32 1169 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1170 { 1171 s32 ret_val = E1000_SUCCESS; 1172 u32 fcrtl = 0, fcrth = 0; 1173 1174 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1175 1176 /* 1177 * Set the flow control receive threshold registers. Normally, 1178 * these registers will be set to a default threshold that may be 1179 * adjusted later by the driver's runtime code. However, if the 1180 * ability to transmit pause frames is not enabled, then these 1181 * registers will be set to 0. 1182 */ 1183 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1184 /* 1185 * We need to set up the Receive Threshold high and low water 1186 * marks as well as (optionally) enabling the transmission of 1187 * XON frames. 1188 */ 1189 fcrtl = hw->fc.low_water; 1190 if (hw->fc.send_xon) 1191 fcrtl |= E1000_FCRTL_XONE; 1192 1193 fcrth = hw->fc.high_water; 1194 } 1195 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1196 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1197 1198 return (ret_val); 1199 } 1200 1201 /* 1202 * e1000_set_default_fc_generic - Set flow control default values 1203 * @hw: pointer to the HW structure 1204 * 1205 * Read the EEPROM for the default values for flow control and store the 1206 * values. 1207 */ 1208 s32 1209 e1000_set_default_fc_generic(struct e1000_hw *hw) 1210 { 1211 s32 ret_val = E1000_SUCCESS; 1212 u16 nvm_data; 1213 1214 DEBUGFUNC("e1000_set_default_fc_generic"); 1215 1216 /* 1217 * Read and store word 0x0F of the EEPROM. This word contains bits 1218 * that determine the hardware's default PAUSE (flow control) mode, 1219 * a bit that determines whether the HW defaults to enabling or 1220 * disabling auto-negotiation, and the direction of the 1221 * SW defined pins. If there is no SW over-ride of the flow 1222 * control setting, then the variable hw->fc will 1223 * be initialized based on a value in the EEPROM. 1224 */ 1225 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1226 1227 if (ret_val) { 1228 DEBUGOUT("NVM Read Error\n"); 1229 goto out; 1230 } 1231 1232 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1233 hw->fc.requested_mode = e1000_fc_none; 1234 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1235 NVM_WORD0F_ASM_DIR) 1236 hw->fc.requested_mode = e1000_fc_tx_pause; 1237 else 1238 hw->fc.requested_mode = e1000_fc_full; 1239 1240 out: 1241 return (ret_val); 1242 } 1243 1244 /* 1245 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1246 * @hw: pointer to the HW structure 1247 * 1248 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1249 * device control register to reflect the adapter settings. TFCE and RFCE 1250 * need to be explicitly set by software when a copper PHY is used because 1251 * autonegotiation is managed by the PHY rather than the MAC. Software must 1252 * also configure these bits when link is forced on a fiber connection. 1253 */ 1254 s32 1255 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1256 { 1257 u32 ctrl; 1258 s32 ret_val = E1000_SUCCESS; 1259 1260 DEBUGFUNC("e1000_force_mac_fc_generic"); 1261 1262 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1263 1264 /* 1265 * Because we didn't get link via the internal auto-negotiation 1266 * mechanism (we either forced link or we got link via PHY 1267 * auto-neg), we have to manually enable/disable transmit an 1268 * receive flow control. 1269 * 1270 * The "Case" statement below enables/disable flow control 1271 * according to the "hw->fc.current_mode" parameter. 1272 * 1273 * The possible values of the "fc" parameter are: 1274 * 0: Flow control is completely disabled 1275 * 1: Rx flow control is enabled (we can receive pause 1276 * frames but not send pause frames). 1277 * 2: Tx flow control is enabled (we can send pause frames 1278 * frames but we do not receive pause frames). 1279 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1280 * other: No other values should be possible at this point. 1281 */ 1282 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1283 1284 switch (hw->fc.current_mode) { 1285 case e1000_fc_none: 1286 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1287 break; 1288 case e1000_fc_rx_pause: 1289 ctrl &= (~E1000_CTRL_TFCE); 1290 ctrl |= E1000_CTRL_RFCE; 1291 break; 1292 case e1000_fc_tx_pause: 1293 ctrl &= (~E1000_CTRL_RFCE); 1294 ctrl |= E1000_CTRL_TFCE; 1295 break; 1296 case e1000_fc_full: 1297 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1298 break; 1299 default: 1300 DEBUGOUT("Flow control param set incorrectly\n"); 1301 ret_val = -E1000_ERR_CONFIG; 1302 goto out; 1303 } 1304 1305 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1306 1307 out: 1308 return (ret_val); 1309 } 1310 1311 /* 1312 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1313 * @hw: pointer to the HW structure 1314 * 1315 * Checks the status of auto-negotiation after link up to ensure that the 1316 * speed and duplex were not forced. If the link needed to be forced, then 1317 * flow control needs to be forced also. If auto-negotiation is enabled 1318 * and did not fail, then we configure flow control based on our link 1319 * partner. 1320 */ 1321 s32 1322 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1323 { 1324 struct e1000_mac_info *mac = &hw->mac; 1325 s32 ret_val = E1000_SUCCESS; 1326 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1327 u16 speed, duplex; 1328 1329 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1330 1331 /* 1332 * Check for the case where we have fiber media and auto-neg failed 1333 * so we had to force link. In this case, we need to force the 1334 * configuration of the MAC to match the "fc" parameter. 1335 */ 1336 if (mac->autoneg_failed) { 1337 if (hw->phy.media_type == e1000_media_type_fiber || 1338 hw->phy.media_type == e1000_media_type_internal_serdes) 1339 ret_val = e1000_force_mac_fc_generic(hw); 1340 } else { 1341 if (hw->phy.media_type == e1000_media_type_copper) 1342 ret_val = e1000_force_mac_fc_generic(hw); 1343 } 1344 1345 if (ret_val) { 1346 DEBUGOUT("Error forcing flow control settings\n"); 1347 goto out; 1348 } 1349 1350 /* 1351 * Check for the case where we have copper media and auto-neg is 1352 * enabled. In this case, we need to check and see if Auto-Neg 1353 * has completed, and if so, how the PHY and link partner has 1354 * flow control configured. 1355 */ 1356 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1357 /* 1358 * Read the MII Status Register and check to see if AutoNeg 1359 * has completed. We read this twice because this reg has 1360 * some "sticky" (latched) bits. 1361 */ 1362 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1363 if (ret_val) 1364 goto out; 1365 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1366 if (ret_val) 1367 goto out; 1368 1369 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1370 DEBUGOUT("Copper PHY and Auto Neg " 1371 "has not completed.\n"); 1372 goto out; 1373 } 1374 1375 /* 1376 * The AutoNeg process has completed, so we now need to 1377 * read both the Auto Negotiation Advertisement 1378 * Register (Address 4) and the Auto_Negotiation Base 1379 * Page Ability Register (Address 5) to determine how 1380 * flow control was negotiated. 1381 */ 1382 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1383 &mii_nway_adv_reg); 1384 if (ret_val) 1385 goto out; 1386 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1387 &mii_nway_lp_ability_reg); 1388 if (ret_val) 1389 goto out; 1390 1391 /* 1392 * Two bits in the Auto Negotiation Advertisement Register 1393 * (Address 4) and two bits in the Auto Negotiation Base 1394 * Page Ability Register (Address 5) determine flow control 1395 * for both the PHY and the link partner. The following 1396 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1397 * 1999, describes these PAUSE resolution bits and how flow 1398 * control is determined based upon these settings. 1399 * NOTE: DC = Don't Care 1400 * 1401 * LOCAL DEVICE | LINK PARTNER 1402 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1403 * ------|---------|-------|---------|-------------------- 1404 * 0 | 0 | DC | DC | e1000_fc_none 1405 * 0 | 1 | 0 | DC | e1000_fc_none 1406 * 0 | 1 | 1 | 0 | e1000_fc_none 1407 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1408 * 1 | 0 | 0 | DC | e1000_fc_none 1409 * 1 | DC | 1 | DC | e1000_fc_full 1410 * 1 | 1 | 0 | 0 | e1000_fc_none 1411 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1412 * 1413 * Are both PAUSE bits set to 1? If so, this implies 1414 * Symmetric Flow Control is enabled at both ends. The 1415 * ASM_DIR bits are irrelevant per the spec. 1416 * 1417 * For Symmetric Flow Control: 1418 * 1419 * LOCAL DEVICE | LINK PARTNER 1420 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1421 * ------|---------|-------|---------|-------------------- 1422 * 1 | DC | 1 | DC | E1000_fc_full 1423 * 1424 */ 1425 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1426 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1427 /* 1428 * Now we need to check if the user selected Rx ONLY 1429 * of pause frames. In this case, we had to advertise 1430 * FULL flow control because we could not advertise RX 1431 * ONLY. Hence, we must now check to see if we need to 1432 * turn OFF the TRANSMISSION of PAUSE frames. 1433 */ 1434 if (hw->fc.requested_mode == e1000_fc_full) { 1435 hw->fc.current_mode = e1000_fc_full; 1436 DEBUGOUT("Flow Control = FULL.\r\n"); 1437 } else { 1438 hw->fc.current_mode = e1000_fc_rx_pause; 1439 DEBUGOUT("Flow Control = " 1440 "RX PAUSE frames only.\r\n"); 1441 } 1442 } 1443 /* 1444 * For receiving PAUSE frames ONLY. 1445 * 1446 * LOCAL DEVICE | LINK PARTNER 1447 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1448 * ------|---------|-------|---------|-------------------- 1449 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1450 */ 1451 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1452 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1453 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1454 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1455 hw->fc.current_mode = e1000_fc_tx_pause; 1456 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1457 } 1458 /* 1459 * For transmitting PAUSE frames ONLY. 1460 * 1461 * LOCAL DEVICE | LINK PARTNER 1462 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1463 * ------|---------|-------|---------|-------------------- 1464 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1465 */ 1466 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1467 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1468 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1469 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1470 hw->fc.current_mode = e1000_fc_rx_pause; 1471 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1472 } else { 1473 /* 1474 * Per the IEEE spec, at this point flow control 1475 * should be disabled. 1476 */ 1477 hw->fc.current_mode = e1000_fc_none; 1478 DEBUGOUT("Flow Control = NONE.\r\n"); 1479 } 1480 1481 /* 1482 * Now we need to do one last check... If we auto- 1483 * negotiated to HALF DUPLEX, flow control should not be 1484 * enabled per IEEE 802.3 spec. 1485 */ 1486 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1487 if (ret_val) { 1488 DEBUGOUT("Error getting link speed and duplex\n"); 1489 goto out; 1490 } 1491 1492 if (duplex == HALF_DUPLEX) 1493 hw->fc.current_mode = e1000_fc_none; 1494 1495 /* 1496 * Now we call a subroutine to actually force the MAC 1497 * controller to use the correct flow control settings. 1498 */ 1499 ret_val = e1000_force_mac_fc_generic(hw); 1500 if (ret_val) { 1501 DEBUGOUT("Error forcing flow control settings\n"); 1502 goto out; 1503 } 1504 } 1505 1506 out: 1507 return (ret_val); 1508 } 1509 1510 /* 1511 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1512 * @hw: pointer to the HW structure 1513 * @speed: stores the current speed 1514 * @duplex: stores the current duplex 1515 * 1516 * Read the status register for the current speed/duplex and store the current 1517 * speed and duplex for copper connections. 1518 */ 1519 s32 1520 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1521 u16 *duplex) 1522 { 1523 u32 status; 1524 1525 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1526 1527 status = E1000_READ_REG(hw, E1000_STATUS); 1528 if (status & E1000_STATUS_SPEED_1000) { 1529 *speed = SPEED_1000; 1530 DEBUGOUT("1000 Mbs, "); 1531 } else if (status & E1000_STATUS_SPEED_100) { 1532 *speed = SPEED_100; 1533 DEBUGOUT("100 Mbs, "); 1534 } else { 1535 *speed = SPEED_10; 1536 DEBUGOUT("10 Mbs, "); 1537 } 1538 1539 if (status & E1000_STATUS_FD) { 1540 *duplex = FULL_DUPLEX; 1541 DEBUGOUT("Full Duplex\n"); 1542 } else { 1543 *duplex = HALF_DUPLEX; 1544 DEBUGOUT("Half Duplex\n"); 1545 } 1546 1547 return (E1000_SUCCESS); 1548 } 1549 1550 /* 1551 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1552 * @hw: pointer to the HW structure 1553 * @speed: stores the current speed 1554 * @duplex: stores the current duplex 1555 * 1556 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1557 * for fiber/serdes links. 1558 */ 1559 s32 1560 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1561 u16 *speed, u16 *duplex) 1562 { 1563 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1564 UNREFERENCED_1PARAMETER(hw); 1565 1566 *speed = SPEED_1000; 1567 *duplex = FULL_DUPLEX; 1568 1569 return (E1000_SUCCESS); 1570 } 1571 1572 /* 1573 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1574 * @hw: pointer to the HW structure 1575 * 1576 * Acquire the HW semaphore to access the PHY or NVM 1577 */ 1578 s32 1579 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1580 { 1581 u32 swsm; 1582 s32 ret_val = E1000_SUCCESS; 1583 s32 timeout = hw->nvm.word_size + 1; 1584 s32 i = 0; 1585 1586 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1587 1588 /* Get the SW semaphore */ 1589 while (i < timeout) { 1590 swsm = E1000_READ_REG(hw, E1000_SWSM); 1591 if (!(swsm & E1000_SWSM_SMBI)) 1592 break; 1593 1594 usec_delay(50); 1595 i++; 1596 } 1597 1598 if (i == timeout) { 1599 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1600 ret_val = -E1000_ERR_NVM; 1601 goto out; 1602 } 1603 1604 /* Get the FW semaphore. */ 1605 for (i = 0; i < timeout; i++) { 1606 swsm = E1000_READ_REG(hw, E1000_SWSM); 1607 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1608 1609 /* Semaphore acquired if bit latched */ 1610 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1611 break; 1612 1613 usec_delay(50); 1614 } 1615 1616 if (i == timeout) { 1617 /* Release semaphores */ 1618 e1000_put_hw_semaphore_generic(hw); 1619 DEBUGOUT("Driver can't access the NVM\n"); 1620 ret_val = -E1000_ERR_NVM; 1621 goto out; 1622 } 1623 1624 out: 1625 return (ret_val); 1626 } 1627 1628 /* 1629 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1630 * @hw: pointer to the HW structure 1631 * 1632 * Release hardware semaphore used to access the PHY or NVM 1633 */ 1634 void 1635 e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1636 { 1637 u32 swsm; 1638 1639 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1640 1641 swsm = E1000_READ_REG(hw, E1000_SWSM); 1642 1643 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1644 1645 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1646 } 1647 1648 /* 1649 * e1000_get_auto_rd_done_generic - Check for auto read completion 1650 * @hw: pointer to the HW structure 1651 * 1652 * Check EEPROM for Auto Read done bit. 1653 */ 1654 s32 1655 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1656 { 1657 s32 i = 0; 1658 s32 ret_val = E1000_SUCCESS; 1659 1660 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1661 1662 while (i < AUTO_READ_DONE_TIMEOUT) { 1663 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1664 break; 1665 msec_delay(1); 1666 i++; 1667 } 1668 1669 if (i == AUTO_READ_DONE_TIMEOUT) { 1670 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1671 ret_val = -E1000_ERR_RESET; 1672 goto out; 1673 } 1674 1675 out: 1676 return (ret_val); 1677 } 1678 1679 /* 1680 * e1000_valid_led_default_generic - Verify a valid default LED config 1681 * @hw: pointer to the HW structure 1682 * @data: pointer to the NVM (EEPROM) 1683 * 1684 * Read the EEPROM for the current default LED configuration. If the 1685 * LED configuration is not valid, set to a valid LED configuration. 1686 */ 1687 s32 1688 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1689 { 1690 s32 ret_val; 1691 1692 DEBUGFUNC("e1000_valid_led_default_generic"); 1693 1694 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1695 if (ret_val) { 1696 DEBUGOUT("NVM Read Error\n"); 1697 goto out; 1698 } 1699 1700 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1701 *data = ID_LED_DEFAULT; 1702 1703 out: 1704 return (ret_val); 1705 } 1706 1707 /* 1708 * e1000_id_led_init_generic - 1709 * @hw: pointer to the HW structure 1710 * 1711 */ 1712 s32 1713 e1000_id_led_init_generic(struct e1000_hw *hw) 1714 { 1715 struct e1000_mac_info *mac = &hw->mac; 1716 s32 ret_val; 1717 const u32 ledctl_mask = 0x000000FF; 1718 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1719 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1720 u16 data, i, temp; 1721 const u16 led_mask = 0x0F; 1722 1723 DEBUGFUNC("e1000_id_led_init_generic"); 1724 1725 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1726 if (ret_val) 1727 goto out; 1728 1729 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1730 mac->ledctl_mode1 = mac->ledctl_default; 1731 mac->ledctl_mode2 = mac->ledctl_default; 1732 1733 for (i = 0; i < 4; i++) { 1734 temp = (data >> (i << 2)) & led_mask; 1735 switch (temp) { 1736 case ID_LED_ON1_DEF2: 1737 case ID_LED_ON1_ON2: 1738 case ID_LED_ON1_OFF2: 1739 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1740 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1741 break; 1742 case ID_LED_OFF1_DEF2: 1743 case ID_LED_OFF1_ON2: 1744 case ID_LED_OFF1_OFF2: 1745 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1746 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1747 break; 1748 default: 1749 /* Do nothing */ 1750 break; 1751 } 1752 switch (temp) { 1753 case ID_LED_DEF1_ON2: 1754 case ID_LED_ON1_ON2: 1755 case ID_LED_OFF1_ON2: 1756 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1757 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1758 break; 1759 case ID_LED_DEF1_OFF2: 1760 case ID_LED_ON1_OFF2: 1761 case ID_LED_OFF1_OFF2: 1762 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1763 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1764 break; 1765 default: 1766 /* Do nothing */ 1767 break; 1768 } 1769 } 1770 1771 out: 1772 return (ret_val); 1773 } 1774 1775 /* 1776 * e1000_setup_led_generic - Configures SW controllable LED 1777 * @hw: pointer to the HW structure 1778 * 1779 * This prepares the SW controllable LED for use and saves the current state 1780 * of the LED so it can be later restored. 1781 */ 1782 s32 1783 e1000_setup_led_generic(struct e1000_hw *hw) 1784 { 1785 u32 ledctl; 1786 s32 ret_val = E1000_SUCCESS; 1787 1788 DEBUGFUNC("e1000_setup_led_generic"); 1789 1790 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1791 ret_val = -E1000_ERR_CONFIG; 1792 goto out; 1793 } 1794 1795 if (hw->phy.media_type == e1000_media_type_fiber) { 1796 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1797 hw->mac.ledctl_default = ledctl; 1798 /* Turn off LED0 */ 1799 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1800 E1000_LEDCTL_LED0_BLINK | 1801 E1000_LEDCTL_LED0_MODE_MASK); 1802 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1803 E1000_LEDCTL_LED0_MODE_SHIFT); 1804 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1805 } else if (hw->phy.media_type == e1000_media_type_copper) { 1806 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1807 } 1808 1809 out: 1810 return (ret_val); 1811 } 1812 1813 /* 1814 * e1000_cleanup_led_generic - Set LED config to default operation 1815 * @hw: pointer to the HW structure 1816 * 1817 * Remove the current LED configuration and set the LED configuration 1818 * to the default value, saved from the EEPROM. 1819 */ 1820 s32 1821 e1000_cleanup_led_generic(struct e1000_hw *hw) 1822 { 1823 s32 ret_val = E1000_SUCCESS; 1824 1825 DEBUGFUNC("e1000_cleanup_led_generic"); 1826 1827 if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) { 1828 ret_val = -E1000_ERR_CONFIG; 1829 goto out; 1830 } 1831 1832 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1833 1834 out: 1835 return (ret_val); 1836 } 1837 1838 /* 1839 * e1000_blink_led_generic - Blink LED 1840 * @hw: pointer to the HW structure 1841 * 1842 * Blink the LEDs which are set to be on. 1843 */ 1844 s32 1845 e1000_blink_led_generic(struct e1000_hw *hw) 1846 { 1847 u32 ledctl_blink = 0; 1848 u32 i; 1849 1850 DEBUGFUNC("e1000_blink_led_generic"); 1851 1852 if (hw->phy.media_type == e1000_media_type_fiber) { 1853 /* always blink LED0 for PCI-E fiber */ 1854 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1855 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1856 } else { 1857 /* 1858 * set the blink bit for each LED that's "on" (0x0E) 1859 * in ledctl_mode2 1860 */ 1861 ledctl_blink = hw->mac.ledctl_mode2; 1862 for (i = 0; i < 4; i++) 1863 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1864 E1000_LEDCTL_MODE_LED_ON) 1865 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1866 (i * 8)); 1867 } 1868 1869 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1870 1871 return (E1000_SUCCESS); 1872 } 1873 1874 /* 1875 * e1000_led_on_generic - Turn LED on 1876 * @hw: pointer to the HW structure 1877 * 1878 * Turn LED on. 1879 */ 1880 s32 1881 e1000_led_on_generic(struct e1000_hw *hw) 1882 { 1883 u32 ctrl; 1884 1885 DEBUGFUNC("e1000_led_on_generic"); 1886 1887 switch (hw->phy.media_type) { 1888 case e1000_media_type_fiber: 1889 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1890 ctrl &= ~E1000_CTRL_SWDPIN0; 1891 ctrl |= E1000_CTRL_SWDPIO0; 1892 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1893 break; 1894 case e1000_media_type_copper: 1895 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1896 break; 1897 default: 1898 break; 1899 } 1900 1901 return (E1000_SUCCESS); 1902 } 1903 1904 /* 1905 * e1000_led_off_generic - Turn LED off 1906 * @hw: pointer to the HW structure 1907 * 1908 * Turn LED off. 1909 */ 1910 s32 1911 e1000_led_off_generic(struct e1000_hw *hw) 1912 { 1913 u32 ctrl; 1914 1915 DEBUGFUNC("e1000_led_off_generic"); 1916 1917 switch (hw->phy.media_type) { 1918 case e1000_media_type_fiber: 1919 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1920 ctrl |= E1000_CTRL_SWDPIN0; 1921 ctrl |= E1000_CTRL_SWDPIO0; 1922 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1923 break; 1924 case e1000_media_type_copper: 1925 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1926 break; 1927 default: 1928 break; 1929 } 1930 1931 return (E1000_SUCCESS); 1932 } 1933 1934 /* 1935 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1936 * @hw: pointer to the HW structure 1937 * @no_snoop: bitmap of snoop events 1938 * 1939 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1940 */ 1941 void 1942 e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1943 { 1944 u32 gcr; 1945 1946 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1947 1948 if (hw->bus.type != e1000_bus_type_pci_express) 1949 return; 1950 1951 if (no_snoop) { 1952 gcr = E1000_READ_REG(hw, E1000_GCR); 1953 gcr &= ~(PCIE_NO_SNOOP_ALL); 1954 gcr |= no_snoop; 1955 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1956 } 1957 } 1958 1959 /* 1960 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1961 * @hw: pointer to the HW structure 1962 * 1963 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 1964 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1965 * the master requests to be disabled. 1966 * 1967 * Disables PCI-Express master access and verifies there are no pending 1968 * requests. 1969 */ 1970 s32 1971 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 1972 { 1973 u32 ctrl; 1974 s32 timeout = MASTER_DISABLE_TIMEOUT; 1975 s32 ret_val = E1000_SUCCESS; 1976 1977 DEBUGFUNC("e1000_disable_pcie_master_generic"); 1978 1979 if (hw->bus.type != e1000_bus_type_pci_express) 1980 goto out; 1981 1982 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1983 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1984 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1985 1986 while (timeout) { 1987 if (!(E1000_READ_REG(hw, E1000_STATUS) & 1988 E1000_STATUS_GIO_MASTER_ENABLE)) 1989 break; 1990 usec_delay(100); 1991 timeout--; 1992 } 1993 1994 if (!timeout) { 1995 DEBUGOUT("Master requests are pending.\n"); 1996 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 1997 goto out; 1998 } 1999 2000 out: 2001 return (ret_val); 2002 } 2003 2004 /* 2005 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2006 * @hw: pointer to the HW structure 2007 * 2008 * Reset the Adaptive Interframe Spacing throttle to default values. 2009 */ 2010 void 2011 e1000_reset_adaptive_generic(struct e1000_hw *hw) 2012 { 2013 struct e1000_mac_info *mac = &hw->mac; 2014 2015 DEBUGFUNC("e1000_reset_adaptive_generic"); 2016 2017 if (!mac->adaptive_ifs) { 2018 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2019 return; 2020 } 2021 2022 mac->current_ifs_val = 0; 2023 mac->ifs_min_val = IFS_MIN; 2024 mac->ifs_max_val = IFS_MAX; 2025 mac->ifs_step_size = IFS_STEP; 2026 mac->ifs_ratio = IFS_RATIO; 2027 2028 mac->in_ifs_mode = false; 2029 E1000_WRITE_REG(hw, E1000_AIT, 0); 2030 } 2031 2032 /* 2033 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2034 * @hw: pointer to the HW structure 2035 * 2036 * Update the Adaptive Interframe Spacing Throttle value based on the 2037 * time between transmitted packets and time between collisions. 2038 */ 2039 void 2040 e1000_update_adaptive_generic(struct e1000_hw *hw) 2041 { 2042 struct e1000_mac_info *mac = &hw->mac; 2043 2044 DEBUGFUNC("e1000_update_adaptive_generic"); 2045 2046 if (!mac->adaptive_ifs) { 2047 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2048 return; 2049 } 2050 2051 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2052 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2053 mac->in_ifs_mode = true; 2054 if (mac->current_ifs_val < mac->ifs_max_val) { 2055 if (!mac->current_ifs_val) 2056 mac->current_ifs_val = mac->ifs_min_val; 2057 else 2058 mac->current_ifs_val += 2059 mac->ifs_step_size; 2060 E1000_WRITE_REG(hw, E1000_AIT, 2061 mac->current_ifs_val); 2062 } 2063 } 2064 } else { 2065 if (mac->in_ifs_mode && 2066 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2067 mac->current_ifs_val = 0; 2068 mac->in_ifs_mode = false; 2069 E1000_WRITE_REG(hw, E1000_AIT, 0); 2070 } 2071 } 2072 } 2073 2074 /* 2075 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2076 * @hw: pointer to the HW structure 2077 * 2078 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2079 * set, which is forced to MDI mode only. 2080 */ 2081 static s32 2082 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2083 { 2084 s32 ret_val = E1000_SUCCESS; 2085 2086 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2087 2088 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2089 DEBUGOUT("Invalid MDI setting detected\n"); 2090 hw->phy.mdix = 1; 2091 ret_val = -E1000_ERR_CONFIG; 2092 goto out; 2093 } 2094 2095 out: 2096 return (ret_val); 2097 } 2098 2099 /* 2100 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2101 * @hw: pointer to the HW structure 2102 * @reg: 32bit register offset such as E1000_SCTL 2103 * @offset: register offset to write to 2104 * @data: data to write at register offset 2105 * 2106 * Writes an address/data control type register. There are several of these 2107 * and they all have the format address << 8 | data and bit 31 is polled for 2108 * completion. 2109 */ 2110 s32 2111 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2112 u32 offset, u8 data) 2113 { 2114 u32 i, regvalue = 0; 2115 s32 ret_val = E1000_SUCCESS; 2116 2117 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2118 2119 /* Set up the address and data */ 2120 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2121 E1000_WRITE_REG(hw, reg, regvalue); 2122 2123 /* Poll the ready bit to see if the MDI read completed */ 2124 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2125 usec_delay(5); 2126 regvalue = E1000_READ_REG(hw, reg); 2127 if (regvalue & E1000_GEN_CTL_READY) 2128 break; 2129 } 2130 if (!(regvalue & E1000_GEN_CTL_READY)) { 2131 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2132 ret_val = -E1000_ERR_PHY; 2133 goto out; 2134 } 2135 2136 out: 2137 return (ret_val); 2138 } 2139
Indexes created Wed Feb 10 09:32:22 UTC 2010
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