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      1 /*
      2  * CDDL HEADER START
      3  *
      4  * Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
      5  * The contents of this file are subject to the terms of the
      6  * Common Development and Distribution License (the "License").
      7  * You may not use this file except in compliance with the License.
      8  *
      9  * You can obtain a copy of the license at:
     10  *	http://www.opensolaris.org/os/licensing.
     11  * See the License for the specific language governing permissions
     12  * and limitations under the License.
     13  *
     14  * When using or redistributing this file, you may do so under the
     15  * License only. No other modification of this header is permitted.
     16  *
     17  * If applicable, add the following below this CDDL HEADER, with the
     18  * fields enclosed by brackets "[]" replaced with your own identifying
     19  * information: Portions Copyright [yyyy] [name of copyright owner]
     20  *
     21  * CDDL HEADER END
     22  */
     23 
     24 /*
     25  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
     26  * Use is subject to license terms of the CDDL.
     27  */
     28 
     29 /* IntelVersion: 1.398 v2008-10-7 */
     30 
     31 #ifndef _IGB_HW_H
     32 #define	_IGB_HW_H
     33 
     34 #ifdef __cplusplus
     35 extern "C" {
     36 #endif
     37 
     38 #include "igb_osdep.h"
     39 #include "igb_regs.h"
     40 #include "igb_defines.h"
     41 
     42 struct e1000_hw;
     43 
     44 #define	E1000_DEV_ID_82576			0x10C9
     45 #define	E1000_DEV_ID_82576_FIBER		0x10E6
     46 #define	E1000_DEV_ID_82576_SERDES		0x10E7
     47 #define	E1000_DEV_ID_82576_QUAD_COPPER		0x10E8
     48 #define	E1000_DEV_ID_82576_NS			0x150A
     49 #define	E1000_DEV_ID_82576_SERDES_QUAD		0x150D
     50 #define	E1000_DEV_ID_82575EB_COPPER		0x10A7
     51 #define	E1000_DEV_ID_82575EB_FIBER_SERDES	0x10A9
     52 #define	E1000_DEV_ID_82575GB_QUAD_COPPER	0x10D6
     53 
     54 #define	E1000_REVISION_0 0
     55 #define	E1000_REVISION_1 1
     56 #define	E1000_REVISION_2 2
     57 #define	E1000_REVISION_3 3
     58 #define	E1000_REVISION_4 4
     59 
     60 #define	E1000_FUNC_0	0
     61 #define	E1000_FUNC_1	1
     62 #define	E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0
     63 #define	E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3
     64 
     65 enum e1000_mac_type {
     66 	e1000_undefined = 0,
     67 	e1000_82575,
     68 	e1000_82576,
     69 	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
     70 };
     71 
     72 enum e1000_media_type {
     73 	e1000_media_type_unknown = 0,
     74 	e1000_media_type_copper = 1,
     75 	e1000_media_type_fiber = 2,
     76 	e1000_media_type_internal_serdes = 3,
     77 	e1000_num_media_types
     78 };
     79 
     80 enum e1000_nvm_type {
     81 	e1000_nvm_unknown = 0,
     82 	e1000_nvm_none,
     83 	e1000_nvm_eeprom_spi,
     84 	e1000_nvm_eeprom_microwire,
     85 	e1000_nvm_flash_hw,
     86 	e1000_nvm_flash_sw
     87 };
     88 
     89 enum e1000_nvm_override {
     90 	e1000_nvm_override_none = 0,
     91 	e1000_nvm_override_spi_small,
     92 	e1000_nvm_override_spi_large,
     93 	e1000_nvm_override_microwire_small,
     94 	e1000_nvm_override_microwire_large
     95 };
     96 
     97 enum e1000_phy_type {
     98 	e1000_phy_unknown = 0,
     99 	e1000_phy_none,
    100 	e1000_phy_m88,
    101 	e1000_phy_igp,
    102 	e1000_phy_igp_2,
    103 	e1000_phy_gg82563,
    104 	e1000_phy_igp_3,
    105 	e1000_phy_ife,
    106 	e1000_phy_vf
    107 };
    108 
    109 enum e1000_bus_type {
    110 	e1000_bus_type_unknown = 0,
    111 	e1000_bus_type_pci,
    112 	e1000_bus_type_pcix,
    113 	e1000_bus_type_pci_express,
    114 	e1000_bus_type_reserved
    115 };
    116 
    117 enum e1000_bus_speed {
    118 	e1000_bus_speed_unknown = 0,
    119 	e1000_bus_speed_33,
    120 	e1000_bus_speed_66,
    121 	e1000_bus_speed_100,
    122 	e1000_bus_speed_120,
    123 	e1000_bus_speed_133,
    124 	e1000_bus_speed_2500,
    125 	e1000_bus_speed_5000,
    126 	e1000_bus_speed_reserved
    127 };
    128 
    129 enum e1000_bus_width {
    130 	e1000_bus_width_unknown = 0,
    131 	e1000_bus_width_pcie_x1,
    132 	e1000_bus_width_pcie_x2,
    133 	e1000_bus_width_pcie_x4 = 4,
    134 	e1000_bus_width_pcie_x8 = 8,
    135 	e1000_bus_width_32,
    136 	e1000_bus_width_64,
    137 	e1000_bus_width_reserved
    138 };
    139 
    140 enum e1000_1000t_rx_status {
    141 	e1000_1000t_rx_status_not_ok = 0,
    142 	e1000_1000t_rx_status_ok,
    143 	e1000_1000t_rx_status_undefined = 0xFF
    144 };
    145 
    146 enum e1000_rev_polarity {
    147 	e1000_rev_polarity_normal = 0,
    148 	e1000_rev_polarity_reversed,
    149 	e1000_rev_polarity_undefined = 0xFF
    150 };
    151 
    152 enum e1000_fc_mode {
    153 	e1000_fc_none = 0,
    154 	e1000_fc_rx_pause,
    155 	e1000_fc_tx_pause,
    156 	e1000_fc_full,
    157 	e1000_fc_default = 0xFF
    158 };
    159 
    160 enum e1000_ms_type {
    161 	e1000_ms_hw_default = 0,
    162 	e1000_ms_force_master,
    163 	e1000_ms_force_slave,
    164 	e1000_ms_auto
    165 };
    166 
    167 enum e1000_smart_speed {
    168 	e1000_smart_speed_default = 0,
    169 	e1000_smart_speed_on,
    170 	e1000_smart_speed_off
    171 };
    172 
    173 enum e1000_serdes_link_state {
    174 	e1000_serdes_link_down = 0,
    175 	e1000_serdes_link_autoneg_progress,
    176 	e1000_serdes_link_autoneg_complete,
    177 	e1000_serdes_link_forced_up
    178 };
    179 
    180 /* Receive Descriptor */
    181 struct e1000_rx_desc {
    182 	__le64 buffer_addr; /* Address of the descriptor's data buffer */
    183 	__le16 length;	/* Length of data DMAed into data buffer */
    184 	__le16 csum;	/* Packet checksum */
    185 	u8  status;	/* Descriptor status */
    186 	u8  errors;	/* Descriptor Errors */
    187 	__le16 special;
    188 };
    189 
    190 /* Receive Descriptor - Extended */
    191 union e1000_rx_desc_extended {
    192 	struct {
    193 		__le64 buffer_addr;
    194 		__le64 reserved;
    195 	} read;
    196 	struct {
    197 		struct {
    198 			__le32 mrq;	/* Multiple Rx Queues */
    199 			union {
    200 				__le32 rss;	/* RSS Hash */
    201 				struct {
    202 					__le16 ip_id;  /* IP id */
    203 					__le16 csum;   /* Packet Checksum */
    204 				} csum_ip;
    205 			} hi_dword;
    206 		} lower;
    207 		struct {
    208 			__le32 status_error;	/* ext status/error */
    209 			__le16 length;
    210 			__le16 vlan;		/* VLAN tag */
    211 		} upper;
    212 	} wb;  /* writeback */
    213 };
    214 
    215 #define	MAX_PS_BUFFERS 4
    216 /* Receive Descriptor - Packet Split */
    217 union e1000_rx_desc_packet_split {
    218 	struct {
    219 		/* one buffer for protocol header(s), three data buffers */
    220 		__le64 buffer_addr[MAX_PS_BUFFERS];
    221 	} read;
    222 	struct {
    223 		struct {
    224 			__le32 mrq;	/* Multiple Rx Queues */
    225 			union {
    226 				__le32 rss;	/* RSS Hash */
    227 				struct {
    228 					__le16 ip_id;	/* IP id */
    229 					__le16 csum;	/* Packet Checksum */
    230 				} csum_ip;
    231 			} hi_dword;
    232 		} lower;
    233 		struct {
    234 			__le32 status_error;	/* ext status/error */
    235 			__le16 length0;	/* length of buffer 0 */
    236 			__le16 vlan;	/* VLAN tag */
    237 		} middle;
    238 		struct {
    239 			__le16 header_status;
    240 			__le16 length[3];	/* length of buffers 1-3 */
    241 		} upper;
    242 		__le64 reserved;
    243 	} wb; /* writeback */
    244 };
    245 
    246 /* Transmit Descriptor */
    247 struct e1000_tx_desc {
    248 	__le64 buffer_addr;	/* Address of the descriptor's data buffer */
    249 	union {
    250 		__le32 data;
    251 		struct {
    252 			__le16 length;	/* Data buffer length */
    253 			u8 cso;		/* Checksum offset */
    254 			u8 cmd;		/* Descriptor control */
    255 		} flags;
    256 	} lower;
    257 	union {
    258 		__le32 data;
    259 		struct {
    260 			u8 status;	/* Descriptor status */
    261 			u8 css;		/* Checksum start */
    262 			__le16 special;
    263 		} fields;
    264 	} upper;
    265 };
    266 
    267 /* Offload Context Descriptor */
    268 struct e1000_context_desc {
    269 	union {
    270 		__le32 ip_config;
    271 		struct {
    272 			u8 ipcss;	/* IP checksum start */
    273 			u8 ipcso;	/* IP checksum offset */
    274 			__le16 ipcse;	/* IP checksum end */
    275 		} ip_fields;
    276 	} lower_setup;
    277 	union {
    278 		__le32 tcp_config;
    279 		struct {
    280 			u8 tucss;	/* TCP checksum start */
    281 			u8 tucso;	/* TCP checksum offset */
    282 			__le16 tucse;	/* TCP checksum end */
    283 		} tcp_fields;
    284 	} upper_setup;
    285 	__le32 cmd_and_length;
    286 	union {
    287 		__le32 data;
    288 		struct {
    289 			u8 status;	/* Descriptor status */
    290 			u8 hdr_len;	/* Header length */
    291 			__le16 mss;	/* Maximum segment size */
    292 		} fields;
    293 	} tcp_seg_setup;
    294 };
    295 
    296 /* Offload data descriptor */
    297 struct e1000_data_desc {
    298 	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
    299 	union {
    300 		__le32 data;
    301 		struct {
    302 			__le16 length;    /* Data buffer length */
    303 			u8 typ_len_ext;
    304 			u8 cmd;
    305 		} flags;
    306 	} lower;
    307 	union {
    308 		__le32 data;
    309 		struct {
    310 			u8 status;	/* Descriptor status */
    311 			u8 popts;	/* Packet Options */
    312 			__le16 special;
    313 		} fields;
    314 	} upper;
    315 };
    316 
    317 /* Statistics counters collected by the MAC */
    318 struct e1000_hw_stats {
    319 	u64 crcerrs;
    320 	u64 algnerrc;
    321 	u64 symerrs;
    322 	u64 rxerrc;
    323 	u64 mpc;
    324 	u64 scc;
    325 	u64 ecol;
    326 	u64 mcc;
    327 	u64 latecol;
    328 	u64 colc;
    329 	u64 dc;
    330 	u64 tncrs;
    331 	u64 sec;
    332 	u64 cexterr;
    333 	u64 rlec;
    334 	u64 xonrxc;
    335 	u64 xontxc;
    336 	u64 xoffrxc;
    337 	u64 xofftxc;
    338 	u64 fcruc;
    339 	u64 prc64;
    340 	u64 prc127;
    341 	u64 prc255;
    342 	u64 prc511;
    343 	u64 prc1023;
    344 	u64 prc1522;
    345 	u64 gprc;
    346 	u64 bprc;
    347 	u64 mprc;
    348 	u64 gptc;
    349 	u64 gorc;
    350 	u64 gotc;
    351 	u64 rnbc;
    352 	u64 ruc;
    353 	u64 rfc;
    354 	u64 roc;
    355 	u64 rjc;
    356 	u64 mgprc;
    357 	u64 mgpdc;
    358 	u64 mgptc;
    359 	u64 tor;
    360 	u64 tot;
    361 	u64 tpr;
    362 	u64 tpt;
    363 	u64 ptc64;
    364 	u64 ptc127;
    365 	u64 ptc255;
    366 	u64 ptc511;
    367 	u64 ptc1023;
    368 	u64 ptc1522;
    369 	u64 mptc;
    370 	u64 bptc;
    371 	u64 tsctc;
    372 	u64 tsctfc;
    373 	u64 iac;
    374 	u64 icrxptc;
    375 	u64 icrxatc;
    376 	u64 ictxptc;
    377 	u64 ictxatc;
    378 	u64 ictxqec;
    379 	u64 ictxqmtc;
    380 	u64 icrxdmtc;
    381 	u64 icrxoc;
    382 	u64 cbtmpc;
    383 	u64 htdpmc;
    384 	u64 cbrdpc;
    385 	u64 cbrmpc;
    386 	u64 rpthc;
    387 	u64 hgptc;
    388 	u64 htcbdpc;
    389 	u64 hgorc;
    390 	u64 hgotc;
    391 	u64 lenerrs;
    392 	u64 scvpc;
    393 	u64 hrmpc;
    394 	u64 doosync;
    395 };
    396 
    397 struct e1000_phy_stats {
    398 	u32 idle_errors;
    399 	u32 receive_errors;
    400 };
    401 
    402 struct e1000_host_mng_dhcp_cookie {
    403 	u32 signature;
    404 	u8  status;
    405 	u8  reserved0;
    406 	u16 vlan_id;
    407 	u32 reserved1;
    408 	u16 reserved2;
    409 	u8  reserved3;
    410 	u8  checksum;
    411 };
    412 
    413 /* Host Interface "Rev 1" */
    414 struct e1000_host_command_header {
    415 	u8 command_id;
    416 	u8 command_length;
    417 	u8 command_options;
    418 	u8 checksum;
    419 };
    420 
    421 #define	E1000_HI_MAX_DATA_LENGTH	252
    422 struct e1000_host_command_info {
    423 	struct e1000_host_command_header command_header;
    424 	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
    425 };
    426 
    427 /* Host Interface "Rev 2" */
    428 struct e1000_host_mng_command_header {
    429 	u8  command_id;
    430 	u8  checksum;
    431 	u16 reserved1;
    432 	u16 reserved2;
    433 	u16 command_length;
    434 };
    435 
    436 #define	E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
    437 struct e1000_host_mng_command_info {
    438 	struct e1000_host_mng_command_header command_header;
    439 	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
    440 };
    441 
    442 #include "igb_mac.h"
    443 #include "igb_phy.h"
    444 #include "igb_nvm.h"
    445 #include "igb_manage.h"
    446 
    447 struct e1000_mac_operations {
    448 	/* Function pointers for the MAC. */
    449 	s32  (*init_params)(struct e1000_hw *);
    450 	s32  (*id_led_init)(struct e1000_hw *);
    451 	s32  (*blink_led)(struct e1000_hw *);
    452 	s32  (*check_for_link)(struct e1000_hw *);
    453 	bool (*check_mng_mode)(struct e1000_hw *hw);
    454 	s32  (*cleanup_led)(struct e1000_hw *);
    455 	void (*clear_hw_cntrs)(struct e1000_hw *);
    456 	void (*clear_vfta)(struct e1000_hw *);
    457 	s32  (*get_bus_info)(struct e1000_hw *);
    458 	void (*set_lan_id)(struct e1000_hw *);
    459 	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
    460 	s32  (*led_on)(struct e1000_hw *);
    461 	s32  (*led_off)(struct e1000_hw *);
    462 	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
    463 	s32  (*reset_hw)(struct e1000_hw *);
    464 	s32  (*init_hw)(struct e1000_hw *);
    465 	void (*shutdown_serdes)(struct e1000_hw *);
    466 	s32  (*setup_link)(struct e1000_hw *);
    467 	s32  (*setup_physical_interface)(struct e1000_hw *);
    468 	s32  (*setup_led)(struct e1000_hw *);
    469 	void (*write_vfta)(struct e1000_hw *, u32, u32);
    470 	void (*mta_set)(struct e1000_hw *, u32);
    471 	void (*config_collision_dist)(struct e1000_hw *);
    472 	void (*rar_set)(struct e1000_hw *, u8*, u32);
    473 	s32  (*read_mac_addr)(struct e1000_hw *);
    474 	s32  (*validate_mdi_setting)(struct e1000_hw *);
    475 	s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
    476 	s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
    477 	    struct e1000_host_mng_command_header *);
    478 	s32  (*mng_enable_host_if)(struct e1000_hw *);
    479 	s32  (*wait_autoneg)(struct e1000_hw *);
    480 };
    481 
    482 struct e1000_phy_operations {
    483 	s32  (*init_params)(struct e1000_hw *);
    484 	s32  (*acquire)(struct e1000_hw *);
    485 	s32  (*check_polarity)(struct e1000_hw *);
    486 	s32  (*check_reset_block)(struct e1000_hw *);
    487 	s32  (*commit)(struct e1000_hw *);
    488 	s32  (*force_speed_duplex)(struct e1000_hw *);
    489 	s32  (*get_cfg_done)(struct e1000_hw *hw);
    490 	s32  (*get_cable_length)(struct e1000_hw *);
    491 	s32  (*get_info)(struct e1000_hw *);
    492 	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
    493 	void (*release)(struct e1000_hw *);
    494 	s32  (*reset)(struct e1000_hw *);
    495 	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
    496 	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
    497 	s32  (*write_reg)(struct e1000_hw *, u32, u16);
    498 	void (*power_up)(struct e1000_hw *);
    499 	void (*power_down)(struct e1000_hw *);
    500 };
    501 
    502 struct e1000_nvm_operations {
    503 	s32  (*init_params)(struct e1000_hw *);
    504 	s32  (*acquire)(struct e1000_hw *);
    505 	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
    506 	void (*release)(struct e1000_hw *);
    507 	void (*reload)(struct e1000_hw *);
    508 	s32  (*update)(struct e1000_hw *);
    509 	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
    510 	s32  (*validate)(struct e1000_hw *);
    511 	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
    512 };
    513 
    514 struct e1000_mac_info {
    515 	struct e1000_mac_operations ops;
    516 	u8 addr[6];
    517 	u8 perm_addr[6];
    518 
    519 	enum e1000_mac_type type;
    520 
    521 	u32 collision_delta;
    522 	u32 ledctl_default;
    523 	u32 ledctl_mode1;
    524 	u32 ledctl_mode2;
    525 	u32 mc_filter_type;
    526 	u32 tx_packet_delta;
    527 	u32 txcw;
    528 
    529 	u16 current_ifs_val;
    530 	u16 ifs_max_val;
    531 	u16 ifs_min_val;
    532 	u16 ifs_ratio;
    533 	u16 ifs_step_size;
    534 	u16 mta_reg_count;
    535 
    536 	/* Maximum size of the MTA register table in all supported adapters */
    537 #define	MAX_MTA_REG 128
    538 	u32 mta_shadow[MAX_MTA_REG];
    539 	u16 rar_entry_count;
    540 
    541 	u8  forced_speed_duplex;
    542 
    543 	bool adaptive_ifs;
    544 	bool arc_subsystem_valid;
    545 	bool asf_firmware_present;
    546 	bool autoneg;
    547 	bool autoneg_failed;
    548 	bool get_link_status;
    549 	bool in_ifs_mode;
    550 	enum e1000_serdes_link_state serdes_link_state;
    551 	bool serdes_has_link;
    552 	bool tx_pkt_filtering;
    553 };
    554 
    555 struct e1000_phy_info {
    556 	struct e1000_phy_operations ops;
    557 	enum e1000_phy_type type;
    558 
    559 	enum e1000_1000t_rx_status local_rx;
    560 	enum e1000_1000t_rx_status remote_rx;
    561 	enum e1000_ms_type ms_type;
    562 	enum e1000_ms_type original_ms_type;
    563 	enum e1000_rev_polarity cable_polarity;
    564 	enum e1000_smart_speed smart_speed;
    565 
    566 	u32 addr;
    567 	u32 id;
    568 	u32 reset_delay_us; /* in usec */
    569 	u32 revision;
    570 
    571 	enum e1000_media_type media_type;
    572 
    573 	u16 autoneg_advertised;
    574 	u16 autoneg_mask;
    575 	u16 cable_length;
    576 	u16 max_cable_length;
    577 	u16 min_cable_length;
    578 
    579 	u8 mdix;
    580 
    581 	bool disable_polarity_correction;
    582 	bool is_mdix;
    583 	bool polarity_correction;
    584 	bool reset_disable;
    585 	bool speed_downgraded;
    586 	bool autoneg_wait_to_complete;
    587 };
    588 
    589 struct e1000_nvm_info {
    590 	struct e1000_nvm_operations ops;
    591 	enum e1000_nvm_type type;
    592 	enum e1000_nvm_override override;
    593 
    594 	u32 flash_bank_size;
    595 	u32 flash_base_addr;
    596 
    597 	u16 word_size;
    598 	u16 delay_usec;
    599 	u16 address_bits;
    600 	u16 opcode_bits;
    601 	u16 page_size;
    602 };
    603 
    604 struct e1000_bus_info {
    605 	enum e1000_bus_type type;
    606 	enum e1000_bus_speed speed;
    607 	enum e1000_bus_width width;
    608 
    609 	u16 func;
    610 	u16 pci_cmd_word;
    611 };
    612 
    613 struct e1000_fc_info {
    614 	u32 high_water;		/* Flow control high-water mark */
    615 	u32 low_water;		/* Flow control low-water mark */
    616 	u16 pause_time;		/* Flow control pause timer */
    617 	bool send_xon;		/* Flow control send XON */
    618 	bool strict_ieee;	/* Strict IEEE mode */
    619 	enum e1000_fc_mode current_mode; /* FC mode in effect */
    620 	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
    621 };
    622 
    623 struct e1000_dev_spec_82575 {
    624 	bool sgmii_active;
    625 	bool global_device_reset;
    626 };
    627 
    628 struct e1000_dev_spec_vf {
    629 	u32	vf_number;
    630 	u32	v2p_mailbox;
    631 };
    632 
    633 struct e1000_hw {
    634 	void *back;
    635 
    636 	u8 *hw_addr;
    637 	u8 *flash_address;
    638 	unsigned long io_base;
    639 
    640 	struct e1000_mac_info  mac;
    641 	struct e1000_fc_info   fc;
    642 	struct e1000_phy_info  phy;
    643 	struct e1000_nvm_info  nvm;
    644 	struct e1000_bus_info  bus;
    645 	struct e1000_host_mng_dhcp_cookie mng_cookie;
    646 
    647 	union {
    648 		struct e1000_dev_spec_82575	_82575;
    649 		struct e1000_dev_spec_vf	vf;
    650 	} dev_spec;
    651 
    652 	u16 device_id;
    653 	u16 subsystem_vendor_id;
    654 	u16 subsystem_device_id;
    655 	u16 vendor_id;
    656 
    657 	u8  revision_id;
    658 };
    659 
    660 #include "igb_82575.h"
    661 
    662 /* These functions must be implemented by drivers */
    663 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
    664 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
    665 
    666 #ifdef __cplusplus
    667 }
    668 #endif
    669 
    670 #endif	/* _IGB_HW_H */
    671