1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.444 scm_100809_154340 */ 30 31 #ifndef _IGB_HW_H 32 #define _IGB_HW_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include "igb_osdep.h" 39 #include "igb_regs.h" 40 #include "igb_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82576 0x10C9 45 #define E1000_DEV_ID_82576_FIBER 0x10E6 46 #define E1000_DEV_ID_82576_SERDES 0x10E7 47 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 48 #define E1000_DEV_ID_82576_NS 0x150A 49 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 50 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 51 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 52 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 53 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 54 #define E1000_DEV_ID_82580_COPPER 0x150E 55 #define E1000_DEV_ID_82580_FIBER 0x150F 56 #define E1000_DEV_ID_82580_SERDES 0x1510 57 #define E1000_DEV_ID_82580_SGMII 0x1511 58 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 59 60 #define E1000_REVISION_0 0 61 #define E1000_REVISION_1 1 62 #define E1000_REVISION_2 2 63 #define E1000_REVISION_3 3 64 #define E1000_REVISION_4 4 65 66 #define E1000_FUNC_0 0 67 #define E1000_FUNC_1 1 68 #define E1000_FUNC_2 2 69 #define E1000_FUNC_3 3 70 71 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 72 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 73 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 74 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 75 76 enum e1000_mac_type { 77 e1000_undefined = 0, 78 e1000_82575, 79 e1000_82576, 80 e1000_82580, 81 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 82 }; 83 84 enum e1000_media_type { 85 e1000_media_type_unknown = 0, 86 e1000_media_type_copper = 1, 87 e1000_media_type_fiber = 2, 88 e1000_media_type_internal_serdes = 3, 89 e1000_num_media_types 90 }; 91 92 enum e1000_nvm_type { 93 e1000_nvm_unknown = 0, 94 e1000_nvm_none, 95 e1000_nvm_eeprom_spi, 96 e1000_nvm_eeprom_microwire, 97 e1000_nvm_flash_hw, 98 e1000_nvm_flash_sw 99 }; 100 101 enum e1000_nvm_override { 102 e1000_nvm_override_none = 0, 103 e1000_nvm_override_spi_small, 104 e1000_nvm_override_spi_large, 105 e1000_nvm_override_microwire_small, 106 e1000_nvm_override_microwire_large 107 }; 108 109 enum e1000_phy_type { 110 e1000_phy_unknown = 0, 111 e1000_phy_none, 112 e1000_phy_m88, 113 e1000_phy_igp, 114 e1000_phy_igp_2, 115 e1000_phy_gg82563, 116 e1000_phy_igp_3, 117 e1000_phy_ife, 118 e1000_phy_82580, 119 e1000_phy_vf 120 }; 121 122 enum e1000_bus_type { 123 e1000_bus_type_unknown = 0, 124 e1000_bus_type_pci, 125 e1000_bus_type_pcix, 126 e1000_bus_type_pci_express, 127 e1000_bus_type_reserved 128 }; 129 130 enum e1000_bus_speed { 131 e1000_bus_speed_unknown = 0, 132 e1000_bus_speed_33, 133 e1000_bus_speed_66, 134 e1000_bus_speed_100, 135 e1000_bus_speed_120, 136 e1000_bus_speed_133, 137 e1000_bus_speed_2500, 138 e1000_bus_speed_5000, 139 e1000_bus_speed_reserved 140 }; 141 142 enum e1000_bus_width { 143 e1000_bus_width_unknown = 0, 144 e1000_bus_width_pcie_x1, 145 e1000_bus_width_pcie_x2, 146 e1000_bus_width_pcie_x4 = 4, 147 e1000_bus_width_pcie_x8 = 8, 148 e1000_bus_width_32, 149 e1000_bus_width_64, 150 e1000_bus_width_reserved 151 }; 152 153 enum e1000_1000t_rx_status { 154 e1000_1000t_rx_status_not_ok = 0, 155 e1000_1000t_rx_status_ok, 156 e1000_1000t_rx_status_undefined = 0xFF 157 }; 158 159 enum e1000_rev_polarity { 160 e1000_rev_polarity_normal = 0, 161 e1000_rev_polarity_reversed, 162 e1000_rev_polarity_undefined = 0xFF 163 }; 164 165 enum e1000_fc_mode { 166 e1000_fc_none = 0, 167 e1000_fc_rx_pause, 168 e1000_fc_tx_pause, 169 e1000_fc_full, 170 e1000_fc_default = 0xFF 171 }; 172 173 enum e1000_ms_type { 174 e1000_ms_hw_default = 0, 175 e1000_ms_force_master, 176 e1000_ms_force_slave, 177 e1000_ms_auto 178 }; 179 180 enum e1000_smart_speed { 181 e1000_smart_speed_default = 0, 182 e1000_smart_speed_on, 183 e1000_smart_speed_off 184 }; 185 186 enum e1000_serdes_link_state { 187 e1000_serdes_link_down = 0, 188 e1000_serdes_link_autoneg_progress, 189 e1000_serdes_link_autoneg_complete, 190 e1000_serdes_link_forced_up 191 }; 192 193 /* Receive Descriptor */ 194 struct e1000_rx_desc { 195 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 196 __le16 length; /* Length of data DMAed into data buffer */ 197 __le16 csum; /* Packet checksum */ 198 u8 status; /* Descriptor status */ 199 u8 errors; /* Descriptor Errors */ 200 __le16 special; 201 }; 202 203 /* Receive Descriptor - Extended */ 204 union e1000_rx_desc_extended { 205 struct { 206 __le64 buffer_addr; 207 __le64 reserved; 208 } read; 209 struct { 210 struct { 211 __le32 mrq; /* Multiple Rx Queues */ 212 union { 213 __le32 rss; /* RSS Hash */ 214 struct { 215 __le16 ip_id; /* IP id */ 216 __le16 csum; /* Packet Checksum */ 217 } csum_ip; 218 } hi_dword; 219 } lower; 220 struct { 221 __le32 status_error; /* ext status/error */ 222 __le16 length; 223 __le16 vlan; /* VLAN tag */ 224 } upper; 225 } wb; /* writeback */ 226 }; 227 228 #define MAX_PS_BUFFERS 4 229 /* Receive Descriptor - Packet Split */ 230 union e1000_rx_desc_packet_split { 231 struct { 232 /* one buffer for protocol header(s), three data buffers */ 233 __le64 buffer_addr[MAX_PS_BUFFERS]; 234 } read; 235 struct { 236 struct { 237 __le32 mrq; /* Multiple Rx Queues */ 238 union { 239 __le32 rss; /* RSS Hash */ 240 struct { 241 __le16 ip_id; /* IP id */ 242 __le16 csum; /* Packet Checksum */ 243 } csum_ip; 244 } hi_dword; 245 } lower; 246 struct { 247 __le32 status_error; /* ext status/error */ 248 __le16 length0; /* length of buffer 0 */ 249 __le16 vlan; /* VLAN tag */ 250 } middle; 251 struct { 252 __le16 header_status; 253 __le16 length[3]; /* length of buffers 1-3 */ 254 } upper; 255 __le64 reserved; 256 } wb; /* writeback */ 257 }; 258 259 /* Transmit Descriptor */ 260 struct e1000_tx_desc { 261 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 262 union { 263 __le32 data; 264 struct { 265 __le16 length; /* Data buffer length */ 266 u8 cso; /* Checksum offset */ 267 u8 cmd; /* Descriptor control */ 268 } flags; 269 } lower; 270 union { 271 __le32 data; 272 struct { 273 u8 status; /* Descriptor status */ 274 u8 css; /* Checksum start */ 275 __le16 special; 276 } fields; 277 } upper; 278 }; 279 280 /* Offload Context Descriptor */ 281 struct e1000_context_desc { 282 union { 283 __le32 ip_config; 284 struct { 285 u8 ipcss; /* IP checksum start */ 286 u8 ipcso; /* IP checksum offset */ 287 __le16 ipcse; /* IP checksum end */ 288 } ip_fields; 289 } lower_setup; 290 union { 291 __le32 tcp_config; 292 struct { 293 u8 tucss; /* TCP checksum start */ 294 u8 tucso; /* TCP checksum offset */ 295 __le16 tucse; /* TCP checksum end */ 296 } tcp_fields; 297 } upper_setup; 298 __le32 cmd_and_length; 299 union { 300 __le32 data; 301 struct { 302 u8 status; /* Descriptor status */ 303 u8 hdr_len; /* Header length */ 304 __le16 mss; /* Maximum segment size */ 305 } fields; 306 } tcp_seg_setup; 307 }; 308 309 /* Offload data descriptor */ 310 struct e1000_data_desc { 311 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 312 union { 313 __le32 data; 314 struct { 315 __le16 length; /* Data buffer length */ 316 u8 typ_len_ext; 317 u8 cmd; 318 } flags; 319 } lower; 320 union { 321 __le32 data; 322 struct { 323 u8 status; /* Descriptor status */ 324 u8 popts; /* Packet Options */ 325 __le16 special; 326 } fields; 327 } upper; 328 }; 329 330 /* Statistics counters collected by the MAC */ 331 struct e1000_hw_stats { 332 u64 crcerrs; 333 u64 algnerrc; 334 u64 symerrs; 335 u64 rxerrc; 336 u64 mpc; 337 u64 scc; 338 u64 ecol; 339 u64 mcc; 340 u64 latecol; 341 u64 colc; 342 u64 dc; 343 u64 tncrs; 344 u64 sec; 345 u64 cexterr; 346 u64 rlec; 347 u64 xonrxc; 348 u64 xontxc; 349 u64 xoffrxc; 350 u64 xofftxc; 351 u64 fcruc; 352 u64 prc64; 353 u64 prc127; 354 u64 prc255; 355 u64 prc511; 356 u64 prc1023; 357 u64 prc1522; 358 u64 gprc; 359 u64 bprc; 360 u64 mprc; 361 u64 gptc; 362 u64 gorc; 363 u64 gotc; 364 u64 rnbc; 365 u64 ruc; 366 u64 rfc; 367 u64 roc; 368 u64 rjc; 369 u64 mgprc; 370 u64 mgpdc; 371 u64 mgptc; 372 u64 tor; 373 u64 tot; 374 u64 tpr; 375 u64 tpt; 376 u64 ptc64; 377 u64 ptc127; 378 u64 ptc255; 379 u64 ptc511; 380 u64 ptc1023; 381 u64 ptc1522; 382 u64 mptc; 383 u64 bptc; 384 u64 tsctc; 385 u64 tsctfc; 386 u64 iac; 387 u64 icrxptc; 388 u64 icrxatc; 389 u64 ictxptc; 390 u64 ictxatc; 391 u64 ictxqec; 392 u64 ictxqmtc; 393 u64 icrxdmtc; 394 u64 icrxoc; 395 u64 cbtmpc; 396 u64 htdpmc; 397 u64 cbrdpc; 398 u64 cbrmpc; 399 u64 rpthc; 400 u64 hgptc; 401 u64 htcbdpc; 402 u64 hgorc; 403 u64 hgotc; 404 u64 lenerrs; 405 u64 scvpc; 406 u64 hrmpc; 407 u64 doosync; 408 }; 409 410 struct e1000_phy_stats { 411 u32 idle_errors; 412 u32 receive_errors; 413 }; 414 415 struct e1000_host_mng_dhcp_cookie { 416 u32 signature; 417 u8 status; 418 u8 reserved0; 419 u16 vlan_id; 420 u32 reserved1; 421 u16 reserved2; 422 u8 reserved3; 423 u8 checksum; 424 }; 425 426 /* Host Interface "Rev 1" */ 427 struct e1000_host_command_header { 428 u8 command_id; 429 u8 command_length; 430 u8 command_options; 431 u8 checksum; 432 }; 433 434 #define E1000_HI_MAX_DATA_LENGTH 252 435 struct e1000_host_command_info { 436 struct e1000_host_command_header command_header; 437 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 438 }; 439 440 /* Host Interface "Rev 2" */ 441 struct e1000_host_mng_command_header { 442 u8 command_id; 443 u8 checksum; 444 u16 reserved1; 445 u16 reserved2; 446 u16 command_length; 447 }; 448 449 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 450 struct e1000_host_mng_command_info { 451 struct e1000_host_mng_command_header command_header; 452 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 453 }; 454 455 #include "igb_mac.h" 456 #include "igb_phy.h" 457 #include "igb_nvm.h" 458 #include "igb_manage.h" 459 460 struct e1000_mac_operations { 461 /* Function pointers for the MAC. */ 462 s32 (*init_params)(struct e1000_hw *); 463 s32 (*id_led_init)(struct e1000_hw *); 464 s32 (*blink_led)(struct e1000_hw *); 465 s32 (*check_for_link)(struct e1000_hw *); 466 bool (*check_mng_mode)(struct e1000_hw *hw); 467 s32 (*cleanup_led)(struct e1000_hw *); 468 void (*clear_hw_cntrs)(struct e1000_hw *); 469 void (*clear_vfta)(struct e1000_hw *); 470 s32 (*get_bus_info)(struct e1000_hw *); 471 void (*set_lan_id)(struct e1000_hw *); 472 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 473 s32 (*led_on)(struct e1000_hw *); 474 s32 (*led_off)(struct e1000_hw *); 475 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 476 s32 (*reset_hw)(struct e1000_hw *); 477 s32 (*init_hw)(struct e1000_hw *); 478 void (*shutdown_serdes)(struct e1000_hw *); 479 s32 (*setup_link)(struct e1000_hw *); 480 s32 (*setup_physical_interface)(struct e1000_hw *); 481 s32 (*setup_led)(struct e1000_hw *); 482 void (*write_vfta)(struct e1000_hw *, u32, u32); 483 void (*mta_set)(struct e1000_hw *, u32); 484 void (*config_collision_dist)(struct e1000_hw *); 485 void (*rar_set)(struct e1000_hw *, u8*, u32); 486 s32 (*read_mac_addr)(struct e1000_hw *); 487 s32 (*validate_mdi_setting)(struct e1000_hw *); 488 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); 489 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 490 struct e1000_host_mng_command_header *); 491 s32 (*mng_enable_host_if)(struct e1000_hw *); 492 s32 (*wait_autoneg)(struct e1000_hw *); 493 }; 494 495 struct e1000_phy_operations { 496 s32 (*init_params)(struct e1000_hw *); 497 s32 (*acquire)(struct e1000_hw *); 498 s32 (*check_polarity)(struct e1000_hw *); 499 s32 (*check_reset_block)(struct e1000_hw *); 500 s32 (*commit)(struct e1000_hw *); 501 s32 (*force_speed_duplex)(struct e1000_hw *); 502 s32 (*get_cfg_done)(struct e1000_hw *hw); 503 s32 (*get_cable_length)(struct e1000_hw *); 504 s32 (*get_info)(struct e1000_hw *); 505 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 506 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 507 void (*release)(struct e1000_hw *); 508 s32 (*reset)(struct e1000_hw *); 509 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 510 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 511 s32 (*write_reg)(struct e1000_hw *, u32, u16); 512 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 513 void (*power_up)(struct e1000_hw *); 514 void (*power_down)(struct e1000_hw *); 515 }; 516 517 struct e1000_nvm_operations { 518 s32 (*init_params)(struct e1000_hw *); 519 s32 (*acquire)(struct e1000_hw *); 520 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 521 void (*release)(struct e1000_hw *); 522 void (*reload)(struct e1000_hw *); 523 s32 (*update)(struct e1000_hw *); 524 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 525 s32 (*validate)(struct e1000_hw *); 526 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 527 }; 528 529 struct e1000_mac_info { 530 struct e1000_mac_operations ops; 531 u8 addr[6]; 532 u8 perm_addr[6]; 533 534 enum e1000_mac_type type; 535 536 u32 collision_delta; 537 u32 ledctl_default; 538 u32 ledctl_mode1; 539 u32 ledctl_mode2; 540 u32 mc_filter_type; 541 u32 tx_packet_delta; 542 u32 txcw; 543 544 u16 current_ifs_val; 545 u16 ifs_max_val; 546 u16 ifs_min_val; 547 u16 ifs_ratio; 548 u16 ifs_step_size; 549 u16 mta_reg_count; 550 u16 uta_reg_count; 551 552 /* Maximum size of the MTA register table in all supported adapters */ 553 #define MAX_MTA_REG 128 554 u32 mta_shadow[MAX_MTA_REG]; 555 u16 rar_entry_count; 556 557 u8 forced_speed_duplex; 558 559 bool adaptive_ifs; 560 bool arc_subsystem_valid; 561 bool asf_firmware_present; 562 bool autoneg; 563 bool autoneg_failed; 564 bool get_link_status; 565 bool in_ifs_mode; 566 enum e1000_serdes_link_state serdes_link_state; 567 bool serdes_has_link; 568 bool tx_pkt_filtering; 569 }; 570 571 struct e1000_phy_info { 572 struct e1000_phy_operations ops; 573 enum e1000_phy_type type; 574 575 enum e1000_1000t_rx_status local_rx; 576 enum e1000_1000t_rx_status remote_rx; 577 enum e1000_ms_type ms_type; 578 enum e1000_ms_type original_ms_type; 579 enum e1000_rev_polarity cable_polarity; 580 enum e1000_smart_speed smart_speed; 581 582 u32 addr; 583 u32 id; 584 u32 reset_delay_us; /* in usec */ 585 u32 revision; 586 587 enum e1000_media_type media_type; 588 589 u16 autoneg_advertised; 590 u16 autoneg_mask; 591 u16 cable_length; 592 u16 max_cable_length; 593 u16 min_cable_length; 594 595 u8 mdix; 596 597 bool disable_polarity_correction; 598 bool is_mdix; 599 bool polarity_correction; 600 bool reset_disable; 601 bool speed_downgraded; 602 bool autoneg_wait_to_complete; 603 }; 604 605 struct e1000_nvm_info { 606 struct e1000_nvm_operations ops; 607 enum e1000_nvm_type type; 608 enum e1000_nvm_override override; 609 610 u32 flash_bank_size; 611 u32 flash_base_addr; 612 613 u16 word_size; 614 u16 delay_usec; 615 u16 address_bits; 616 u16 opcode_bits; 617 u16 page_size; 618 }; 619 620 struct e1000_bus_info { 621 enum e1000_bus_type type; 622 enum e1000_bus_speed speed; 623 enum e1000_bus_width width; 624 625 u16 func; 626 u16 pci_cmd_word; 627 }; 628 629 struct e1000_fc_info { 630 u32 high_water; /* Flow control high-water mark */ 631 u32 low_water; /* Flow control low-water mark */ 632 u16 pause_time; /* Flow control pause timer */ 633 bool send_xon; /* Flow control send XON */ 634 bool strict_ieee; /* Strict IEEE mode */ 635 enum e1000_fc_mode current_mode; /* FC mode in effect */ 636 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 637 }; 638 639 struct e1000_dev_spec_82575 { 640 bool sgmii_active; 641 bool global_device_reset; 642 }; 643 644 struct e1000_dev_spec_vf { 645 u32 vf_number; 646 u32 v2p_mailbox; 647 }; 648 649 struct e1000_hw { 650 void *back; 651 652 u8 *hw_addr; 653 u8 *flash_address; 654 unsigned long io_base; 655 656 struct e1000_mac_info mac; 657 struct e1000_fc_info fc; 658 struct e1000_phy_info phy; 659 struct e1000_nvm_info nvm; 660 struct e1000_bus_info bus; 661 struct e1000_host_mng_dhcp_cookie mng_cookie; 662 663 union { 664 struct e1000_dev_spec_82575 _82575; 665 struct e1000_dev_spec_vf vf; 666 } dev_spec; 667 668 u16 device_id; 669 u16 subsystem_vendor_id; 670 u16 subsystem_device_id; 671 u16 vendor_id; 672 673 u8 revision_id; 674 }; 675 676 #include "igb_82575.h" 677 678 /* These functions must be implemented by drivers */ 679 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 680 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 681 682 #ifdef __cplusplus 683 } 684 #endif 685 686 #endif /* _IGB_HW_H */ 687
Indexes created Wed Feb 10 05:58:14 UTC 2010
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