1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.111 v2-9-8_2009-6-12 */ 30 31 #ifndef _IGB_DEFINES_H 32 #define _IGB_DEFINES_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 39 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 40 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 41 42 /* Definitions for power management and wakeup registers */ 43 /* Wake Up Control */ 44 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 46 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 47 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 48 #define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */ 49 #define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */ 50 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */ 51 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 52 53 /* Wake Up Filter Control */ 54 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 55 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 56 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 57 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 58 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 59 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 60 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 61 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 62 #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 63 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 64 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 65 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 66 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 67 #define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ 68 #define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ 69 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ 70 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 71 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 72 /* 73 * For 82576 to utilize Extended filter masks in addition to 74 * existing (filter) masks 75 */ 76 #define E1000_WUFC_EXT_FLX_FILTERS 0x00300000 /* Ext. FLX filter mask */ 77 78 /* Wake Up Status */ 79 #define E1000_WUS_LNKC E1000_WUFC_LNKC 80 #define E1000_WUS_MAG E1000_WUFC_MAG 81 #define E1000_WUS_EX E1000_WUFC_EX 82 #define E1000_WUS_MC E1000_WUFC_MC 83 #define E1000_WUS_BC E1000_WUFC_BC 84 #define E1000_WUS_ARP E1000_WUFC_ARP 85 #define E1000_WUS_IPV4 E1000_WUFC_IPV4 86 #define E1000_WUS_IPV6 E1000_WUFC_IPV6 87 #define E1000_WUS_FLX0 E1000_WUFC_FLX0 88 #define E1000_WUS_FLX1 E1000_WUFC_FLX1 89 #define E1000_WUS_FLX2 E1000_WUFC_FLX2 90 #define E1000_WUS_FLX3 E1000_WUFC_FLX3 91 #define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS 92 93 /* Wake Up Packet Length */ 94 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 95 96 /* Four Flexible Filters are supported */ 97 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 98 /* Two Extended Flexible Filters are supported (82576) */ 99 #define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 100 #define E1000_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ 101 #define E1000_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ 102 103 /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 104 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 105 106 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX 107 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 108 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 109 110 /* Extended Device Control */ 111 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 112 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 113 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 114 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 115 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 116 /* Reserved (bits 4,5) in >= 82575 */ 117 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */ 118 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */ 119 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 120 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */ 121 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */ 122 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ 123 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 124 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 125 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 126 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ 127 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 128 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 129 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 130 /* Physical Func Reset Done Indication */ 131 #define E1000_CTRL_EXT_PFRSTD 0x00004000 132 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 133 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 134 /* DMA Dynamic Clock Gating */ 135 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 136 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 137 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 138 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 139 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 140 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 141 #define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 142 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 143 #define E1000_CTRL_EXT_EIAME 0x01000000 144 #define E1000_CTRL_EXT_IRCA 0x00000001 145 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 146 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 147 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 148 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 149 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 150 #define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */ 151 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 152 /* IAME enable bit (27) was removed in >= 82575 */ 153 /* Interrupt acknowledge Auto-mask */ 154 #define E1000_CTRL_EXT_IAME 0x08000000 155 /* Clear Interrupt timers after IMS clear */ 156 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 157 /* packet buffer parity error detection enabled */ 158 #define E1000_CRTL_EXT_PB_PAREN 0x01000000 159 /* descriptor FIFO parity error detection enable */ 160 #define E1000_CTRL_EXT_DF_PAREN 0x02000000 161 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 162 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 163 #define E1000_I2CCMD_REG_ADDR_SHIFT 16 164 #define E1000_I2CCMD_REG_ADDR 0x00FF0000 165 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 166 #define E1000_I2CCMD_PHY_ADDR 0x07000000 167 #define E1000_I2CCMD_OPCODE_READ 0x08000000 168 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 169 #define E1000_I2CCMD_RESET 0x10000000 170 #define E1000_I2CCMD_READY 0x20000000 171 #define E1000_I2CCMD_INTERRUPT_ENA 0x40000000 172 #define E1000_I2CCMD_ERROR 0x80000000 173 #define E1000_MAX_SGMII_PHY_REG_ADDR 255 174 #define E1000_I2CCMD_PHY_TIMEOUT 200 175 #define E1000_IVAR_VALID 0x80 176 #define E1000_GPIE_NSICR 0x00000001 177 #define E1000_GPIE_MSIX_MODE 0x00000010 178 #define E1000_GPIE_EIAME 0x40000000 179 #define E1000_GPIE_PBA 0x80000000 180 181 /* Receive Descriptor bit definitions */ 182 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 183 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 184 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 185 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 186 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 187 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 188 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 189 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 190 #define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 191 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 192 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 193 #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 194 #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 195 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 196 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 197 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 198 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 199 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 200 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 201 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 202 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 203 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 204 #define E1000_RXD_SPC_PRI_SHIFT 13 205 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 206 #define E1000_RXD_SPC_CFI_SHIFT 12 207 208 #define E1000_RXDEXT_STATERR_CE 0x01000000 209 #define E1000_RXDEXT_STATERR_SE 0x02000000 210 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 211 #define E1000_RXDEXT_STATERR_CXE 0x10000000 212 #define E1000_RXDEXT_STATERR_TCPE 0x20000000 213 #define E1000_RXDEXT_STATERR_IPE 0x40000000 214 #define E1000_RXDEXT_STATERR_RXE 0x80000000 215 216 /* mask to determine if packets should be dropped due to frame errors */ 217 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 218 E1000_RXD_ERR_CE | \ 219 E1000_RXD_ERR_SE | \ 220 E1000_RXD_ERR_SEQ | \ 221 E1000_RXD_ERR_CXE | \ 222 E1000_RXD_ERR_RXE) 223 224 /* Same mask, but for extended and packet split descriptors */ 225 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 226 E1000_RXDEXT_STATERR_CE | \ 227 E1000_RXDEXT_STATERR_SE | \ 228 E1000_RXDEXT_STATERR_SEQ | \ 229 E1000_RXDEXT_STATERR_CXE | \ 230 E1000_RXDEXT_STATERR_RXE) 231 232 #define E1000_MRQC_ENABLE_MASK 0x00000007 233 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 234 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004 235 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 236 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 237 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 238 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 239 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 240 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 241 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 242 243 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 244 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 245 246 /* Management Control */ 247 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 248 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 249 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 250 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 251 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 252 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 253 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 254 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 255 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 256 /* Enable Neighbor Discovery Filtering */ 257 #define E1000_MANC_NEIGHBOR_EN 0x00004000 258 #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ 259 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 260 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 261 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 262 #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ 263 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 264 /* Enable MAC address filtering */ 265 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 266 /* Enable MNG packets to host memory */ 267 #define E1000_MANC_EN_MNG2HOST 0x00200000 268 /* Enable IP address filtering */ 269 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 270 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 271 #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 272 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 273 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 274 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 275 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 276 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 277 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 278 279 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 280 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 281 282 /* Receive Control */ 283 #define E1000_RCTL_RST 0x00000001 /* Software reset */ 284 #define E1000_RCTL_EN 0x00000002 /* enable */ 285 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 286 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 287 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 288 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 289 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 290 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 291 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 292 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 293 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ 294 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 295 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 296 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 297 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 298 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 299 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 300 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 301 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 302 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 303 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 304 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 305 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 306 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 307 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 308 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 309 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 310 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 311 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 312 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 313 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 314 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 315 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 316 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 317 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 318 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 319 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 320 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 321 #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ 322 #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ 323 324 /* 325 * Use byte values for the following shift parameters 326 * Usage: 327 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 328 * E1000_PSRCTL_BSIZE0_MASK) | 329 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 330 * E1000_PSRCTL_BSIZE1_MASK) | 331 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 332 * E1000_PSRCTL_BSIZE2_MASK) | 333 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 334 * E1000_PSRCTL_BSIZE3_MASK)) 335 * where value0 = [128..16256], default=256 336 * value1 = [1024..64512], default=4096 337 * value2 = [0..64512], default=4096 338 * value3 = [0..64512], default=0 339 */ 340 341 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 342 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 343 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 344 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 345 346 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 347 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 348 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 349 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 350 351 /* SWFW_SYNC Definitions */ 352 #define E1000_SWFW_EEP_SM 0x1 353 #define E1000_SWFW_PHY0_SM 0x2 354 #define E1000_SWFW_PHY1_SM 0x4 355 #define E1000_SWFW_CSR_SM 0x8 356 357 /* FACTPS Definitions */ 358 #define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */ 359 /* Device Control */ 360 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 361 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 362 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 363 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /* Block new Master requests */ 364 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 365 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 366 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 367 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 368 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 369 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 370 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 371 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 372 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 373 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 374 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 375 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 376 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 377 #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ 378 /* Defined polarity of Dock/Undock indication in SDP[0] */ 379 #define E1000_CTRL_D_UD_POLARITY 0x00004000 380 /* Reset both PHY ports, through PHYRST_N pin */ 381 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 382 /* enable link status from external LINK_0 and LINK_1 pins */ 383 #define E1000_CTRL_EXT_LINK_EN 0x00010000 384 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 385 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 386 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 387 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 388 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 389 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 390 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 391 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 392 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 393 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 394 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 395 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 396 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 397 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 398 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 399 #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */ 400 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 401 402 /* 403 * Bit definitions for the Management Data IO (MDIO) and Management Data 404 * Clock (MDC) pins in the Device Control Register. 405 */ 406 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 407 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 408 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 409 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 410 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 411 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 412 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR 413 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA 414 415 #define E1000_CONNSW_ENRGSRC 0x4 416 #define E1000_PCS_CFG_PCS_EN 8 417 #define E1000_PCS_LCTL_FLV_LINK_UP 1 418 #define E1000_PCS_LCTL_FSV_10 0 419 #define E1000_PCS_LCTL_FSV_100 2 420 #define E1000_PCS_LCTL_FSV_1000 4 421 #define E1000_PCS_LCTL_FDV_FULL 8 422 #define E1000_PCS_LCTL_FSD 0x10 423 #define E1000_PCS_LCTL_FORCE_LINK 0x20 424 #define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40 425 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 426 #define E1000_PCS_LCTL_AN_ENABLE 0x10000 427 #define E1000_PCS_LCTL_AN_RESTART 0x20000 428 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 429 #define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 430 #define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 431 #define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 432 #define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000 433 #define E1000_PCS_LCTL_CRS_ON_NI 0x4000000 434 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 435 436 #define E1000_PCS_LSTS_LINK_OK 1 437 #define E1000_PCS_LSTS_SPEED_10 0 438 #define E1000_PCS_LSTS_SPEED_100 2 439 #define E1000_PCS_LSTS_SPEED_1000 4 440 #define E1000_PCS_LSTS_DUPLEX_FULL 8 441 #define E1000_PCS_LSTS_SYNK_OK 0x10 442 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 443 #define E1000_PCS_LSTS_AN_PAGE_RX 0x20000 444 #define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000 445 #define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 446 #define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000 447 448 /* Device Status */ 449 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 450 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 451 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 452 #define E1000_STATUS_FUNC_SHIFT 2 453 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 454 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 455 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 456 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 457 #define E1000_STATUS_SPEED_MASK 0x000000C0 458 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 459 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 460 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 461 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ 462 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 463 /* Change in Dock/Undock state. Clear on write '0'. */ 464 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 465 #define E1000_STATUS_DOCK_CI 0x00000800 466 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ 467 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 468 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 469 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 470 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 471 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 472 #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ 473 #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ 474 #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ 475 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ 476 /* BMC external code execution disabled */ 477 #define E1000_STATUS_BMC_LITE 0x01000000 478 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ 479 #define E1000_STATUS_FUSE_8 0x04000000 480 #define E1000_STATUS_FUSE_9 0x08000000 481 #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ 482 #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ 483 484 /* Constants used to interpret the masked PCI-X bus speed. */ 485 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ 486 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ 487 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ 488 489 #define SPEED_10 10 490 #define SPEED_100 100 491 #define SPEED_1000 1000 492 #define HALF_DUPLEX 1 493 #define FULL_DUPLEX 2 494 495 #define PHY_FORCE_TIME 20 496 497 #define ADVERTISE_10_HALF 0x0001 498 #define ADVERTISE_10_FULL 0x0002 499 #define ADVERTISE_100_HALF 0x0004 500 #define ADVERTISE_100_FULL 0x0008 501 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 502 #define ADVERTISE_1000_FULL 0x0020 503 504 /* 1000/H is not supported, nor spec-compliant. */ 505 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 506 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 507 ADVERTISE_1000_FULL) 508 #define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 509 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 510 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 511 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 512 #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ 513 ADVERTISE_1000_FULL) 514 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 515 516 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 517 518 /* LED Control */ 519 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 520 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 521 #define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020 522 #define E1000_LEDCTL_LED0_IVRT 0x00000040 523 #define E1000_LEDCTL_LED0_BLINK 0x00000080 524 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 525 #define E1000_LEDCTL_LED1_MODE_SHIFT 8 526 #define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000 527 #define E1000_LEDCTL_LED1_IVRT 0x00004000 528 #define E1000_LEDCTL_LED1_BLINK 0x00008000 529 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 530 #define E1000_LEDCTL_LED2_MODE_SHIFT 16 531 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 532 #define E1000_LEDCTL_LED2_IVRT 0x00400000 533 #define E1000_LEDCTL_LED2_BLINK 0x00800000 534 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 535 #define E1000_LEDCTL_LED3_MODE_SHIFT 24 536 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 537 #define E1000_LEDCTL_LED3_IVRT 0x40000000 538 #define E1000_LEDCTL_LED3_BLINK 0x80000000 539 540 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0 541 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 542 #define E1000_LEDCTL_MODE_LINK_UP 0x2 543 #define E1000_LEDCTL_MODE_ACTIVITY 0x3 544 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 545 #define E1000_LEDCTL_MODE_LINK_10 0x5 546 #define E1000_LEDCTL_MODE_LINK_100 0x6 547 #define E1000_LEDCTL_MODE_LINK_1000 0x7 548 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8 549 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 550 #define E1000_LEDCTL_MODE_COLLISION 0xA 551 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB 552 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC 553 #define E1000_LEDCTL_MODE_PAUSED 0xD 554 #define E1000_LEDCTL_MODE_LED_ON 0xE 555 #define E1000_LEDCTL_MODE_LED_OFF 0xF 556 557 /* Transmit Descriptor bit definitions */ 558 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 559 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 560 #define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */ 561 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 562 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 563 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 564 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 565 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 566 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 567 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 568 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0=legacy) */ 569 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 570 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 571 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 572 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 573 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 574 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 575 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 576 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 577 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 578 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 579 /* Extended desc bits for Linksec and timesync */ 580 581 /* Transmit Control */ 582 #define E1000_TCTL_RST 0x00000001 /* software reset */ 583 #define E1000_TCTL_EN 0x00000002 /* enable tx */ 584 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 585 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 586 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 587 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 588 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 589 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 590 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 591 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 592 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 593 594 /* Transmit Arbitration Count */ 595 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ 596 597 /* SerDes Control */ 598 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 599 600 /* Receive Checksum Control */ 601 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 602 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 603 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 604 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 605 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 606 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 607 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 608 609 /* Header split receive */ 610 #define E1000_RFCTL_ISCSI_DIS 0x00000001 611 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E 612 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1 613 #define E1000_RFCTL_NFSW_DIS 0x00000040 614 #define E1000_RFCTL_NFSR_DIS 0x00000080 615 #define E1000_RFCTL_NFS_VER_MASK 0x00000300 616 #define E1000_RFCTL_NFS_VER_SHIFT 8 617 #define E1000_RFCTL_IPV6_DIS 0x00000400 618 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 619 #define E1000_RFCTL_ACK_DIS 0x00001000 620 #define E1000_RFCTL_ACKD_DIS 0x00002000 621 #define E1000_RFCTL_IPFRSP_DIS 0x00004000 622 #define E1000_RFCTL_EXTEN 0x00008000 623 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 624 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 625 #define E1000_RFCTL_LEF 0x00040000 626 627 /* Collision related configuration parameters */ 628 #define E1000_COLLISION_THRESHOLD 15 629 #define E1000_CT_SHIFT 4 630 #define E1000_COLLISION_DISTANCE 63 631 #define E1000_COLD_SHIFT 12 632 633 /* Default values for the transmit IPG register */ 634 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 635 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 636 637 #define E1000_TIPG_IPGT_MASK 0x000003FF 638 #define E1000_TIPG_IPGR1_MASK 0x000FFC00 639 #define E1000_TIPG_IPGR2_MASK 0x3FF00000 640 641 #define DEFAULT_82543_TIPG_IPGR1 8 642 #define E1000_TIPG_IPGR1_SHIFT 10 643 644 #define DEFAULT_82543_TIPG_IPGR2 6 645 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 646 #define E1000_TIPG_IPGR2_SHIFT 20 647 648 /* Ethertype field values */ 649 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 650 651 #define ETHERNET_FCS_SIZE 4 652 #define MAX_JUMBO_FRAME_SIZE 0x3F00 653 654 /* Extended Configuration Control and Size */ 655 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 656 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 657 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 658 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 659 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 660 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 661 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 662 663 #define E1000_PHY_CTRL_SPD_EN 0x00000001 664 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 665 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 666 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 667 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 668 669 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 670 671 /* PBA constants */ 672 #define E1000_PBA_6K 0x0006 /* 6KB */ 673 #define E1000_PBA_8K 0x0008 /* 8KB */ 674 #define E1000_PBA_10K 0x000A /* 10KB */ 675 #define E1000_PBA_12K 0x000C /* 12KB */ 676 #define E1000_PBA_14K 0x000E /* 14KB */ 677 #define E1000_PBA_16K 0x0010 /* 16KB */ 678 #define E1000_PBA_18K 0x0012 679 #define E1000_PBA_20K 0x0014 680 #define E1000_PBA_22K 0x0016 681 #define E1000_PBA_24K 0x0018 682 #define E1000_PBA_26K 0x001A 683 #define E1000_PBA_30K 0x001E 684 #define E1000_PBA_32K 0x0020 685 #define E1000_PBA_34K 0x0022 686 #define E1000_PBA_35K 0x0023 687 #define E1000_PBA_38K 0x0026 688 #define E1000_PBA_40K 0x0028 689 #define E1000_PBA_48K 0x0030 /* 48KB */ 690 #define E1000_PBA_64K 0x0040 /* 64KB */ 691 692 #define E1000_PBS_16K E1000_PBA_16K 693 #define E1000_PBS_24K E1000_PBA_24K 694 695 #define IFS_MAX 80 696 #define IFS_MIN 40 697 #define IFS_RATIO 4 698 #define IFS_STEP 10 699 #define MIN_NUM_XMITS 1000 700 701 /* SW Semaphore Register */ 702 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 703 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 704 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 705 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 706 707 /* Secondary driver semaphore bit */ 708 #define E1000_SWSM2_LOCK 0x00000002 709 710 /* Interrupt Cause Read */ 711 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 712 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 713 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 714 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 715 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 716 #define E1000_ICR_RXO 0x00000040 /* rx overrun */ 717 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 718 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 719 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 720 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ 721 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 722 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 723 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 724 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 725 #define E1000_ICR_TXD_LOW 0x00008000 726 #define E1000_ICR_SRPD 0x00010000 727 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 728 #define E1000_ICR_MNG 0x00040000 /* Manageability event */ 729 #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ 730 /* If this bit asserted, the driver should claim the interrupt */ 731 #define E1000_ICR_INT_ASSERTED 0x80000000 732 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */ 733 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */ 734 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */ 735 #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 736 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */ 737 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */ 738 #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 739 /* FW changed the status of DISSW bit in the FWSM */ 740 #define E1000_ICR_DSW 0x00000020 741 /* LAN connected device generates an interrupt */ 742 #define E1000_ICR_PHYINT 0x00001000 743 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 744 #define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ 745 746 /* Extended Interrupt Cause Read */ 747 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 748 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 749 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 750 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 751 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 752 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 753 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 754 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 755 #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 756 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 757 /* TCP Timer */ 758 #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */ 759 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ 760 #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ 761 #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */ 762 763 /* 764 * This defines the bits that are set in the Interrupt Mask 765 * Set/Read Register. Each bit is documented below: 766 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 767 * o RXSEQ = Receive Sequence Error 768 */ 769 #define POLL_IMS_ENABLE_MASK ( \ 770 E1000_IMS_RXDMT0 | \ 771 E1000_IMS_RXSEQ) 772 773 /* 774 * This defines the bits that are set in the Interrupt Mask 775 * Set/Read Register. Each bit is documented below: 776 * o RXT0 = Receiver Timer Interrupt (ring 0) 777 * o TXDW = Transmit Descriptor Written Back 778 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 779 * o RXSEQ = Receive Sequence Error 780 * o LSC = Link Status Change 781 */ 782 #define IMS_ENABLE_MASK ( \ 783 E1000_IMS_RXT0 | \ 784 E1000_IMS_TXDW | \ 785 E1000_IMS_RXDMT0 | \ 786 E1000_IMS_RXSEQ | \ 787 E1000_IMS_LSC) 788 789 /* Interrupt Mask Set */ 790 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 791 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 792 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 793 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ 794 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 795 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 796 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 797 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 798 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 799 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ 800 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 801 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 802 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 803 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 804 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 805 #define E1000_IMS_SRPD E1000_ICR_SRPD 806 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 807 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 808 #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 809 /* queue 0 Rx descriptor FIFO parity error */ 810 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 811 /* queue 0 Tx descriptor FIFO parity error */ 812 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 813 /* host arb read buffer parity error */ 814 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR 815 /* packet buffer parity error */ 816 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR 817 /* queue 1 Rx descriptor FIFO parity error */ 818 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 819 /* queue 1 Tx descriptor FIFO parity error */ 820 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 821 #define E1000_IMS_DSW E1000_ICR_DSW 822 #define E1000_IMS_PHYINT E1000_ICR_PHYINT 823 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 824 #define E1000_IMS_EPRST E1000_ICR_EPRST 825 826 /* Extended Interrupt Mask Set */ 827 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 828 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 829 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 830 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 831 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 832 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 833 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 834 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 835 #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 836 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 837 838 /* Interrupt Cause Set */ 839 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 840 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 841 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 842 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 843 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 844 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 845 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 846 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 847 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ 848 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 849 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 850 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 851 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 852 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 853 #define E1000_ICS_SRPD E1000_ICR_SRPD 854 #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 855 #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 856 #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 857 /* queue 0 Rx descriptor FIFO parity error */ 858 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 859 /* queue 0 Tx descriptor FIFO parity error */ 860 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 861 /* host arb read buffer parity error */ 862 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR 863 /* packet buffer parity error */ 864 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR 865 /* queue 1 Rx descriptor FIFO parity error */ 866 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 867 /* queue 1 Tx descriptor FIFO parity error */ 868 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 869 #define E1000_ICS_DSW E1000_ICR_DSW 870 #define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 871 #define E1000_ICS_PHYINT E1000_ICR_PHYINT 872 #define E1000_ICS_EPRST E1000_ICR_EPRST 873 874 /* Extended Interrupt Cause Set */ 875 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 876 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 877 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 878 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 879 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 880 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 881 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 882 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 883 #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 884 #define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 885 886 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF 887 888 /* Transmit Descriptor Control */ 889 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 890 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 891 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 892 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 893 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 894 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 895 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 896 /* Enable the counting of descriptors still to be processed. */ 897 #define E1000_TXDCTL_COUNT_DESC 0x00400000 898 899 /* Flow Control Constants */ 900 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 901 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 902 #define FLOW_CONTROL_TYPE 0x8808 903 904 /* 802.1q VLAN Packet Size */ 905 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 906 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 907 908 /* Receive Address */ 909 /* 910 * Number of high/low register pairs in the RAR. The RAR (Receive Address 911 * Registers) holds the directed and multicast addresses that we monitor. 912 * Technically, we have 16 spots. However, we reserve one of these spots 913 * (RAR[15]) for our directed address used by controllers with 914 * manageability enabled, allowing us room for 15 multicast addresses. 915 */ 916 #define E1000_RAR_ENTRIES 15 917 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 918 #define E1000_RAL_MAC_ADDR_LEN 4 919 #define E1000_RAH_MAC_ADDR_LEN 2 920 #define E1000_RAH_POOL_MASK 0x03FC0000 921 #define E1000_RAH_POOL_1 0x00040000 922 923 /* Error Codes */ 924 #define E1000_SUCCESS 0 925 #define E1000_ERR_NVM 1 926 #define E1000_ERR_PHY 2 927 #define E1000_ERR_CONFIG 3 928 #define E1000_ERR_PARAM 4 929 #define E1000_ERR_MAC_INIT 5 930 #define E1000_ERR_PHY_TYPE 6 931 #define E1000_ERR_RESET 9 932 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 933 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 934 #define E1000_BLK_PHY_RESET 12 935 #define E1000_ERR_SWFW_SYNC 13 936 #define E1000_NOT_IMPLEMENTED 14 937 #define E1000_ERR_MBX 15 938 939 /* Loop limit on how long we wait for auto-negotiation to complete */ 940 #define FIBER_LINK_UP_LIMIT 50 941 #define COPPER_LINK_UP_LIMIT 10 942 #define PHY_AUTO_NEG_LIMIT 45 943 #define PHY_FORCE_LIMIT 20 944 /* Number of 100 microseconds we wait for PCI Express master disable */ 945 #define MASTER_DISABLE_TIMEOUT 800 946 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 947 #define PHY_CFG_TIMEOUT 100 948 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 949 #define MDIO_OWNERSHIP_TIMEOUT 10 950 /* Number of milliseconds for NVM auto read done after MAC reset. */ 951 #define AUTO_READ_DONE_TIMEOUT 10 952 953 /* Flow Control */ 954 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 955 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 956 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 957 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 958 959 /* Transmit Configuration Word */ 960 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 961 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 962 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 963 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 964 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 965 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 966 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 967 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 968 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 969 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 970 971 /* Receive Configuration Word */ 972 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 973 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 974 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 975 #define E1000_RXCW_CC 0x10000000 /* Receive config change */ 976 #define E1000_RXCW_C 0x20000000 /* Receive config */ 977 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 978 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 979 980 /* PCI Express Control */ 981 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 982 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 983 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 984 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 985 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 986 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 987 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 988 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 989 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 990 #define E1000_GCR_CAP_VER2 0x00040000 991 992 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 993 E1000_GCR_RXDSCW_NO_SNOOP | \ 994 E1000_GCR_RXDSCR_NO_SNOOP | \ 995 E1000_GCR_TXD_NO_SNOOP | \ 996 E1000_GCR_TXDSCW_NO_SNOOP | \ 997 E1000_GCR_TXDSCR_NO_SNOOP) 998 999 /* PHY Control Register */ 1000 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1001 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 1002 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 1003 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 1004 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 1005 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 1006 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 1007 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1008 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 1009 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 1010 #define MII_CR_SPEED_1000 0x0040 1011 #define MII_CR_SPEED_100 0x2000 1012 #define MII_CR_SPEED_10 0x0000 1013 1014 /* PHY Status Register */ 1015 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 1016 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 1017 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 1018 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 1019 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 1020 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 1021 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 1022 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 1023 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 1024 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 1025 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 1026 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 1027 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 1028 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 1029 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 1030 1031 /* Autoneg Advertisement Register */ 1032 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 1033 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 1034 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 1035 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 1036 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 1037 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 1038 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 1039 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 1040 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 1041 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1042 1043 /* Link Partner Ability Register (Base Page) */ 1044 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 1045 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ 1046 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ 1047 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ 1048 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ 1049 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 1050 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 1051 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 1052 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ 1053 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ 1054 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1055 1056 /* Autoneg Expansion Register */ 1057 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 1058 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ 1059 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ 1060 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ 1061 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ 1062 1063 /* 1000BASE-T Control Register */ 1064 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 1065 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 1066 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 1067 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 1068 /* 0=DTE device */ 1069 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 1070 /* 0=Configure PHY as Slave */ 1071 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 1072 /* 0=Automatic Master/Slave config */ 1073 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 1074 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 1075 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 1076 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 1077 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 1078 1079 /* 1000BASE-T Status Register */ 1080 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ 1081 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ 1082 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 1083 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 1084 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 1085 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 1086 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx is Master, 0=Slave */ 1087 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 1088 1089 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 1090 1091 /* PHY 1000 MII Register/Bit Definitions */ 1092 /* PHY Registers defined by IEEE */ 1093 #define PHY_CONTROL 0x00 /* Control Register */ 1094 #define PHY_STATUS 0x01 /* Status Register */ 1095 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 1096 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 1097 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 1098 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 1099 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 1100 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ 1101 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 1102 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 1103 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 1104 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 1105 1106 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 1107 1108 /* NVM Control */ 1109 #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 1110 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 1111 #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 1112 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 1113 #define E1000_EECD_FWE_MASK 0x00000030 1114 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1115 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 1116 #define E1000_EECD_FWE_SHIFT 4 1117 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 1118 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 1119 #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 1120 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 1121 /* NVM Addressing bits based on type 0=small, 1=large */ 1122 #define E1000_EECD_ADDR_BITS 0x00000400 1123 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ 1124 #ifndef E1000_NVM_GRANT_ATTEMPTS 1125 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 1126 #endif 1127 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 1128 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 1129 #define E1000_EECD_SIZE_EX_SHIFT 11 1130 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ 1131 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 1132 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 1133 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1134 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 1135 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 1136 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1137 #define E1000_EECD_SECVAL_SHIFT 22 1138 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 1139 1140 #define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */ 1141 #define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */ 1142 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ 1143 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1144 #define E1000_NVM_RW_REG_START 1 /* Start operation */ 1145 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1146 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 1147 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 1148 #define E1000_FLASH_UPDATES 2000 1149 1150 /* NVM Word Offsets */ 1151 #define NVM_COMPAT 0x0003 1152 #define NVM_ID_LED_SETTINGS 0x0004 1153 #define NVM_VERSION 0x0005 1154 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ 1155 #define NVM_PHY_CLASS_WORD 0x0007 1156 #define NVM_INIT_CONTROL1_REG 0x000A 1157 #define NVM_INIT_CONTROL2_REG 0x000F 1158 #define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 1159 #define NVM_INIT_CONTROL3_PORT_B 0x0014 1160 #define NVM_INIT_3GIO_3 0x001A 1161 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 1162 #define NVM_INIT_CONTROL3_PORT_A 0x0024 1163 #define NVM_CFG 0x0012 1164 #define NVM_FLASH_VERSION 0x0032 1165 #define NVM_ALT_MAC_ADDR_PTR 0x0037 1166 #define NVM_CHECKSUM_REG 0x003F 1167 1168 #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ 1169 #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ 1170 1171 /* Mask bits for fields in Word 0x0f of the NVM */ 1172 #define NVM_WORD0F_PAUSE_MASK 0x3000 1173 #define NVM_WORD0F_PAUSE 0x1000 1174 #define NVM_WORD0F_ASM_DIR 0x2000 1175 #define NVM_WORD0F_ANE 0x0800 1176 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 1177 #define NVM_WORD0F_LPLU 0x0001 1178 1179 /* Mask bits for fields in Word 0x1a of the NVM */ 1180 #define NVM_WORD1A_ASPM_MASK 0x000C 1181 1182 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 1183 #define NVM_SUM 0xBABA 1184 1185 #define NVM_MAC_ADDR_OFFSET 0 1186 #define NVM_PBA_OFFSET_0 8 1187 #define NVM_PBA_OFFSET_1 9 1188 #define NVM_RESERVED_WORD 0xFFFF 1189 #define NVM_PHY_CLASS_A 0x8000 1190 #define NVM_SERDES_AMPLITUDE_MASK 0x000F 1191 #define NVM_SIZE_MASK 0x1C00 1192 #define NVM_SIZE_SHIFT 10 1193 #define NVM_WORD_SIZE_BASE_SHIFT 6 1194 #define NVM_SWDPIO_EXT_SHIFT 4 1195 1196 /* NVM Commands - Microwire */ 1197 #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ 1198 #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ 1199 #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ 1200 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ 1201 #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */ 1202 1203 /* NVM Commands - SPI */ 1204 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1205 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 1206 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 1207 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 1208 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 1209 #define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */ 1210 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 1211 #define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */ 1212 1213 /* SPI NVM Status Register */ 1214 #define NVM_STATUS_RDY_SPI 0x01 1215 #define NVM_STATUS_WEN_SPI 0x02 1216 #define NVM_STATUS_BP0_SPI 0x04 1217 #define NVM_STATUS_BP1_SPI 0x08 1218 #define NVM_STATUS_WPEN_SPI 0x80 1219 1220 /* Word definitions for ID LED Settings */ 1221 #define ID_LED_RESERVED_0000 0x0000 1222 #define ID_LED_RESERVED_FFFF 0xFFFF 1223 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1224 (ID_LED_OFF1_OFF2 << 8) | \ 1225 (ID_LED_DEF1_DEF2 << 4) | \ 1226 (ID_LED_DEF1_DEF2)) 1227 #define ID_LED_DEF1_DEF2 0x1 1228 #define ID_LED_DEF1_ON2 0x2 1229 #define ID_LED_DEF1_OFF2 0x3 1230 #define ID_LED_ON1_DEF2 0x4 1231 #define ID_LED_ON1_ON2 0x5 1232 #define ID_LED_ON1_OFF2 0x6 1233 #define ID_LED_OFF1_DEF2 0x7 1234 #define ID_LED_OFF1_ON2 0x8 1235 #define ID_LED_OFF1_OFF2 0x9 1236 1237 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 1238 #define IGP_ACTIVITY_LED_ENABLE 0x0300 1239 #define IGP_LED3_MODE 0x07000000 1240 1241 /* PCI/PCI-X/PCI-EX Config space */ 1242 #define PCI_HEADER_TYPE_REGISTER 0x0E 1243 #define PCIE_LINK_STATUS 0x12 1244 #define PCIE_DEVICE_CONTROL2 0x28 1245 1246 #define PCI_HEADER_TYPE_MULTIFUNC 0x80 1247 #define PCIE_LINK_WIDTH_MASK 0x3F0 1248 #define PCIE_LINK_WIDTH_SHIFT 4 1249 #define PCIE_DEVICE_CONTROL2_16ms 0x0005 1250 1251 #ifndef ETH_ADDR_LEN 1252 #define ETH_ADDR_LEN 6 1253 #endif 1254 1255 #define PHY_REVISION_MASK 0xFFFFFFF0 1256 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 1257 #define MAX_PHY_MULTI_PAGE_REG 0xF 1258 1259 /* Bit definitions for valid PHY IDs. */ 1260 /* 1261 * I = Integrated 1262 * E = External 1263 */ 1264 #define M88E1000_E_PHY_ID 0x01410C50 1265 #define M88E1000_I_PHY_ID 0x01410C30 1266 #define M88E1011_I_PHY_ID 0x01410C20 1267 #define IGP01E1000_I_PHY_ID 0x02A80380 1268 #define M88E1011_I_REV_4 0x04 1269 #define M88E1111_I_PHY_ID 0x01410CC0 1270 #define GG82563_E_PHY_ID 0x01410CA0 1271 #define IGP03E1000_E_PHY_ID 0x02A80390 1272 #define IFE_E_PHY_ID 0x02A80330 1273 #define IFE_PLUS_E_PHY_ID 0x02A80320 1274 #define IFE_C_E_PHY_ID 0x02A80310 1275 #define IGP04E1000_E_PHY_ID 0x02A80391 1276 #define M88_VENDOR 0x0141 1277 1278 /* M88E1000 Specific Registers */ 1279 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 1280 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 1281 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 1282 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 1283 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 1284 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 1285 1286 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 1287 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg29 for page number setting */ 1288 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 1289 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 1290 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 1291 1292 /* M88E1000 PHY Specific Control Register */ 1293 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 1294 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 1295 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 1296 /* 1=CLK125 low, 0=CLK125 toggling */ 1297 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 1298 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 1299 /* Manual MDI configuration */ 1300 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 1301 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 1302 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 1303 /* Auto crossover enabled all speeds */ 1304 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 1305 /* 1306 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold 1307 * 0=Normal 10BASE-T Rx Threshold 1308 */ 1309 #define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 1310 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ 1311 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 1312 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 1313 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 1314 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 1315 1316 /* M88E1000 PHY Specific Status Register */ 1317 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 1318 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 1319 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 1320 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 1321 /* 1322 * 0 = <50M 1323 * 1 = 50-80M 1324 * 2 = 80-110M 1325 * 3 = 110-140M 1326 * 4 = >140M 1327 */ 1328 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 1329 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 1330 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 1331 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 1332 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 1333 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 1334 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 1335 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 1336 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 1337 1338 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 1339 1340 /* M88E1000 Extended PHY Specific Control Register */ 1341 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 1342 /* 1343 * 1 = Lost lock detect enabled. 1344 * Will assert lost lock and bring 1345 * link down if idle not seen 1346 * within 1ms in 1000BASE-T 1347 */ 1348 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 1349 /* 1350 * Number of times we will attempt to autonegotiate before downshifting if we 1351 * are the master 1352 */ 1353 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1354 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1355 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 1356 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 1357 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 1358 /* 1359 * Number of times we will attempt to autonegotiate before downshifting if we 1360 * are the slave 1361 */ 1362 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1363 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 1364 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1365 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 1366 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 1367 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 1368 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 1369 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 1370 1371 /* M88EC018 Rev 2 specific DownShift settings */ 1372 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 1373 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 1374 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 1375 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 1376 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 1377 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 1378 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 1379 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 1380 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 1381 1382 /* 1383 * Bits... 1384 * 15-5: page 1385 * 4-0: register offset 1386 */ 1387 #define GG82563_PAGE_SHIFT 5 1388 #define GG82563_REG(page, reg) \ 1389 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 1390 #define GG82563_MIN_ALT_REG 30 1391 1392 /* GG82563 Specific Registers */ 1393 #define GG82563_PHY_SPEC_CTRL \ 1394 GG82563_REG(0, 16) /* PHY Specific Control */ 1395 #define GG82563_PHY_SPEC_STATUS \ 1396 GG82563_REG(0, 17) /* PHY Specific Status */ 1397 #define GG82563_PHY_INT_ENABLE \ 1398 GG82563_REG(0, 18) /* Interrupt Enable */ 1399 #define GG82563_PHY_SPEC_STATUS_2 \ 1400 GG82563_REG(0, 19) /* PHY Specific Status 2 */ 1401 #define GG82563_PHY_RX_ERR_CNTR \ 1402 GG82563_REG(0, 21) /* Receive Error Counter */ 1403 #define GG82563_PHY_PAGE_SELECT \ 1404 GG82563_REG(0, 22) /* Page Select */ 1405 #define GG82563_PHY_SPEC_CTRL_2 \ 1406 GG82563_REG(0, 26) /* PHY Specific Control 2 */ 1407 #define GG82563_PHY_PAGE_SELECT_ALT \ 1408 GG82563_REG(0, 29) /* Alternate Page Select */ 1409 #define GG82563_PHY_TEST_CLK_CTRL \ 1410 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ 1411 1412 #define GG82563_PHY_MAC_SPEC_CTRL \ 1413 GG82563_REG(2, 21) /* MAC Specific Control Register */ 1414 #define GG82563_PHY_MAC_SPEC_CTRL_2 \ 1415 GG82563_REG(2, 26) /* MAC Specific Control 2 */ 1416 1417 #define GG82563_PHY_DSP_DISTANCE \ 1418 GG82563_REG(5, 26) /* DSP Distance */ 1419 1420 /* Page 193 - Port Control Registers */ 1421 #define GG82563_PHY_KMRN_MODE_CTRL \ 1422 GG82563_REG(193, 16) /* Kumeran Mode Control */ 1423 #define GG82563_PHY_PORT_RESET \ 1424 GG82563_REG(193, 17) /* Port Reset */ 1425 #define GG82563_PHY_REVISION_ID \ 1426 GG82563_REG(193, 18) /* Revision ID */ 1427 #define GG82563_PHY_DEVICE_ID \ 1428 GG82563_REG(193, 19) /* Device ID */ 1429 #define GG82563_PHY_PWR_MGMT_CTRL \ 1430 GG82563_REG(193, 20) /* Power Management Control */ 1431 #define GG82563_PHY_RATE_ADAPT_CTRL \ 1432 GG82563_REG(193, 25) /* Rate Adaptation Control */ 1433 1434 /* Page 194 - KMRN Registers */ 1435 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ 1436 GG82563_REG(194, 16) /* FIFO's Control/Status */ 1437 #define GG82563_PHY_KMRN_CTRL \ 1438 GG82563_REG(194, 17) /* Control */ 1439 #define GG82563_PHY_INBAND_CTRL \ 1440 GG82563_REG(194, 18) /* Inband Control */ 1441 #define GG82563_PHY_KMRN_DIAGNOSTIC \ 1442 GG82563_REG(194, 19) /* Diagnostic */ 1443 #define GG82563_PHY_ACK_TIMEOUTS \ 1444 GG82563_REG(194, 20) /* Acknowledge Timeouts */ 1445 #define GG82563_PHY_ADV_ABILITY \ 1446 GG82563_REG(194, 21) /* Advertised Ability */ 1447 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ 1448 GG82563_REG(194, 23) /* Link Partner Advertised Ability */ 1449 #define GG82563_PHY_ADV_NEXT_PAGE \ 1450 GG82563_REG(194, 24) /* Advertised Next Page */ 1451 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ 1452 GG82563_REG(194, 25) /* Link Partner Advertised Next page */ 1453 #define GG82563_PHY_KMRN_MISC \ 1454 GG82563_REG(194, 26) /* Misc. */ 1455 1456 /* MDI Control */ 1457 #define E1000_MDIC_DATA_MASK 0x0000FFFF 1458 #define E1000_MDIC_REG_MASK 0x001F0000 1459 #define E1000_MDIC_REG_SHIFT 16 1460 #define E1000_MDIC_PHY_MASK 0x03E00000 1461 #define E1000_MDIC_PHY_SHIFT 21 1462 #define E1000_MDIC_OP_WRITE 0x04000000 1463 #define E1000_MDIC_OP_READ 0x08000000 1464 #define E1000_MDIC_READY 0x10000000 1465 #define E1000_MDIC_INT_EN 0x20000000 1466 #define E1000_MDIC_ERROR 0x40000000 1467 1468 /* SerDes Control */ 1469 #define E1000_GEN_CTL_READY 0x80000000 1470 #define E1000_GEN_CTL_ADDRESS_SHIFT 8 1471 #define E1000_GEN_POLL_TIMEOUT 640 1472 1473 /* LinkSec register fields */ 1474 #define E1000_LSECTXCAP_SUM_MASK 0x00FF0000 1475 #define E1000_LSECTXCAP_SUM_SHIFT 16 1476 #define E1000_LSECRXCAP_SUM_MASK 0x00FF0000 1477 #define E1000_LSECRXCAP_SUM_SHIFT 16 1478 1479 #define E1000_LSECTXCTRL_EN_MASK 0x00000003 1480 #define E1000_LSECTXCTRL_DISABLE 0x0 1481 #define E1000_LSECTXCTRL_AUTH 0x1 1482 #define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2 1483 #define E1000_LSECTXCTRL_AISCI 0x00000020 1484 #define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 1485 #define E1000_LSECTXCTRL_RSV_MASK 0x000000D8 1486 1487 #define E1000_LSECRXCTRL_EN_MASK 0x0000000C 1488 #define E1000_LSECRXCTRL_EN_SHIFT 2 1489 #define E1000_LSECRXCTRL_DISABLE 0x0 1490 #define E1000_LSECRXCTRL_CHECK 0x1 1491 #define E1000_LSECRXCTRL_STRICT 0x2 1492 #define E1000_LSECRXCTRL_DROP 0x3 1493 #define E1000_LSECRXCTRL_PLSH 0x00000040 1494 #define E1000_LSECRXCTRL_RP 0x00000080 1495 #define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33 1496 1497 #ifdef __cplusplus 1498 } 1499 #endif 1500 1501 #endif /* _IGB_DEFINES_H */ 1502
Indexes created Sun Nov 22 02:16:54 UTC 2009
Terms of Use |
Privacy |
Trademarks |
Copyright Policy |
Site Guidelines |
Help
Your use of this web site or any of its content or software indicates your agreement to be bound by these Terms of Use.
Copyright © 1995-2008 Sun Microsystems, Inc.