1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.143 scm_100809_154340 */ 30 31 /* 32 * 82575EB Gigabit Network Connection 33 * 82575EB Gigabit Backplane Connection 34 * 82575GB Gigabit Network Connection 35 * 82576 Gigabit Network Connection 36 * 82576 Quad Port Gigabit Mezzanine Adapter 37 */ 38 39 #include "igb_api.h" 40 41 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 42 static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 43 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 44 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 45 static void e1000_release_phy_82575(struct e1000_hw *hw); 46 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 47 static void e1000_release_nvm_82575(struct e1000_hw *hw); 48 static s32 e1000_check_for_link_82575(struct e1000_hw *hw); 49 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 50 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 51 u16 *duplex); 52 static s32 e1000_init_hw_82575(struct e1000_hw *hw); 53 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 54 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 55 u16 *data); 56 static s32 e1000_reset_hw_82575(struct e1000_hw *hw); 57 static s32 e1000_reset_hw_82580(struct e1000_hw *hw); 58 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, 59 u16 *data); 60 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, 61 u16 data); 62 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 63 bool active); 64 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 65 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 66 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 67 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 68 u32 offset, u16 data); 69 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 70 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 71 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 72 u16 *speed, u16 *duplex); 73 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 74 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 75 static bool e1000_sgmii_active_82575(struct e1000_hw *hw); 76 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 77 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 78 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 79 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 80 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 81 82 static const u16 e1000_82580_rxpbs_table[] = 83 {36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140}; 84 #define E1000_82580_RXPBS_TABLE_SIZE \ 85 (sizeof (e1000_82580_rxpbs_table)/sizeof (u16)) 86 87 /* 88 * e1000_init_phy_params_82575 - Init PHY func ptrs. 89 * @hw: pointer to the HW structure 90 */ 91 static s32 92 e1000_init_phy_params_82575(struct e1000_hw *hw) 93 { 94 struct e1000_phy_info *phy = &hw->phy; 95 s32 ret_val = E1000_SUCCESS; 96 97 DEBUGFUNC("e1000_init_phy_params_82575"); 98 99 if (hw->phy.media_type != e1000_media_type_copper) { 100 phy->type = e1000_phy_none; 101 goto out; 102 } 103 104 phy->ops.power_up = e1000_power_up_phy_copper; 105 phy->ops.power_down = e1000_power_down_phy_copper_82575; 106 107 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 108 phy->reset_delay_us = 100; 109 110 phy->ops.acquire = e1000_acquire_phy_82575; 111 phy->ops.check_reset_block = e1000_check_reset_block_generic; 112 phy->ops.commit = e1000_phy_sw_reset_generic; 113 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 114 phy->ops.release = e1000_release_phy_82575; 115 116 if (e1000_sgmii_active_82575(hw)) { 117 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 118 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 119 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 120 } else if (hw->mac.type == e1000_82580) { 121 phy->ops.reset = e1000_phy_hw_reset_generic; 122 phy->ops.read_reg = e1000_read_phy_reg_82580; 123 phy->ops.write_reg = e1000_write_phy_reg_82580; 124 } else { 125 phy->ops.reset = e1000_phy_hw_reset_generic; 126 phy->ops.read_reg = e1000_read_phy_reg_igp; 127 phy->ops.write_reg = e1000_write_phy_reg_igp; 128 } 129 130 /* Set phy->phy_addr and phy->id. */ 131 ret_val = e1000_get_phy_id_82575(hw); 132 133 /* Verify phy id and set remaining function pointers */ 134 switch (phy->id) { 135 case M88E1111_I_PHY_ID: 136 phy->type = e1000_phy_m88; 137 phy->ops.check_polarity = e1000_check_polarity_m88; 138 phy->ops.get_info = e1000_get_phy_info_m88; 139 phy->ops.get_cable_length = e1000_get_cable_length_m88; 140 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 141 break; 142 case IGP03E1000_E_PHY_ID: 143 case IGP04E1000_E_PHY_ID: 144 phy->type = e1000_phy_igp_3; 145 phy->ops.check_polarity = e1000_check_polarity_igp; 146 phy->ops.get_info = e1000_get_phy_info_igp; 147 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 148 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 149 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 150 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 151 break; 152 case I82580_I_PHY_ID: 153 phy->type = e1000_phy_82580; 154 phy->ops.check_polarity = e1000_check_polarity_82577; 155 phy->ops.force_speed_duplex = 156 e1000_phy_force_speed_duplex_82577; 157 phy->ops.get_cable_length = e1000_get_cable_length_82577; 158 phy->ops.get_info = e1000_get_phy_info_82577; 159 break; 160 default: 161 ret_val = -E1000_ERR_PHY; 162 goto out; 163 } 164 165 out: 166 return (ret_val); 167 } 168 169 /* 170 * e1000_init_nvm_params_82575 - Init NVM func ptrs. 171 * @hw: pointer to the HW structure 172 */ 173 static s32 174 e1000_init_nvm_params_82575(struct e1000_hw *hw) 175 { 176 struct e1000_nvm_info *nvm = &hw->nvm; 177 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 178 u16 size; 179 180 DEBUGFUNC("e1000_init_nvm_params_82575"); 181 182 nvm->opcode_bits = 8; 183 nvm->delay_usec = 1; 184 switch (nvm->override) { 185 case e1000_nvm_override_spi_large: 186 nvm->page_size = 32; 187 nvm->address_bits = 16; 188 break; 189 case e1000_nvm_override_spi_small: 190 nvm->page_size = 8; 191 nvm->address_bits = 8; 192 break; 193 default: 194 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 195 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 196 break; 197 } 198 199 nvm->type = e1000_nvm_eeprom_spi; 200 201 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 202 E1000_EECD_SIZE_EX_SHIFT); 203 204 /* 205 * Added to a constant, "size" becomes the left-shift value 206 * for setting word_size. 207 */ 208 size += NVM_WORD_SIZE_BASE_SHIFT; 209 210 /* EEPROM access above 16k is unsupported */ 211 if (size > 14) 212 size = 14; 213 nvm->word_size = 1 << size; 214 215 /* Function Pointers */ 216 nvm->ops.acquire = e1000_acquire_nvm_82575; 217 nvm->ops.read = e1000_read_nvm_eerd; 218 nvm->ops.release = e1000_release_nvm_82575; 219 nvm->ops.update = e1000_update_nvm_checksum_generic; 220 nvm->ops.valid_led_default = e1000_valid_led_default_82575; 221 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 222 nvm->ops.write = e1000_write_nvm_spi; 223 224 return (E1000_SUCCESS); 225 } 226 227 /* 228 * e1000_init_mac_params_82575 - Init MAC func ptrs. 229 * @hw: pointer to the HW structure 230 */ 231 static s32 232 e1000_init_mac_params_82575(struct e1000_hw *hw) 233 { 234 struct e1000_mac_info *mac = &hw->mac; 235 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 236 u32 ctrl_ext = 0; 237 238 DEBUGFUNC("e1000_init_mac_params_82575"); 239 240 /* Set media type */ 241 /* 242 * The 82575 uses bits 22:23 for link mode. The mode can be changed 243 * based on the EEPROM. We cannot rely upon device ID. There 244 * is no distinguishable difference between fiber and internal 245 * SerDes mode on the 82575. There can be an external PHY attached 246 * on the SGMII interface. For this, we'll set sgmii_active to true. 247 */ 248 hw->phy.media_type = e1000_media_type_copper; 249 dev_spec->sgmii_active = false; 250 251 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 252 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 253 case E1000_CTRL_EXT_LINK_MODE_SGMII: 254 dev_spec->sgmii_active = true; 255 ctrl_ext |= E1000_CTRL_I2C_ENA; 256 break; 257 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 258 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 259 hw->phy.media_type = e1000_media_type_internal_serdes; 260 ctrl_ext |= E1000_CTRL_I2C_ENA; 261 break; 262 default: 263 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 264 break; 265 } 266 267 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 268 269 /* Set mta register count */ 270 mac->mta_reg_count = 128; 271 /* Set uta register count */ 272 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 273 /* Set rar entry count */ 274 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 275 if (mac->type == e1000_82576) 276 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 277 if (mac->type == e1000_82580) 278 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 279 /* Set if part includes ASF firmware */ 280 mac->asf_firmware_present = true; 281 /* Set if manageability features are enabled. */ 282 mac->arc_subsystem_valid = 283 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 284 ? true : false; 285 286 /* Function pointers */ 287 288 /* bus type/speed/width */ 289 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 290 /* reset */ 291 if (mac->type == e1000_82580) 292 mac->ops.reset_hw = e1000_reset_hw_82580; 293 else 294 mac->ops.reset_hw = e1000_reset_hw_82575; 295 /* hw initialization */ 296 mac->ops.init_hw = e1000_init_hw_82575; 297 /* link setup */ 298 mac->ops.setup_link = e1000_setup_link_generic; 299 /* physical interface link setup */ 300 mac->ops.setup_physical_interface = 301 (hw->phy.media_type == e1000_media_type_copper) 302 ? e1000_setup_copper_link_82575 303 : e1000_setup_serdes_link_82575; 304 /* physical interface shutdown */ 305 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 306 /* check for link */ 307 mac->ops.check_for_link = e1000_check_for_link_82575; 308 /* receive address register setting */ 309 mac->ops.rar_set = e1000_rar_set_generic; 310 /* read mac address */ 311 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 312 /* multicast address update */ 313 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 314 /* writing VFTA */ 315 mac->ops.write_vfta = e1000_write_vfta_generic; 316 /* clearing VFTA */ 317 mac->ops.clear_vfta = e1000_clear_vfta_generic; 318 /* setting MTA */ 319 mac->ops.mta_set = e1000_mta_set_generic; 320 /* ID LED init */ 321 mac->ops.id_led_init = e1000_id_led_init_generic; 322 /* blink LED */ 323 mac->ops.blink_led = e1000_blink_led_generic; 324 /* setup LED */ 325 mac->ops.setup_led = e1000_setup_led_generic; 326 /* cleanup LED */ 327 mac->ops.cleanup_led = e1000_cleanup_led_generic; 328 /* turn on/off LED */ 329 mac->ops.led_on = e1000_led_on_generic; 330 mac->ops.led_off = e1000_led_off_generic; 331 /* clear hardware counters */ 332 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 333 /* link info */ 334 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 335 336 /* set lan id for port to determine which phy lock to use */ 337 hw->mac.ops.set_lan_id(hw); 338 339 return (E1000_SUCCESS); 340 } 341 342 /* 343 * e1000_init_function_pointers_82575 - Init func ptrs. 344 * @hw: pointer to the HW structure 345 * 346 * Called to initialize all function pointers and parameters. 347 */ 348 void 349 e1000_init_function_pointers_82575(struct e1000_hw *hw) 350 { 351 DEBUGFUNC("e1000_init_function_pointers_82575"); 352 353 hw->mac.ops.init_params = e1000_init_mac_params_82575; 354 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 355 hw->phy.ops.init_params = e1000_init_phy_params_82575; 356 } 357 358 /* 359 * e1000_acquire_phy_82575 - Acquire rights to access PHY 360 * @hw: pointer to the HW structure 361 * 362 * Acquire access rights to the correct PHY. 363 */ 364 static s32 365 e1000_acquire_phy_82575(struct e1000_hw *hw) 366 { 367 u16 mask = E1000_SWFW_PHY0_SM; 368 369 DEBUGFUNC("e1000_acquire_phy_82575"); 370 371 if (hw->bus.func == E1000_FUNC_1) 372 mask = E1000_SWFW_PHY1_SM; 373 else if (hw->bus.func == E1000_FUNC_2) 374 mask = E1000_SWFW_PHY2_SM; 375 else if (hw->bus.func == E1000_FUNC_3) 376 mask = E1000_SWFW_PHY3_SM; 377 378 return (e1000_acquire_swfw_sync_82575(hw, mask)); 379 } 380 381 /* 382 * e1000_release_phy_82575 - Release rights to access PHY 383 * @hw: pointer to the HW structure 384 * 385 * A wrapper to release access rights to the correct PHY. 386 */ 387 static void 388 e1000_release_phy_82575(struct e1000_hw *hw) 389 { 390 u16 mask = E1000_SWFW_PHY0_SM; 391 392 DEBUGFUNC("e1000_release_phy_82575"); 393 394 if (hw->bus.func == E1000_FUNC_1) 395 mask = E1000_SWFW_PHY1_SM; 396 else if (hw->bus.func == E1000_FUNC_2) 397 mask = E1000_SWFW_PHY2_SM; 398 else if (hw->bus.func == E1000_FUNC_3) 399 mask = E1000_SWFW_PHY3_SM; 400 401 e1000_release_swfw_sync_82575(hw, mask); 402 } 403 404 /* 405 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 406 * @hw: pointer to the HW structure 407 * @offset: register offset to be read 408 * @data: pointer to the read data 409 * 410 * Reads the PHY register at offset using the serial gigabit media independent 411 * interface and stores the retrieved information in data. 412 */ 413 static s32 414 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 *data) 415 { 416 s32 ret_val = -E1000_ERR_PARAM; 417 418 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 419 420 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 421 DEBUGOUT1("PHY Address %u is out of range\n", offset); 422 goto out; 423 } 424 425 ret_val = hw->phy.ops.acquire(hw); 426 if (ret_val) 427 goto out; 428 429 ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 430 431 hw->phy.ops.release(hw); 432 433 out: 434 return (ret_val); 435 } 436 437 /* 438 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 439 * @hw: pointer to the HW structure 440 * @offset: register offset to write to 441 * @data: data to write at register offset 442 * 443 * Writes the data to PHY register at the offset using the serial gigabit 444 * media independent interface. 445 */ 446 static s32 447 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 data) 448 { 449 s32 ret_val = -E1000_ERR_PARAM; 450 451 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 452 453 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 454 DEBUGOUT1("PHY Address %d is out of range\n", offset); 455 goto out; 456 } 457 458 ret_val = hw->phy.ops.acquire(hw); 459 if (ret_val) 460 goto out; 461 462 ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 463 464 hw->phy.ops.release(hw); 465 466 out: 467 return (ret_val); 468 } 469 470 /* 471 * e1000_get_phy_id_82575 - Retrieve PHY addr and id 472 * @hw: pointer to the HW structure 473 * 474 * Retrieves the PHY address and ID for both PHY's which do and do not use 475 * sgmi interface. 476 */ 477 static s32 478 e1000_get_phy_id_82575(struct e1000_hw *hw) 479 { 480 struct e1000_phy_info *phy = &hw->phy; 481 s32 ret_val = E1000_SUCCESS; 482 u16 phy_id; 483 u32 ctrl_ext; 484 485 DEBUGFUNC("e1000_get_phy_id_82575"); 486 487 /* 488 * For SGMII PHYs, we try the list of possible addresses until 489 * we find one that works. For non-SGMII PHYs 490 * (e.g. integrated copper PHYs), an address of 1 should 491 * work. The result of this function should mean phy->phy_addr 492 * and phy->id are set correctly. 493 */ 494 if (!e1000_sgmii_active_82575(hw)) { 495 phy->addr = 1; 496 ret_val = e1000_get_phy_id(hw); 497 goto out; 498 } 499 500 /* Power on sgmii phy if it is disabled */ 501 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 502 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 503 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 504 E1000_WRITE_FLUSH(hw); 505 msec_delay(300); 506 507 /* 508 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 509 * Therefore, we need to test 1-7 510 */ 511 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 512 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 513 if (ret_val == E1000_SUCCESS) { 514 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 515 phy_id, 516 phy->addr); 517 /* 518 * At the time of this writing, The M88 part is 519 * the only supported SGMII PHY product. 520 */ 521 if (phy_id == M88_VENDOR) 522 break; 523 } else { 524 DEBUGOUT1("PHY address %u was unreadable\n", 525 phy->addr); 526 } 527 } 528 529 /* A valid PHY type couldn't be found. */ 530 if (phy->addr == 8) { 531 phy->addr = 0; 532 ret_val = -E1000_ERR_PHY; 533 } else { 534 ret_val = e1000_get_phy_id(hw); 535 } 536 537 /* restore previous sfp cage power state */ 538 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 539 540 out: 541 return (ret_val); 542 } 543 544 /* 545 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 546 * @hw: pointer to the HW structure 547 * 548 * Resets the PHY using the serial gigabit media independent interface. 549 */ 550 static s32 551 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 552 { 553 s32 ret_val = E1000_SUCCESS; 554 555 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 556 557 /* 558 * This isn't a true "hard" reset, but is the only reset 559 * available to us at this time. 560 */ 561 562 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 563 564 if (!(hw->phy.ops.write_reg)) 565 goto out; 566 567 /* 568 * SFP documentation requires the following to configure the SPF module 569 * to work on SGMII. No further documentation is given. 570 */ 571 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 572 if (ret_val) 573 goto out; 574 575 ret_val = hw->phy.ops.commit(hw); 576 577 out: 578 return (ret_val); 579 } 580 581 /* 582 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 583 * @hw: pointer to the HW structure 584 * @active: true to enable LPLU, false to disable 585 * 586 * Sets the LPLU D0 state according to the active flag. When 587 * activating LPLU this function also disables smart speed 588 * and vice versa. LPLU will not be activated unless the 589 * device autonegotiation advertisement meets standards of 590 * either 10 or 10/100 or 10/100/1000 at all duplexes. 591 * This is a function pointer entry point only called by 592 * PHY setup routines. 593 */ 594 static s32 595 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 596 { 597 struct e1000_phy_info *phy = &hw->phy; 598 s32 ret_val = E1000_SUCCESS; 599 u16 data; 600 601 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 602 603 if (!(hw->phy.ops.read_reg)) 604 goto out; 605 606 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 607 if (ret_val) 608 goto out; 609 610 if (active) { 611 data |= IGP02E1000_PM_D0_LPLU; 612 ret_val = phy->ops.write_reg(hw, 613 IGP02E1000_PHY_POWER_MGMT, 614 data); 615 if (ret_val) 616 goto out; 617 618 /* When LPLU is enabled, we should disable SmartSpeed */ 619 ret_val = phy->ops.read_reg(hw, 620 IGP01E1000_PHY_PORT_CONFIG, 621 &data); 622 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 623 ret_val = phy->ops.write_reg(hw, 624 IGP01E1000_PHY_PORT_CONFIG, 625 data); 626 if (ret_val) 627 goto out; 628 } else { 629 data &= ~IGP02E1000_PM_D0_LPLU; 630 ret_val = phy->ops.write_reg(hw, 631 IGP02E1000_PHY_POWER_MGMT, 632 data); 633 /* 634 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 635 * during Dx states where the power conservation is most 636 * important. During driver activity we should enable 637 * SmartSpeed, so performance is maintained. 638 */ 639 if (phy->smart_speed == e1000_smart_speed_on) { 640 ret_val = phy->ops.read_reg(hw, 641 IGP01E1000_PHY_PORT_CONFIG, 642 &data); 643 if (ret_val) 644 goto out; 645 646 data |= IGP01E1000_PSCFR_SMART_SPEED; 647 ret_val = phy->ops.write_reg(hw, 648 IGP01E1000_PHY_PORT_CONFIG, 649 data); 650 if (ret_val) 651 goto out; 652 } else if (phy->smart_speed == e1000_smart_speed_off) { 653 ret_val = phy->ops.read_reg(hw, 654 IGP01E1000_PHY_PORT_CONFIG, 655 &data); 656 if (ret_val) 657 goto out; 658 659 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 660 ret_val = phy->ops.write_reg(hw, 661 IGP01E1000_PHY_PORT_CONFIG, 662 data); 663 if (ret_val) 664 goto out; 665 } 666 } 667 668 out: 669 return (ret_val); 670 } 671 672 /* 673 * e1000_acquire_nvm_82575 - Request for access to EEPROM 674 * @hw: pointer to the HW structure 675 * 676 * Acquire the necessary semaphores for exclusive access to the EEPROM. 677 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 678 * Return successful if access grant bit set, else clear the request for 679 * EEPROM access and return -E1000_ERR_NVM (-1). 680 */ 681 static s32 682 e1000_acquire_nvm_82575(struct e1000_hw *hw) 683 { 684 s32 ret_val; 685 686 DEBUGFUNC("e1000_acquire_nvm_82575"); 687 688 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 689 if (ret_val) 690 goto out; 691 692 ret_val = e1000_acquire_nvm_generic(hw); 693 694 if (ret_val) 695 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 696 697 out: 698 return (ret_val); 699 } 700 701 /* 702 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 703 * @hw: pointer to the HW structure 704 * 705 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 706 * then release the semaphores acquired. 707 */ 708 static void 709 e1000_release_nvm_82575(struct e1000_hw *hw) 710 { 711 DEBUGFUNC("e1000_release_nvm_82575"); 712 713 e1000_release_nvm_generic(hw); 714 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 715 } 716 717 /* 718 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 719 * @hw: pointer to the HW structure 720 * @mask: specifies which semaphore to acquire 721 * 722 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 723 * will also specify which port we're acquiring the lock for. 724 */ 725 static s32 726 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 727 { 728 u32 swfw_sync; 729 u32 swmask = mask; 730 u32 fwmask = mask << 16; 731 s32 ret_val = E1000_SUCCESS; 732 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 733 734 DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 735 736 while (i < timeout) { 737 if (e1000_get_hw_semaphore_generic(hw)) { 738 ret_val = -E1000_ERR_SWFW_SYNC; 739 goto out; 740 } 741 742 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 743 if (!(swfw_sync & (fwmask | swmask))) 744 break; 745 746 /* 747 * Firmware currently using resource (fwmask) 748 * or other software thread using resource (swmask) 749 */ 750 e1000_put_hw_semaphore_generic(hw); 751 msec_delay_irq(5); 752 i++; 753 } 754 755 if (i == timeout) { 756 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 757 ret_val = -E1000_ERR_SWFW_SYNC; 758 goto out; 759 } 760 761 swfw_sync |= swmask; 762 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 763 764 e1000_put_hw_semaphore_generic(hw); 765 766 out: 767 return (ret_val); 768 } 769 770 /* 771 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 772 * @hw: pointer to the HW structure 773 * @mask: specifies which semaphore to acquire 774 * 775 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 776 * will also specify which port we're releasing the lock for. 777 */ 778 static void 779 e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 780 { 781 u32 swfw_sync; 782 783 DEBUGFUNC("e1000_release_swfw_sync_82575"); 784 785 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) { 786 /* Empty */ 787 } 788 789 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 790 swfw_sync &= ~mask; 791 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 792 793 e1000_put_hw_semaphore_generic(hw); 794 } 795 796 /* 797 * e1000_get_cfg_done_82575 - Read config done bit 798 * @hw: pointer to the HW structure 799 * 800 * Read the management control register for the config done bit for 801 * completion status. NOTE: silicon which is EEPROM-less will fail trying 802 * to read the config done bit, so an error is *ONLY* logged and returns 803 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 804 * would not be able to be reset or change link. 805 */ 806 static s32 807 e1000_get_cfg_done_82575(struct e1000_hw *hw) 808 { 809 s32 timeout = PHY_CFG_TIMEOUT; 810 s32 ret_val = E1000_SUCCESS; 811 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 812 813 DEBUGFUNC("e1000_get_cfg_done_82575"); 814 815 if (hw->bus.func == E1000_FUNC_1) 816 mask = E1000_NVM_CFG_DONE_PORT_1; 817 else if (hw->bus.func == E1000_FUNC_2) 818 mask = E1000_NVM_CFG_DONE_PORT_2; 819 else if (hw->bus.func == E1000_FUNC_3) 820 mask = E1000_NVM_CFG_DONE_PORT_3; 821 822 while (timeout) { 823 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 824 break; 825 msec_delay(1); 826 timeout--; 827 } 828 if (!timeout) 829 DEBUGOUT("MNG configuration cycle has not completed.\n"); 830 831 /* If EEPROM is not marked present, init the PHY manually */ 832 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 833 (hw->phy.type == e1000_phy_igp_3)) 834 (void) e1000_phy_init_script_igp3(hw); 835 836 return (ret_val); 837 } 838 839 /* 840 * e1000_get_link_up_info_82575 - Get link speed/duplex info 841 * @hw: pointer to the HW structure 842 * @speed: stores the current speed 843 * @duplex: stores the current duplex 844 * 845 * This is a wrapper function, if using the serial gigabit media independent 846 * interface, use PCS to retrieve the link speed and duplex information. 847 * Otherwise, use the generic function to get the link speed and duplex info. 848 */ 849 static s32 850 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, u16 *duplex) 851 { 852 s32 ret_val; 853 854 DEBUGFUNC("e1000_get_link_up_info_82575"); 855 856 if (hw->phy.media_type != e1000_media_type_copper) 857 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 858 duplex); 859 else 860 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 861 duplex); 862 863 return (ret_val); 864 } 865 866 /* 867 * e1000_check_for_link_82575 - Check for link 868 * @hw: pointer to the HW structure 869 * 870 * If sgmii is enabled, then use the pcs register to determine link, otherwise 871 * use the generic interface for determining link. 872 */ 873 static s32 874 e1000_check_for_link_82575(struct e1000_hw *hw) 875 { 876 s32 ret_val; 877 u16 speed, duplex; 878 879 DEBUGFUNC("e1000_check_for_link_82575"); 880 881 /* SGMII link check is done through the PCS register. */ 882 if (hw->phy.media_type != e1000_media_type_copper) { 883 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 884 &duplex); 885 /* 886 * Use this flag to determine if link needs to be checked or 887 * not. If we have link clear the flag so that we do not 888 * continue to check for link. 889 */ 890 hw->mac.get_link_status = !hw->mac.serdes_has_link; 891 } else { 892 ret_val = e1000_check_for_copper_link_generic(hw); 893 } 894 895 return (ret_val); 896 } 897 898 /* 899 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 900 * @hw: pointer to the HW structure 901 * @speed: stores the current speed 902 * @duplex: stores the current duplex 903 * 904 * Using the physical coding sub-layer (PCS), retrieve the current speed and 905 * duplex, then store the values in the pointers provided. 906 */ 907 static s32 908 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 909 u16 *speed, u16 *duplex) 910 { 911 struct e1000_mac_info *mac = &hw->mac; 912 u32 pcs; 913 914 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 915 916 /* Set up defaults for the return values of this function */ 917 mac->serdes_has_link = false; 918 *speed = 0; 919 *duplex = 0; 920 921 /* 922 * Read the PCS Status register for link state. For non-copper mode, 923 * the status register is not accurate. The PCS status register is 924 * used instead. 925 */ 926 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 927 928 /* 929 * The link up bit determines when link is up on autoneg. The sync ok 930 * gets set once both sides sync up and agree upon link. Stable link 931 * can be determined by checking for both link up and link sync ok 932 */ 933 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 934 mac->serdes_has_link = true; 935 936 /* Detect and store PCS speed */ 937 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 938 *speed = SPEED_1000; 939 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 940 *speed = SPEED_100; 941 } else { 942 *speed = SPEED_10; 943 } 944 945 /* Detect and store PCS duplex */ 946 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 947 *duplex = FULL_DUPLEX; 948 } else { 949 *duplex = HALF_DUPLEX; 950 } 951 } 952 953 return (E1000_SUCCESS); 954 } 955 956 /* 957 * e1000_shutdown_serdes_link_82575 - Remove link during power down 958 * @hw: pointer to the HW structure 959 * 960 * In the case of serdes shut down sfp and PCS on driver unload 961 * when management pass thru is not enabled. 962 */ 963 void 964 e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 965 { 966 u32 reg; 967 u16 eeprom_data = 0; 968 969 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 970 !e1000_sgmii_active_82575(hw)) 971 return; 972 973 if (hw->bus.func == E1000_FUNC_0) 974 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 975 else if (hw->mac.type == e1000_82580) 976 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 977 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 978 &eeprom_data); 979 else if (hw->bus.func == E1000_FUNC_1) 980 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 981 982 /* 983 * If APM is not enabled in the EEPROM and management interface is 984 * not enabled, then power down. 985 */ 986 if (!(eeprom_data & E1000_NVM_APME_82575) && 987 !e1000_enable_mng_pass_thru(hw)) { 988 /* Disable PCS to turn off link */ 989 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 990 reg &= ~E1000_PCS_CFG_PCS_EN; 991 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 992 993 /* shutdown the laser */ 994 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 995 reg |= E1000_CTRL_EXT_SDP3_DATA; 996 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 997 998 /* flush the write to verify completion */ 999 E1000_WRITE_FLUSH(hw); 1000 msec_delay(1); 1001 } 1002 } 1003 1004 /* 1005 * e1000_reset_hw_82575 - Reset hardware 1006 * @hw: pointer to the HW structure 1007 * 1008 * This resets the hardware into a known state. 1009 */ 1010 static s32 1011 e1000_reset_hw_82575(struct e1000_hw *hw) 1012 { 1013 u32 ctrl; 1014 s32 ret_val; 1015 1016 DEBUGFUNC("e1000_reset_hw_82575"); 1017 1018 /* 1019 * Prevent the PCI-E bus from sticking if there is no TLP connection 1020 * on the last TLP read/write transaction when MAC is reset. 1021 */ 1022 ret_val = e1000_disable_pcie_master_generic(hw); 1023 if (ret_val) { 1024 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1025 } 1026 1027 /* set the completion timeout for interface */ 1028 ret_val = e1000_set_pcie_completion_timeout(hw); 1029 if (ret_val) { 1030 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1031 } 1032 1033 DEBUGOUT("Masking off all interrupts\n"); 1034 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1035 1036 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1037 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1038 E1000_WRITE_FLUSH(hw); 1039 1040 msec_delay(10); 1041 1042 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1043 1044 DEBUGOUT("Issuing a global reset to MAC\n"); 1045 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1046 1047 ret_val = e1000_get_auto_rd_done_generic(hw); 1048 if (ret_val) { 1049 /* 1050 * When auto config read does not complete, do not 1051 * return with an error. This can happen in situations 1052 * where there is no eeprom and prevents getting link. 1053 */ 1054 DEBUGOUT("Auto Read Done did not complete\n"); 1055 } 1056 1057 /* If EEPROM is not present, run manual init scripts */ 1058 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1059 (void) e1000_reset_init_script_82575(hw); 1060 1061 /* Clear any pending interrupt events. */ 1062 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1063 (void) E1000_READ_REG(hw, E1000_ICR); 1064 1065 /* Install any alternate MAC address into RAR0 */ 1066 ret_val = e1000_check_alt_mac_addr_generic(hw); 1067 1068 return (ret_val); 1069 } 1070 1071 /* 1072 * e1000_init_hw_82575 - Initialize hardware 1073 * @hw: pointer to the HW structure 1074 * 1075 * This inits the hardware readying it for operation. 1076 */ 1077 static s32 1078 e1000_init_hw_82575(struct e1000_hw *hw) 1079 { 1080 struct e1000_mac_info *mac = &hw->mac; 1081 s32 ret_val; 1082 u16 i, rar_count = mac->rar_entry_count; 1083 1084 DEBUGFUNC("e1000_init_hw_82575"); 1085 1086 /* Initialize identification LED */ 1087 ret_val = mac->ops.id_led_init(hw); 1088 if (ret_val) { 1089 DEBUGOUT("Error initializing identification LED\n"); 1090 /* This is not fatal and we should not stop init due to this */ 1091 } 1092 1093 /* Disabling VLAN filtering */ 1094 DEBUGOUT("Initializing the IEEE VLAN\n"); 1095 mac->ops.clear_vfta(hw); 1096 1097 /* Setup the receive address */ 1098 e1000_init_rx_addrs_generic(hw, rar_count); 1099 /* Zero out the Multicast HASH table */ 1100 DEBUGOUT("Zeroing the MTA\n"); 1101 for (i = 0; i < mac->mta_reg_count; i++) 1102 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1103 1104 /* Zero out the Unicast HASH table */ 1105 DEBUGOUT("Zeroing the UTA\n"); 1106 for (i = 0; i < mac->uta_reg_count; i++) 1107 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 1108 1109 /* Setup link and flow control */ 1110 ret_val = mac->ops.setup_link(hw); 1111 1112 /* 1113 * Clear all of the statistics registers (clear on read). It is 1114 * important that we do this after we have tried to establish link 1115 * because the symbol error count will increment wildly if there 1116 * is no link. 1117 */ 1118 e1000_clear_hw_cntrs_82575(hw); 1119 1120 return (ret_val); 1121 } 1122 1123 /* 1124 * e1000_setup_copper_link_82575 - Configure copper link settings 1125 * @hw: pointer to the HW structure 1126 * 1127 * Configures the link for auto-neg or forced speed and duplex. Then we check 1128 * for link, once link is established calls to configure collision distance 1129 * and flow control are called. 1130 */ 1131 static s32 1132 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1133 { 1134 u32 ctrl; 1135 s32 ret_val; 1136 1137 DEBUGFUNC("e1000_setup_copper_link_82575"); 1138 1139 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1140 ctrl |= E1000_CTRL_SLU; 1141 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1142 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1143 1144 ret_val = e1000_setup_serdes_link_82575(hw); 1145 if (ret_val) 1146 goto out; 1147 1148 if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 1149 ret_val = hw->phy.ops.reset(hw); 1150 if (ret_val) { 1151 DEBUGOUT("Error resetting the PHY.\n"); 1152 goto out; 1153 } 1154 } 1155 switch (hw->phy.type) { 1156 case e1000_phy_m88: 1157 ret_val = e1000_copper_link_setup_m88(hw); 1158 break; 1159 case e1000_phy_igp_3: 1160 ret_val = e1000_copper_link_setup_igp(hw); 1161 break; 1162 case e1000_phy_82580: 1163 ret_val = e1000_copper_link_setup_82577(hw); 1164 break; 1165 default: 1166 ret_val = -E1000_ERR_PHY; 1167 break; 1168 } 1169 1170 if (ret_val) 1171 goto out; 1172 1173 ret_val = e1000_setup_copper_link_generic(hw); 1174 out: 1175 return (ret_val); 1176 } 1177 1178 /* 1179 * e1000_setup_serdes_link_82575 - Setup link for serdes 1180 * @hw: pointer to the HW structure 1181 * 1182 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1183 * used on copper connections where the serialized gigabit media independent 1184 * interface (sgmii), or serdes fiber is being used. Configures the link 1185 * for auto-negotiation or forces speed/duplex. 1186 */ 1187 static s32 1188 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1189 { 1190 u32 ctrl_reg, reg; 1191 1192 DEBUGFUNC("e1000_setup_serdes_link_82575"); 1193 1194 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1195 !e1000_sgmii_active_82575(hw)) 1196 return (E1000_SUCCESS); 1197 1198 /* 1199 * On the 82575, SerDes loopback mode persists until it is 1200 * explicitly turned off or a power cycle is performed. A read to 1201 * the register does not indicate its status. Therefore, we ensure 1202 * loopback mode is disabled during initialization. 1203 */ 1204 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1205 1206 /* power on the sfp cage if present */ 1207 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1208 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1209 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1210 1211 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1212 ctrl_reg |= E1000_CTRL_SLU; 1213 1214 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { 1215 /* set both sw defined pins */ 1216 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1217 1218 /* Set switch control to serdes energy detect */ 1219 reg = E1000_READ_REG(hw, E1000_CONNSW); 1220 reg |= E1000_CONNSW_ENRGSRC; 1221 E1000_WRITE_REG(hw, E1000_CONNSW, reg); 1222 } 1223 1224 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1225 1226 if (e1000_sgmii_active_82575(hw)) { 1227 /* allow time for SFP cage to power up phy */ 1228 msec_delay(300); 1229 1230 /* AN time out should be disabled for SGMII mode */ 1231 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1232 } else { 1233 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1234 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1235 } 1236 1237 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1238 1239 /* 1240 * New SerDes mode allows for forcing speed or autonegotiating speed 1241 * at 1gb. Autoneg should be default set by most drivers. This is the 1242 * mode that will be compatible with older link partners and switches. 1243 * However, both are supported by the hardware and some drivers/tools. 1244 */ 1245 1246 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1247 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1248 1249 /* 1250 * We force flow control to prevent the CTRL register values from being 1251 * overwritten by the autonegotiated flow control values 1252 */ 1253 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1254 1255 /* 1256 * we always set sgmii to autoneg since it is the phy that will be 1257 * forcing the link and the serdes is just a go-between 1258 */ 1259 if (hw->mac.autoneg || e1000_sgmii_active_82575(hw)) { 1260 /* Set PCS register for autoneg */ 1261 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1262 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full dplx */ 1263 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1264 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1265 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1266 } else { 1267 /* Check for duplex first */ 1268 if (hw->mac.forced_speed_duplex & E1000_ALL_FULL_DUPLEX) 1269 reg |= E1000_PCS_LCTL_FDV_FULL; 1270 1271 /* 1272 * No need to check for 1000/full since the spec states that 1273 * it requires autoneg to be enabled 1274 */ 1275 1276 /* Now set speed */ 1277 if (hw->mac.forced_speed_duplex & E1000_ALL_100_SPEED) 1278 reg |= E1000_PCS_LCTL_FSV_100; 1279 1280 /* Force speed and force link */ 1281 reg |= E1000_PCS_LCTL_FSD | 1282 E1000_PCS_LCTL_FORCE_LINK | 1283 E1000_PCS_LCTL_FLV_LINK_UP; 1284 1285 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1286 } 1287 1288 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1289 1290 if (!e1000_sgmii_active_82575(hw)) 1291 (void) e1000_force_mac_fc_generic(hw); 1292 1293 return (E1000_SUCCESS); 1294 } 1295 1296 /* 1297 * e1000_valid_led_default_82575 - Verify a valid default LED config 1298 * @hw: pointer to the HW structure 1299 * @data: pointer to the NVM (EEPROM) 1300 * 1301 * Read the EEPROM for the current default LED configuration. If the 1302 * LED configuration is not valid, set to a valid LED configuration. 1303 */ 1304 static s32 1305 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1306 { 1307 s32 ret_val; 1308 1309 DEBUGFUNC("e1000_valid_led_default_82575"); 1310 1311 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1312 if (ret_val) { 1313 DEBUGOUT("NVM Read Error\n"); 1314 goto out; 1315 } 1316 1317 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1318 switch (hw->phy.media_type) { 1319 case e1000_media_type_internal_serdes: 1320 *data = ID_LED_DEFAULT_82575_SERDES; 1321 break; 1322 case e1000_media_type_copper: 1323 default: 1324 *data = ID_LED_DEFAULT; 1325 break; 1326 } 1327 } 1328 out: 1329 return (ret_val); 1330 } 1331 1332 /* 1333 * e1000_sgmii_active_82575 - Return sgmii state 1334 * @hw: pointer to the HW structure 1335 * 1336 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1337 * which can be enabled for use in the embedded applications. Simply 1338 * return the current state of the sgmii interface. 1339 */ 1340 static bool 1341 e1000_sgmii_active_82575(struct e1000_hw *hw) 1342 { 1343 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1344 return (dev_spec->sgmii_active); 1345 } 1346 1347 /* 1348 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1349 * @hw: pointer to the HW structure 1350 * 1351 * Inits recommended HW defaults after a reset when there is no EEPROM 1352 * detected. This is only for the 82575. 1353 */ 1354 static s32 1355 e1000_reset_init_script_82575(struct e1000_hw *hw) 1356 { 1357 DEBUGFUNC("e1000_reset_init_script_82575"); 1358 1359 if (hw->mac.type == e1000_82575) { 1360 DEBUGOUT("Running reset init script for 82575\n"); 1361 /* SerDes configuration via SERDESCTRL */ 1362 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 1363 0x00, 0x0C); 1364 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 1365 0x01, 0x78); 1366 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 1367 0x1B, 0x23); 1368 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 1369 0x23, 0x15); 1370 1371 /* CCM configuration via CCMCTL register */ 1372 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 1373 0x14, 0x00); 1374 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 1375 0x10, 0x00); 1376 1377 /* PCIe lanes configuration */ 1378 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 1379 0x00, 0xEC); 1380 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 1381 0x61, 0xDF); 1382 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 1383 0x34, 0x05); 1384 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 1385 0x2F, 0x81); 1386 1387 /* PCIe PLL Configuration */ 1388 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 1389 0x02, 0x47); 1390 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 1391 0x14, 0x00); 1392 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 1393 0x10, 0x00); 1394 } 1395 1396 return (E1000_SUCCESS); 1397 } 1398 1399 /* 1400 * e1000_read_mac_addr_82575 - Read device MAC address 1401 * @hw: pointer to the HW structure 1402 */ 1403 static s32 1404 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1405 { 1406 s32 ret_val = E1000_SUCCESS; 1407 1408 DEBUGFUNC("e1000_read_mac_addr_82575"); 1409 1410 /* 1411 * If there's an alternate MAC address place it in RAR0 1412 * so that it will override the Si installed default perm 1413 * address. 1414 */ 1415 ret_val = e1000_check_alt_mac_addr_generic(hw); 1416 if (ret_val) 1417 goto out; 1418 1419 ret_val = e1000_read_mac_addr_generic(hw); 1420 1421 out: 1422 return (ret_val); 1423 } 1424 1425 /* 1426 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1427 * @hw: pointer to the HW structure 1428 * 1429 * In the case of a PHY power down to save power, or to turn off link during a 1430 * driver unload, or wake on lan is not enabled, remove the link. 1431 */ 1432 static void 1433 e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1434 { 1435 struct e1000_phy_info *phy = &hw->phy; 1436 struct e1000_mac_info *mac = &hw->mac; 1437 1438 if (!(phy->ops.check_reset_block)) 1439 return; 1440 1441 /* If the management interface is not enabled, then power down */ 1442 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1443 e1000_power_down_phy_copper(hw); 1444 } 1445 1446 /* 1447 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1448 * @hw: pointer to the HW structure 1449 * 1450 * Clears the hardware counters by reading the counter registers. 1451 */ 1452 static void 1453 e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1454 { 1455 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1456 1457 e1000_clear_hw_cntrs_base_generic(hw); 1458 1459 (void) E1000_READ_REG(hw, E1000_PRC64); 1460 (void) E1000_READ_REG(hw, E1000_PRC127); 1461 (void) E1000_READ_REG(hw, E1000_PRC255); 1462 (void) E1000_READ_REG(hw, E1000_PRC511); 1463 (void) E1000_READ_REG(hw, E1000_PRC1023); 1464 (void) E1000_READ_REG(hw, E1000_PRC1522); 1465 (void) E1000_READ_REG(hw, E1000_PTC64); 1466 (void) E1000_READ_REG(hw, E1000_PTC127); 1467 (void) E1000_READ_REG(hw, E1000_PTC255); 1468 (void) E1000_READ_REG(hw, E1000_PTC511); 1469 (void) E1000_READ_REG(hw, E1000_PTC1023); 1470 (void) E1000_READ_REG(hw, E1000_PTC1522); 1471 1472 (void) E1000_READ_REG(hw, E1000_ALGNERRC); 1473 (void) E1000_READ_REG(hw, E1000_RXERRC); 1474 (void) E1000_READ_REG(hw, E1000_TNCRS); 1475 (void) E1000_READ_REG(hw, E1000_CEXTERR); 1476 (void) E1000_READ_REG(hw, E1000_TSCTC); 1477 (void) E1000_READ_REG(hw, E1000_TSCTFC); 1478 1479 (void) E1000_READ_REG(hw, E1000_MGTPRC); 1480 (void) E1000_READ_REG(hw, E1000_MGTPDC); 1481 (void) E1000_READ_REG(hw, E1000_MGTPTC); 1482 1483 (void) E1000_READ_REG(hw, E1000_IAC); 1484 (void) E1000_READ_REG(hw, E1000_ICRXOC); 1485 1486 (void) E1000_READ_REG(hw, E1000_ICRXPTC); 1487 (void) E1000_READ_REG(hw, E1000_ICRXATC); 1488 (void) E1000_READ_REG(hw, E1000_ICTXPTC); 1489 (void) E1000_READ_REG(hw, E1000_ICTXATC); 1490 (void) E1000_READ_REG(hw, E1000_ICTXQEC); 1491 (void) E1000_READ_REG(hw, E1000_ICTXQMTC); 1492 (void) E1000_READ_REG(hw, E1000_ICRXDMTC); 1493 1494 (void) E1000_READ_REG(hw, E1000_CBTMPC); 1495 (void) E1000_READ_REG(hw, E1000_HTDPMC); 1496 (void) E1000_READ_REG(hw, E1000_CBRMPC); 1497 (void) E1000_READ_REG(hw, E1000_RPTHC); 1498 (void) E1000_READ_REG(hw, E1000_HGPTC); 1499 (void) E1000_READ_REG(hw, E1000_HTCBDPC); 1500 (void) E1000_READ_REG(hw, E1000_HGORCL); 1501 (void) E1000_READ_REG(hw, E1000_HGORCH); 1502 (void) E1000_READ_REG(hw, E1000_HGOTCL); 1503 (void) E1000_READ_REG(hw, E1000_HGOTCH); 1504 (void) E1000_READ_REG(hw, E1000_LENERRS); 1505 1506 /* This register should not be read in copper configurations */ 1507 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 1508 e1000_sgmii_active_82575(hw)) 1509 (void) E1000_READ_REG(hw, E1000_SCVPC); 1510 } 1511 1512 /* 1513 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1514 * @hw: pointer to the HW structure 1515 * 1516 * After rx enable if managability is enabled then there is likely some 1517 * bad data at the start of the fifo and possibly in the DMA fifo. This 1518 * function clears the fifos and flushes any packets that came in as rx was 1519 * being enabled. 1520 */ 1521 void 1522 e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 1523 { 1524 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1525 int i, ms_wait; 1526 1527 DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 1528 if (hw->mac.type != e1000_82575 || 1529 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1530 return; 1531 1532 /* Disable all RX queues */ 1533 for (i = 0; i < 4; i++) { 1534 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 1535 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 1536 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1537 } 1538 /* Poll all queues to verify they have shut down */ 1539 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1540 msec_delay(1); 1541 rx_enabled = 0; 1542 for (i = 0; i < 4; i++) 1543 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 1544 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1545 break; 1546 } 1547 1548 if (ms_wait == 10) 1549 DEBUGOUT("Queue disable timed out after 10ms\n"); 1550 1551 /* 1552 * Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1553 * incoming packets are rejected. Set enable and wait 2ms so that 1554 * any packet that was coming in as RCTL.EN was set is flushed 1555 */ 1556 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 1557 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1558 1559 rlpml = E1000_READ_REG(hw, E1000_RLPML); 1560 E1000_WRITE_REG(hw, E1000_RLPML, 0); 1561 1562 rctl = E1000_READ_REG(hw, E1000_RCTL); 1563 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1564 temp_rctl |= E1000_RCTL_LPE; 1565 1566 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 1567 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1568 E1000_WRITE_FLUSH(hw); 1569 msec_delay(2); 1570 1571 /* 1572 * Enable RX queues that were previously enabled and restore our 1573 * previous state 1574 */ 1575 for (i = 0; i < 4; i++) 1576 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 1577 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1578 E1000_WRITE_FLUSH(hw); 1579 1580 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 1581 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 1582 1583 /* Flush receive errors generated by workaround */ 1584 (void) E1000_READ_REG(hw, E1000_ROC); 1585 (void) E1000_READ_REG(hw, E1000_RNBC); 1586 (void) E1000_READ_REG(hw, E1000_MPC); 1587 } 1588 1589 /* 1590 * e1000_set_pcie_completion_timeout - set pci-e completion timeout 1591 * @hw: pointer to the HW structure 1592 * 1593 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 1594 * however the hardware default for these parts is 500us to 1ms which is less 1595 * than the 10ms recommended by the pci-e spec. To address this we need to 1596 * increase the value to either 10ms to 200ms for capability version 1 config, 1597 * or 16ms to 55ms for version 2. 1598 */ 1599 static s32 1600 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 1601 { 1602 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 1603 s32 ret_val = E1000_SUCCESS; 1604 u16 pcie_devctl2; 1605 1606 /* only take action if timeout value is defaulted to 0 */ 1607 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 1608 goto out; 1609 1610 /* 1611 * if capababilities version is type 1 we can write the 1612 * timeout of 10ms to 200ms through the GCR register 1613 */ 1614 if (!(gcr & E1000_GCR_CAP_VER2)) { 1615 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 1616 goto out; 1617 } 1618 1619 /* 1620 * for version 2 capabilities we need to write the config space 1621 * directly in order to set the completion timeout value for 1622 * 16ms to 55ms 1623 */ 1624 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1625 &pcie_devctl2); 1626 if (ret_val) 1627 goto out; 1628 1629 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 1630 1631 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1632 &pcie_devctl2); 1633 out: 1634 /* disable completion timeout resend */ 1635 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 1636 1637 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1638 return (ret_val); 1639 } 1640 1641 /* 1642 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 1643 * @hw: pointer to the hardware struct 1644 * @enable: state to enter, either enabled or disabled 1645 * 1646 * enables/disables L2 switch loopback functionality. 1647 */ 1648 void 1649 e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 1650 { 1651 u32 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 1652 1653 if (enable) 1654 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1655 else 1656 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1657 1658 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 1659 } 1660 1661 /* 1662 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 1663 * @hw: pointer to the hardware struct 1664 * @enable: state to enter, either enabled or disabled 1665 * 1666 * enables/disables replication of packets across multiple pools. 1667 */ 1668 void 1669 e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 1670 { 1671 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 1672 1673 if (enable) 1674 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 1675 else 1676 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 1677 1678 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 1679 } 1680 1681 /* 1682 * e1000_read_phy_reg_82580 - Read 82580 MDI control register 1683 * @hw: pointer to the HW structure 1684 * @offset: register offset to be read 1685 * @data: pointer to the read data 1686 * 1687 * Reads the MDI control register in the PHY at offset and stores the 1688 * information read to data. 1689 */ 1690 static s32 1691 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 1692 { 1693 u32 mdicnfg = 0; 1694 s32 ret_val; 1695 1696 DEBUGFUNC("e1000_read_phy_reg_82580"); 1697 1698 ret_val = hw->phy.ops.acquire(hw); 1699 if (ret_val) 1700 goto out; 1701 1702 /* 1703 * We config the phy address in MDICNFG register now. Same bits 1704 * as before. The values in MDIC can be written but will be 1705 * ignored. This allows us to call the old function after 1706 * configuring the PHY address in the new register 1707 */ 1708 mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT); 1709 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 1710 1711 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 1712 1713 hw->phy.ops.release(hw); 1714 1715 out: 1716 return (ret_val); 1717 } 1718 1719 /* 1720 * e1000_write_phy_reg_82580 - Write 82580 MDI control register 1721 * @hw: pointer to the HW structure 1722 * @offset: register offset to write to 1723 * @data: data to write to register at offset 1724 * 1725 * Writes data to MDI control register in the PHY at offset. 1726 */ 1727 static s32 1728 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 1729 { 1730 u32 mdicnfg = 0; 1731 s32 ret_val; 1732 1733 DEBUGFUNC("e1000_write_phy_reg_82580"); 1734 1735 ret_val = hw->phy.ops.acquire(hw); 1736 if (ret_val) 1737 goto out; 1738 1739 /* 1740 * We config the phy address in MDICNFG register now. Same bits 1741 * as before. The values in MDIC can be written but will be 1742 * ignored. This allows us to call the old function after 1743 * configuring the PHY address in the new register 1744 */ 1745 mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT); 1746 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 1747 1748 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 1749 1750 hw->phy.ops.release(hw); 1751 1752 out: 1753 return (ret_val); 1754 } 1755 1756 /* 1757 * e1000_reset_hw_82580 - Reset hardware 1758 * @hw: pointer to the HW structure 1759 * 1760 * This resets function or entire device (all ports, etc.) 1761 * to a known state. 1762 */ 1763 static s32 1764 e1000_reset_hw_82580(struct e1000_hw *hw) 1765 { 1766 s32 ret_val = E1000_SUCCESS; 1767 /* BH SW mailbox bit in SW_FW_SYNC */ 1768 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 1769 u32 ctrl; 1770 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 1771 1772 DEBUGFUNC("e1000_reset_hw_82580"); 1773 1774 hw->dev_spec._82575.global_device_reset = false; 1775 1776 /* Get current control state. */ 1777 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1778 1779 /* 1780 * Prevent the PCI-E bus from sticking if there is no TLP connection 1781 * on the last TLP read/write transaction when MAC is reset. 1782 */ 1783 ret_val = e1000_disable_pcie_master_generic(hw); 1784 if (ret_val) 1785 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1786 1787 DEBUGOUT("Masking off all interrupts\n"); 1788 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1789 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1790 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1791 E1000_WRITE_FLUSH(hw); 1792 1793 msec_delay(10); 1794 1795 /* Determine whether or not a global dev reset is requested */ 1796 if (global_device_reset && 1797 e1000_acquire_swfw_sync_82575(hw, swmbsw_mask)) 1798 global_device_reset = false; 1799 1800 if (global_device_reset && 1801 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET)) 1802 ctrl |= E1000_CTRL_DEV_RST; 1803 else 1804 ctrl |= E1000_CTRL_RST; 1805 1806 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1807 1808 /* Add delay to insure DEV_RST has time to complete */ 1809 if (global_device_reset) 1810 msec_delay(5); 1811 1812 ret_val = e1000_get_auto_rd_done_generic(hw); 1813 if (ret_val) { 1814 /* 1815 * When auto config read does not complete, do not 1816 * return with an error. This can happen in situations 1817 * where there is no eeprom and prevents getting link. 1818 */ 1819 DEBUGOUT("Auto Read Done did not complete\n"); 1820 } 1821 1822 /* If EEPROM is not present, run manual init scripts */ 1823 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1824 (void) e1000_reset_init_script_82575(hw); 1825 1826 /* clear global device reset status bit */ 1827 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 1828 1829 /* Clear any pending interrupt events. */ 1830 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1831 (void) E1000_READ_REG(hw, E1000_ICR); 1832 1833 /* Install any alternate MAC address into RAR0 */ 1834 ret_val = e1000_check_alt_mac_addr_generic(hw); 1835 1836 /* Release semaphore */ 1837 if (global_device_reset) 1838 e1000_release_swfw_sync_82575(hw, swmbsw_mask); 1839 1840 return (ret_val); 1841 } 1842 1843 /* 1844 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size 1845 * @data: data received by reading RXPBS register 1846 * 1847 * The 82580 uses a table based approach for packet buffer allocation sizes. 1848 * This function converts the retrieved value into the correct table value 1849 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 1850 * 0x0 36 72 144 1 2 4 8 16 1851 * 0x8 35 70 140 rsv rsv rsv rsv rsv 1852 */ 1853 u16 1854 e1000_rxpbs_adjust_82580(u32 data) 1855 { 1856 u16 ret_val = 0; 1857 1858 if (data < E1000_82580_RXPBS_TABLE_SIZE) 1859 ret_val = e1000_82580_rxpbs_table[data]; 1860 1861 return (ret_val); 1862 } 1863
Indexes created Wed Feb 10 04:24:43 UTC 2010
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