1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.123 v2-9-8_2009-6-12 */ 30 31 /* 32 * 82575EB Gigabit Network Connection 33 * 82575EB Gigabit Backplane Connection 34 * 82575GB Gigabit Network Connection 35 * 82576 Gigabit Network Connection 36 * 82576 Quad Port Gigabit Mezzanine Adapter 37 */ 38 39 #include "igb_api.h" 40 41 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 42 static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 43 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 44 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 45 static void e1000_release_phy_82575(struct e1000_hw *hw); 46 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 47 static void e1000_release_nvm_82575(struct e1000_hw *hw); 48 static s32 e1000_check_for_link_82575(struct e1000_hw *hw); 49 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 50 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 51 u16 *duplex); 52 static s32 e1000_init_hw_82575(struct e1000_hw *hw); 53 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 54 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 55 u16 *data); 56 static s32 e1000_reset_hw_82575(struct e1000_hw *hw); 57 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 58 bool active); 59 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 60 static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw); 61 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 62 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 63 u32 offset, u16 data); 64 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 65 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 66 static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw); 67 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 68 u16 *speed, u16 *duplex); 69 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 70 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 71 static bool e1000_sgmii_active_82575(struct e1000_hw *hw); 72 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 73 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 74 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 75 void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw); 76 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 77 78 /* 79 * e1000_init_phy_params_82575 - Init PHY func ptrs. 80 * @hw: pointer to the HW structure 81 */ 82 static s32 83 e1000_init_phy_params_82575(struct e1000_hw *hw) 84 { 85 struct e1000_phy_info *phy = &hw->phy; 86 s32 ret_val = E1000_SUCCESS; 87 88 DEBUGFUNC("e1000_init_phy_params_82575"); 89 90 if (hw->phy.media_type != e1000_media_type_copper) { 91 phy->type = e1000_phy_none; 92 goto out; 93 } else { 94 phy->ops.power_up = e1000_power_up_phy_copper; 95 phy->ops.power_down = e1000_power_down_phy_copper_82575; 96 } 97 98 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 99 phy->reset_delay_us = 100; 100 101 phy->ops.acquire = e1000_acquire_phy_82575; 102 phy->ops.check_reset_block = e1000_check_reset_block_generic; 103 phy->ops.commit = e1000_phy_sw_reset_generic; 104 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 105 phy->ops.release = e1000_release_phy_82575; 106 107 if (e1000_sgmii_active_82575(hw)) { 108 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 109 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 110 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 111 } else { 112 phy->ops.reset = e1000_phy_hw_reset_generic; 113 phy->ops.read_reg = e1000_read_phy_reg_igp; 114 phy->ops.write_reg = e1000_write_phy_reg_igp; 115 } 116 117 /* Set phy->phy_addr and phy->id. */ 118 ret_val = e1000_get_phy_id_82575(hw); 119 120 /* Verify phy id and set remaining function pointers */ 121 switch (phy->id) { 122 case M88E1111_I_PHY_ID: 123 phy->type = e1000_phy_m88; 124 phy->ops.check_polarity = e1000_check_polarity_m88; 125 phy->ops.get_info = e1000_get_phy_info_m88; 126 phy->ops.get_cable_length = e1000_get_cable_length_m88; 127 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 128 break; 129 case IGP03E1000_E_PHY_ID: 130 case IGP04E1000_E_PHY_ID: 131 phy->type = e1000_phy_igp_3; 132 phy->ops.check_polarity = e1000_check_polarity_igp; 133 phy->ops.get_info = e1000_get_phy_info_igp; 134 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 135 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 136 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 137 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 138 break; 139 default: 140 ret_val = -E1000_ERR_PHY; 141 goto out; 142 } 143 144 out: 145 return (ret_val); 146 } 147 148 /* 149 * e1000_init_nvm_params_82575 - Init NVM func ptrs. 150 * @hw: pointer to the HW structure 151 */ 152 static s32 153 e1000_init_nvm_params_82575(struct e1000_hw *hw) 154 { 155 struct e1000_nvm_info *nvm = &hw->nvm; 156 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 157 u16 size; 158 159 DEBUGFUNC("e1000_init_nvm_params_82575"); 160 161 nvm->opcode_bits = 8; 162 nvm->delay_usec = 1; 163 switch (nvm->override) { 164 case e1000_nvm_override_spi_large: 165 nvm->page_size = 32; 166 nvm->address_bits = 16; 167 break; 168 case e1000_nvm_override_spi_small: 169 nvm->page_size = 8; 170 nvm->address_bits = 8; 171 break; 172 default: 173 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 174 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 175 break; 176 } 177 178 nvm->type = e1000_nvm_eeprom_spi; 179 180 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 181 E1000_EECD_SIZE_EX_SHIFT); 182 183 /* 184 * Added to a constant, "size" becomes the left-shift value 185 * for setting word_size. 186 */ 187 size += NVM_WORD_SIZE_BASE_SHIFT; 188 189 /* EEPROM access above 16k is unsupported */ 190 if (size > 14) 191 size = 14; 192 nvm->word_size = 1 << size; 193 194 /* Function Pointers */ 195 nvm->ops.acquire = e1000_acquire_nvm_82575; 196 nvm->ops.read = e1000_read_nvm_eerd; 197 nvm->ops.release = e1000_release_nvm_82575; 198 nvm->ops.update = e1000_update_nvm_checksum_generic; 199 nvm->ops.valid_led_default = e1000_valid_led_default_82575; 200 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 201 nvm->ops.write = e1000_write_nvm_spi; 202 203 return (E1000_SUCCESS); 204 } 205 206 /* 207 * e1000_init_mac_params_82575 - Init MAC func ptrs. 208 * @hw: pointer to the HW structure 209 */ 210 static s32 211 e1000_init_mac_params_82575(struct e1000_hw *hw) 212 { 213 struct e1000_mac_info *mac = &hw->mac; 214 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 215 u32 ctrl_ext = 0; 216 217 DEBUGFUNC("e1000_init_mac_params_82575"); 218 219 /* Set media type */ 220 /* 221 * The 82575 uses bits 22:23 for link mode. The mode can be changed 222 * based on the EEPROM. We cannot rely upon device ID. There 223 * is no distinguishable difference between fiber and internal 224 * SerDes mode on the 82575. There can be an external PHY attached 225 * on the SGMII interface. For this, we'll set sgmii_active to true. 226 */ 227 hw->phy.media_type = e1000_media_type_copper; 228 dev_spec->sgmii_active = false; 229 230 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 231 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) == 232 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) { 233 hw->phy.media_type = e1000_media_type_internal_serdes; 234 ctrl_ext |= E1000_CTRL_I2C_ENA; 235 } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) { 236 dev_spec->sgmii_active = true; 237 ctrl_ext |= E1000_CTRL_I2C_ENA; 238 } else { 239 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 240 } 241 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 242 243 /* Set mta register count */ 244 mac->mta_reg_count = 128; 245 /* Set rar entry count */ 246 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 247 if (mac->type == e1000_82576) 248 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 249 /* Set if part includes ASF firmware */ 250 mac->asf_firmware_present = true; 251 /* Set if manageability features are enabled. */ 252 mac->arc_subsystem_valid = 253 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 254 ? true : false; 255 256 /* Function pointers */ 257 258 /* bus type/speed/width */ 259 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 260 /* reset */ 261 mac->ops.reset_hw = e1000_reset_hw_82575; 262 /* hw initialization */ 263 mac->ops.init_hw = e1000_init_hw_82575; 264 /* link setup */ 265 mac->ops.setup_link = e1000_setup_link_generic; 266 /* physical interface link setup */ 267 mac->ops.setup_physical_interface = 268 (hw->phy.media_type == e1000_media_type_copper) 269 ? e1000_setup_copper_link_82575 270 : e1000_setup_fiber_serdes_link_82575; 271 /* physical interface shutdown */ 272 mac->ops.shutdown_serdes = e1000_shutdown_fiber_serdes_link_82575; 273 /* check for link */ 274 mac->ops.check_for_link = e1000_check_for_link_82575; 275 /* receive address register setting */ 276 mac->ops.rar_set = e1000_rar_set_generic; 277 /* read mac address */ 278 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 279 /* multicast address update */ 280 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 281 /* writing VFTA */ 282 mac->ops.write_vfta = e1000_write_vfta_generic; 283 /* clearing VFTA */ 284 mac->ops.clear_vfta = e1000_clear_vfta_generic; 285 /* setting MTA */ 286 mac->ops.mta_set = e1000_mta_set_generic; 287 /* ID LED init */ 288 mac->ops.id_led_init = e1000_id_led_init_generic; 289 /* blink LED */ 290 mac->ops.blink_led = e1000_blink_led_generic; 291 /* setup LED */ 292 mac->ops.setup_led = e1000_setup_led_generic; 293 /* cleanup LED */ 294 mac->ops.cleanup_led = e1000_cleanup_led_generic; 295 /* turn on/off LED */ 296 mac->ops.led_on = e1000_led_on_generic; 297 mac->ops.led_off = e1000_led_off_generic; 298 /* clear hardware counters */ 299 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 300 /* link info */ 301 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 302 303 return (E1000_SUCCESS); 304 } 305 306 /* 307 * e1000_init_function_pointers_82575 - Init func ptrs. 308 * @hw: pointer to the HW structure 309 * 310 * Called to initialize all function pointers and parameters. 311 */ 312 void 313 e1000_init_function_pointers_82575(struct e1000_hw *hw) 314 { 315 DEBUGFUNC("e1000_init_function_pointers_82575"); 316 317 hw->mac.ops.init_params = e1000_init_mac_params_82575; 318 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 319 hw->phy.ops.init_params = e1000_init_phy_params_82575; 320 } 321 322 /* 323 * e1000_acquire_phy_82575 - Acquire rights to access PHY 324 * @hw: pointer to the HW structure 325 * 326 * Acquire access rights to the correct PHY. 327 */ 328 static s32 329 e1000_acquire_phy_82575(struct e1000_hw *hw) 330 { 331 u16 mask = E1000_SWFW_PHY0_SM; 332 333 DEBUGFUNC("e1000_acquire_phy_82575"); 334 335 if (hw->bus.func == E1000_FUNC_1) 336 mask = E1000_SWFW_PHY1_SM; 337 338 return (e1000_acquire_swfw_sync_82575(hw, mask)); 339 } 340 341 /* 342 * e1000_release_phy_82575 - Release rights to access PHY 343 * @hw: pointer to the HW structure 344 * 345 * A wrapper to release access rights to the correct PHY. 346 */ 347 static void 348 e1000_release_phy_82575(struct e1000_hw *hw) 349 { 350 u16 mask = E1000_SWFW_PHY0_SM; 351 352 DEBUGFUNC("e1000_release_phy_82575"); 353 354 if (hw->bus.func == E1000_FUNC_1) 355 mask = E1000_SWFW_PHY1_SM; 356 357 e1000_release_swfw_sync_82575(hw, mask); 358 } 359 360 /* 361 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 362 * @hw: pointer to the HW structure 363 * @offset: register offset to be read 364 * @data: pointer to the read data 365 * 366 * Reads the PHY register at offset using the serial gigabit media independent 367 * interface and stores the retrieved information in data. 368 */ 369 static s32 370 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 *data) 371 { 372 struct e1000_phy_info *phy = &hw->phy; 373 u32 i, i2ccmd = 0; 374 375 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 376 377 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 378 DEBUGOUT1("PHY Address %u is out of range\n", offset); 379 return (-E1000_ERR_PARAM); 380 } 381 382 /* 383 * Set up Op-code, Phy Address, and register address in the I2CCMD 384 * register. The MAC will take care of interfacing with the 385 * PHY to retrieve the desired data. 386 */ 387 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 388 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 389 (E1000_I2CCMD_OPCODE_READ)); 390 391 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 392 393 /* Poll the ready bit to see if the I2C read completed */ 394 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 395 usec_delay(50); 396 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 397 if (i2ccmd & E1000_I2CCMD_READY) 398 break; 399 } 400 if (!(i2ccmd & E1000_I2CCMD_READY)) { 401 DEBUGOUT("I2CCMD Read did not complete\n"); 402 return (-E1000_ERR_PHY); 403 } 404 if (i2ccmd & E1000_I2CCMD_ERROR) { 405 DEBUGOUT("I2CCMD Error bit set\n"); 406 return (-E1000_ERR_PHY); 407 } 408 409 /* Need to byte-swap the 16-bit value. */ 410 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 411 412 return (E1000_SUCCESS); 413 } 414 415 /* 416 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 417 * @hw: pointer to the HW structure 418 * @offset: register offset to write to 419 * @data: data to write at register offset 420 * 421 * Writes the data to PHY register at the offset using the serial gigabit 422 * media independent interface. 423 */ 424 static s32 425 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 data) 426 { 427 struct e1000_phy_info *phy = &hw->phy; 428 u32 i, i2ccmd = 0; 429 u16 phy_data_swapped; 430 431 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 432 433 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 434 DEBUGOUT1("PHY Address %d is out of range\n", offset); 435 return (-E1000_ERR_PARAM); 436 } 437 438 /* Swap the data bytes for the I2C interface */ 439 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 440 441 /* 442 * Set up Op-code, Phy Address, and register address in the I2CCMD 443 * register. The MAC will take care of interfacing with the 444 * PHY to retrieve the desired data. 445 */ 446 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 447 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 448 E1000_I2CCMD_OPCODE_WRITE | 449 phy_data_swapped); 450 451 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 452 453 /* Poll the ready bit to see if the I2C read completed */ 454 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 455 usec_delay(50); 456 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 457 if (i2ccmd & E1000_I2CCMD_READY) 458 break; 459 } 460 if (!(i2ccmd & E1000_I2CCMD_READY)) { 461 DEBUGOUT("I2CCMD Write did not complete\n"); 462 return (-E1000_ERR_PHY); 463 } 464 if (i2ccmd & E1000_I2CCMD_ERROR) { 465 DEBUGOUT("I2CCMD Error bit set\n"); 466 return (-E1000_ERR_PHY); 467 } 468 469 return (E1000_SUCCESS); 470 } 471 472 /* 473 * e1000_get_phy_id_82575 - Retrieve PHY addr and id 474 * @hw: pointer to the HW structure 475 * 476 * Retrieves the PHY address and ID for both PHY's which do and do not use 477 * sgmi interface. 478 */ 479 static s32 480 e1000_get_phy_id_82575(struct e1000_hw *hw) 481 { 482 struct e1000_phy_info *phy = &hw->phy; 483 s32 ret_val = E1000_SUCCESS; 484 u16 phy_id; 485 486 DEBUGFUNC("e1000_get_phy_id_82575"); 487 488 /* 489 * For SGMII PHYs, we try the list of possible addresses until 490 * we find one that works. For non-SGMII PHYs 491 * (e.g. integrated copper PHYs), an address of 1 should 492 * work. The result of this function should mean phy->phy_addr 493 * and phy->id are set correctly. 494 */ 495 if (!(e1000_sgmii_active_82575(hw))) { 496 phy->addr = 1; 497 ret_val = e1000_get_phy_id(hw); 498 goto out; 499 } 500 501 /* 502 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 503 * Therefore, we need to test 1-7 504 */ 505 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 506 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 507 if (ret_val == E1000_SUCCESS) { 508 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 509 phy_id, 510 phy->addr); 511 /* 512 * At the time of this writing, The M88 part is 513 * the only supported SGMII PHY product. 514 */ 515 if (phy_id == M88_VENDOR) 516 break; 517 } else { 518 DEBUGOUT1("PHY address %u was unreadable\n", 519 phy->addr); 520 } 521 } 522 523 /* A valid PHY type couldn't be found. */ 524 if (phy->addr == 8) { 525 phy->addr = 0; 526 ret_val = -E1000_ERR_PHY; 527 goto out; 528 } 529 530 ret_val = e1000_get_phy_id(hw); 531 532 out: 533 return (ret_val); 534 } 535 536 /* 537 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 538 * @hw: pointer to the HW structure 539 * 540 * Resets the PHY using the serial gigabit media independent interface. 541 */ 542 static s32 543 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 544 { 545 s32 ret_val = E1000_SUCCESS; 546 547 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 548 549 /* 550 * This isn't a true "hard" reset, but is the only reset 551 * available to us at this time. 552 */ 553 554 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 555 556 if (!(hw->phy.ops.write_reg)) 557 goto out; 558 559 /* 560 * SFP documentation requires the following to configure the SPF module 561 * to work on SGMII. No further documentation is given. 562 */ 563 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 564 if (ret_val) 565 goto out; 566 567 ret_val = hw->phy.ops.commit(hw); 568 569 out: 570 return (ret_val); 571 } 572 573 /* 574 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 575 * @hw: pointer to the HW structure 576 * @active: true to enable LPLU, false to disable 577 * 578 * Sets the LPLU D0 state according to the active flag. When 579 * activating LPLU this function also disables smart speed 580 * and vice versa. LPLU will not be activated unless the 581 * device autonegotiation advertisement meets standards of 582 * either 10 or 10/100 or 10/100/1000 at all duplexes. 583 * This is a function pointer entry point only called by 584 * PHY setup routines. 585 */ 586 static s32 587 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 588 { 589 struct e1000_phy_info *phy = &hw->phy; 590 s32 ret_val = E1000_SUCCESS; 591 u16 data; 592 593 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 594 595 if (!(hw->phy.ops.read_reg)) 596 goto out; 597 598 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 599 if (ret_val) 600 goto out; 601 602 if (active) { 603 data |= IGP02E1000_PM_D0_LPLU; 604 ret_val = phy->ops.write_reg(hw, 605 IGP02E1000_PHY_POWER_MGMT, 606 data); 607 if (ret_val) 608 goto out; 609 610 /* When LPLU is enabled, we should disable SmartSpeed */ 611 ret_val = phy->ops.read_reg(hw, 612 IGP01E1000_PHY_PORT_CONFIG, 613 &data); 614 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 615 ret_val = phy->ops.write_reg(hw, 616 IGP01E1000_PHY_PORT_CONFIG, 617 data); 618 if (ret_val) 619 goto out; 620 } else { 621 data &= ~IGP02E1000_PM_D0_LPLU; 622 ret_val = phy->ops.write_reg(hw, 623 IGP02E1000_PHY_POWER_MGMT, 624 data); 625 /* 626 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 627 * during Dx states where the power conservation is most 628 * important. During driver activity we should enable 629 * SmartSpeed, so performance is maintained. 630 */ 631 if (phy->smart_speed == e1000_smart_speed_on) { 632 ret_val = phy->ops.read_reg(hw, 633 IGP01E1000_PHY_PORT_CONFIG, 634 &data); 635 if (ret_val) 636 goto out; 637 638 data |= IGP01E1000_PSCFR_SMART_SPEED; 639 ret_val = phy->ops.write_reg(hw, 640 IGP01E1000_PHY_PORT_CONFIG, 641 data); 642 if (ret_val) 643 goto out; 644 } else if (phy->smart_speed == e1000_smart_speed_off) { 645 ret_val = phy->ops.read_reg(hw, 646 IGP01E1000_PHY_PORT_CONFIG, 647 &data); 648 if (ret_val) 649 goto out; 650 651 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 652 ret_val = phy->ops.write_reg(hw, 653 IGP01E1000_PHY_PORT_CONFIG, 654 data); 655 if (ret_val) 656 goto out; 657 } 658 } 659 660 out: 661 return (ret_val); 662 } 663 664 /* 665 * e1000_acquire_nvm_82575 - Request for access to EEPROM 666 * @hw: pointer to the HW structure 667 * 668 * Acquire the necessary semaphores for exclusive access to the EEPROM. 669 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 670 * Return successful if access grant bit set, else clear the request for 671 * EEPROM access and return -E1000_ERR_NVM (-1). 672 */ 673 static s32 674 e1000_acquire_nvm_82575(struct e1000_hw *hw) 675 { 676 s32 ret_val; 677 678 DEBUGFUNC("e1000_acquire_nvm_82575"); 679 680 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 681 if (ret_val) 682 goto out; 683 684 ret_val = e1000_acquire_nvm_generic(hw); 685 686 if (ret_val) 687 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 688 689 out: 690 return (ret_val); 691 } 692 693 /* 694 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 695 * @hw: pointer to the HW structure 696 * 697 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 698 * then release the semaphores acquired. 699 */ 700 static void 701 e1000_release_nvm_82575(struct e1000_hw *hw) 702 { 703 DEBUGFUNC("e1000_release_nvm_82575"); 704 705 e1000_release_nvm_generic(hw); 706 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 707 } 708 709 /* 710 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 711 * @hw: pointer to the HW structure 712 * @mask: specifies which semaphore to acquire 713 * 714 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 715 * will also specify which port we're acquiring the lock for. 716 */ 717 static s32 718 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 719 { 720 u32 swfw_sync; 721 u32 swmask = mask; 722 u32 fwmask = mask << 16; 723 s32 ret_val = E1000_SUCCESS; 724 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 725 726 DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 727 728 while (i < timeout) { 729 if (e1000_get_hw_semaphore_generic(hw)) { 730 ret_val = -E1000_ERR_SWFW_SYNC; 731 goto out; 732 } 733 734 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 735 if (!(swfw_sync & (fwmask | swmask))) 736 break; 737 738 /* 739 * Firmware currently using resource (fwmask) 740 * or other software thread using resource (swmask) 741 */ 742 e1000_put_hw_semaphore_generic(hw); 743 msec_delay_irq(5); 744 i++; 745 } 746 747 if (i == timeout) { 748 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 749 ret_val = -E1000_ERR_SWFW_SYNC; 750 goto out; 751 } 752 753 swfw_sync |= swmask; 754 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 755 756 e1000_put_hw_semaphore_generic(hw); 757 758 out: 759 return (ret_val); 760 } 761 762 /* 763 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 764 * @hw: pointer to the HW structure 765 * @mask: specifies which semaphore to acquire 766 * 767 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 768 * will also specify which port we're releasing the lock for. 769 */ 770 static void 771 e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 772 { 773 u32 swfw_sync; 774 775 DEBUGFUNC("e1000_release_swfw_sync_82575"); 776 777 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) { 778 /* Empty */ 779 } 780 781 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 782 swfw_sync &= ~mask; 783 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 784 785 e1000_put_hw_semaphore_generic(hw); 786 } 787 788 /* 789 * e1000_get_cfg_done_82575 - Read config done bit 790 * @hw: pointer to the HW structure 791 * 792 * Read the management control register for the config done bit for 793 * completion status. NOTE: silicon which is EEPROM-less will fail trying 794 * to read the config done bit, so an error is *ONLY* logged and returns 795 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 796 * would not be able to be reset or change link. 797 */ 798 static s32 799 e1000_get_cfg_done_82575(struct e1000_hw *hw) 800 { 801 s32 timeout = PHY_CFG_TIMEOUT; 802 s32 ret_val = E1000_SUCCESS; 803 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 804 805 DEBUGFUNC("e1000_get_cfg_done_82575"); 806 807 if (hw->bus.func == E1000_FUNC_1) 808 mask = E1000_NVM_CFG_DONE_PORT_1; 809 810 while (timeout) { 811 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 812 break; 813 msec_delay(1); 814 timeout--; 815 } 816 if (!timeout) { 817 DEBUGOUT("MNG configuration cycle has not completed.\n"); 818 } 819 820 /* If EEPROM is not marked present, init the PHY manually */ 821 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 822 (hw->phy.type == e1000_phy_igp_3)) { 823 (void) e1000_phy_init_script_igp3(hw); 824 } 825 return (ret_val); 826 } 827 828 /* 829 * e1000_get_link_up_info_82575 - Get link speed/duplex info 830 * @hw: pointer to the HW structure 831 * @speed: stores the current speed 832 * @duplex: stores the current duplex 833 * 834 * This is a wrapper function, if using the serial gigabit media independent 835 * interface, use PCS to retrieve the link speed and duplex information. 836 * Otherwise, use the generic function to get the link speed and duplex info. 837 */ 838 static s32 839 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, u16 *duplex) 840 { 841 s32 ret_val; 842 843 DEBUGFUNC("e1000_get_link_up_info_82575"); 844 845 if (hw->phy.media_type != e1000_media_type_copper || 846 e1000_sgmii_active_82575(hw)) { 847 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 848 duplex); 849 } else { 850 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 851 duplex); 852 } 853 854 return (ret_val); 855 } 856 857 /* 858 * e1000_check_for_link_82575 - Check for link 859 * @hw: pointer to the HW structure 860 * 861 * If sgmii is enabled, then use the pcs register to determine link, otherwise 862 * use the generic interface for determining link. 863 */ 864 static s32 865 e1000_check_for_link_82575(struct e1000_hw *hw) 866 { 867 s32 ret_val; 868 u16 speed, duplex; 869 870 DEBUGFUNC("e1000_check_for_link_82575"); 871 872 /* SGMII link check is done through the PCS register. */ 873 if ((hw->phy.media_type != e1000_media_type_copper) || 874 (e1000_sgmii_active_82575(hw))) { 875 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 876 &duplex); 877 /* 878 * Use this flag to determine if link needs to be checked or 879 * not. If we have link clear the flag so that we do not 880 * continue to check for link. 881 */ 882 hw->mac.get_link_status = !hw->mac.serdes_has_link; 883 } else { 884 ret_val = e1000_check_for_copper_link_generic(hw); 885 } 886 887 return (ret_val); 888 } 889 890 /* 891 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 892 * @hw: pointer to the HW structure 893 * @speed: stores the current speed 894 * @duplex: stores the current duplex 895 * 896 * Using the physical coding sub-layer (PCS), retrieve the current speed and 897 * duplex, then store the values in the pointers provided. 898 */ 899 static s32 900 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 901 u16 *speed, u16 *duplex) 902 { 903 struct e1000_mac_info *mac = &hw->mac; 904 u32 pcs; 905 906 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 907 908 /* Set up defaults for the return values of this function */ 909 mac->serdes_has_link = false; 910 *speed = 0; 911 *duplex = 0; 912 913 /* 914 * Read the PCS Status register for link state. For non-copper mode, 915 * the status register is not accurate. The PCS status register is 916 * used instead. 917 */ 918 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 919 920 /* 921 * The link up bit determines when link is up on autoneg. The sync ok 922 * gets set once both sides sync up and agree upon link. Stable link 923 * can be determined by checking for both link up and link sync ok 924 */ 925 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 926 mac->serdes_has_link = true; 927 928 /* Detect and store PCS speed */ 929 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 930 *speed = SPEED_1000; 931 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 932 *speed = SPEED_100; 933 } else { 934 *speed = SPEED_10; 935 } 936 937 /* Detect and store PCS duplex */ 938 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 939 *duplex = FULL_DUPLEX; 940 } else { 941 *duplex = HALF_DUPLEX; 942 } 943 } 944 945 return (E1000_SUCCESS); 946 } 947 948 /* 949 * e1000_shutdown_fiber_serdes_link_82575 - Remove link during power down 950 * @hw: pointer to the HW structure 951 * 952 * In the case of fiber serdes shut down optics and PCS on driver unload 953 * when management pass thru is not enabled. 954 */ 955 void 956 e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw) 957 { 958 u32 reg; 959 u16 eeprom_data = 0; 960 961 if (hw->phy.media_type != e1000_media_type_internal_serdes) 962 return; 963 964 if (hw->bus.func == E1000_FUNC_0) 965 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 966 else if (hw->bus.func == E1000_FUNC_1) 967 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 968 969 /* 970 * If APM is not enabled in the EEPROM and management interface is 971 * not enabled, then power down. 972 */ 973 if (!(eeprom_data & E1000_NVM_APME_82575) && 974 !e1000_enable_mng_pass_thru(hw)) { 975 /* Disable PCS to turn off link */ 976 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 977 reg &= ~E1000_PCS_CFG_PCS_EN; 978 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 979 980 /* shutdown the laser */ 981 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 982 reg |= E1000_CTRL_EXT_SDP7_DATA; 983 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 984 985 /* flush the write to verfiy completion */ 986 E1000_WRITE_FLUSH(hw); 987 msec_delay(1); 988 } 989 } 990 991 /* 992 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 993 * @hw: pointer to the HW structure 994 * @enable: state to enter, either enabled or disabled 995 * 996 * enables/disables L2 switch loopback functionality 997 */ 998 void 999 e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 1000 { 1001 u32 reg; 1002 1003 reg = E1000_READ_REG(hw, E1000_DTXSWC); 1004 if (enable) 1005 reg |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1006 else 1007 reg &= ~(E1000_DTXSWC_VMDQ_LOOPBACK_EN); 1008 1009 E1000_WRITE_REG(hw, E1000_DTXSWC, reg); 1010 } 1011 1012 /* 1013 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 1014 * @hw: pointer to the HW structure 1015 * @enable: state to enter, either enabled or disabled 1016 * 1017 * enables/disables replication of packets across multiple pools 1018 */ 1019 void 1020 e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 1021 { 1022 u32 reg; 1023 1024 reg = E1000_READ_REG(hw, E1000_VT_CTL); 1025 if (enable) 1026 reg |= E1000_VT_CTL_VM_REPL_EN; 1027 else 1028 reg &= ~(E1000_VT_CTL_VM_REPL_EN); 1029 1030 E1000_WRITE_REG(hw, E1000_VT_CTL, reg); 1031 } 1032 1033 /* 1034 * e1000_reset_hw_82575 - Reset hardware 1035 * @hw: pointer to the HW structure 1036 * 1037 * This resets the hardware into a known state. 1038 */ 1039 static s32 1040 e1000_reset_hw_82575(struct e1000_hw *hw) 1041 { 1042 u32 ctrl; 1043 s32 ret_val; 1044 1045 DEBUGFUNC("e1000_reset_hw_82575"); 1046 1047 /* 1048 * Prevent the PCI-E bus from sticking if there is no TLP connection 1049 * on the last TLP read/write transaction when MAC is reset. 1050 */ 1051 ret_val = e1000_disable_pcie_master_generic(hw); 1052 if (ret_val) { 1053 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1054 } 1055 1056 /* set the completion timeout for interface */ 1057 ret_val = e1000_set_pcie_completion_timeout(hw); 1058 if (ret_val) { 1059 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1060 } 1061 1062 DEBUGOUT("Masking off all interrupts\n"); 1063 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1064 1065 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1066 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1067 E1000_WRITE_FLUSH(hw); 1068 1069 msec_delay(10); 1070 1071 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1072 1073 DEBUGOUT("Issuing a global reset to MAC\n"); 1074 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1075 1076 ret_val = e1000_get_auto_rd_done_generic(hw); 1077 if (ret_val) { 1078 /* 1079 * When auto config read does not complete, do not 1080 * return with an error. This can happen in situations 1081 * where there is no eeprom and prevents getting link. 1082 */ 1083 DEBUGOUT("Auto Read Done did not complete\n"); 1084 } 1085 1086 /* If EEPROM is not present, run manual init scripts */ 1087 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1088 (void) e1000_reset_init_script_82575(hw); 1089 1090 /* Clear any pending interrupt events. */ 1091 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1092 (void) E1000_READ_REG(hw, E1000_ICR); 1093 1094 /* Install any alternate MAC address into RAR0 */ 1095 ret_val = e1000_check_alt_mac_addr_generic(hw); 1096 1097 return (ret_val); 1098 } 1099 1100 /* 1101 * e1000_init_hw_82575 - Initialize hardware 1102 * @hw: pointer to the HW structure 1103 * 1104 * This inits the hardware readying it for operation. 1105 */ 1106 static s32 1107 e1000_init_hw_82575(struct e1000_hw *hw) 1108 { 1109 struct e1000_mac_info *mac = &hw->mac; 1110 s32 ret_val; 1111 u16 i, rar_count = mac->rar_entry_count; 1112 1113 DEBUGFUNC("e1000_init_hw_82575"); 1114 1115 /* Initialize identification LED */ 1116 ret_val = mac->ops.id_led_init(hw); 1117 if (ret_val) { 1118 DEBUGOUT("Error initializing identification LED\n"); 1119 /* This is not fatal and we should not stop init due to this */ 1120 } 1121 1122 /* Disabling VLAN filtering */ 1123 DEBUGOUT("Initializing the IEEE VLAN\n"); 1124 mac->ops.clear_vfta(hw); 1125 1126 /* Setup the receive address */ 1127 e1000_init_rx_addrs_generic(hw, rar_count); 1128 /* Zero out the Multicast HASH table */ 1129 DEBUGOUT("Zeroing the MTA\n"); 1130 for (i = 0; i < mac->mta_reg_count; i++) 1131 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1132 1133 /* Setup link and flow control */ 1134 ret_val = mac->ops.setup_link(hw); 1135 1136 /* 1137 * Clear all of the statistics registers (clear on read). It is 1138 * important that we do this after we have tried to establish link 1139 * because the symbol error count will increment wildly if there 1140 * is no link. 1141 */ 1142 e1000_clear_hw_cntrs_82575(hw); 1143 1144 return (ret_val); 1145 } 1146 1147 /* 1148 * e1000_setup_copper_link_82575 - Configure copper link settings 1149 * @hw: pointer to the HW structure 1150 * 1151 * Configures the link for auto-neg or forced speed and duplex. Then we check 1152 * for link, once link is established calls to configure collision distance 1153 * and flow control are called. 1154 */ 1155 static s32 1156 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1157 { 1158 u32 ctrl; 1159 s32 ret_val; 1160 bool link; 1161 1162 DEBUGFUNC("e1000_setup_copper_link_82575"); 1163 1164 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1165 ctrl |= E1000_CTRL_SLU; 1166 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1167 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1168 1169 switch (hw->phy.type) { 1170 case e1000_phy_m88: 1171 ret_val = e1000_copper_link_setup_m88(hw); 1172 break; 1173 case e1000_phy_igp_3: 1174 ret_val = e1000_copper_link_setup_igp(hw); 1175 break; 1176 default: 1177 ret_val = -E1000_ERR_PHY; 1178 break; 1179 } 1180 1181 if (ret_val) 1182 goto out; 1183 1184 if (hw->mac.autoneg) { 1185 /* 1186 * Setup autoneg and flow control advertisement 1187 * and perform autonegotiation. 1188 */ 1189 ret_val = e1000_copper_link_autoneg(hw); 1190 if (ret_val) 1191 goto out; 1192 } else { 1193 /* 1194 * PHY will be set to 10H, 10F, 100H or 100F 1195 * depending on user settings. 1196 */ 1197 DEBUGOUT("Forcing Speed and Duplex\n"); 1198 ret_val = hw->phy.ops.force_speed_duplex(hw); 1199 if (ret_val) { 1200 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1201 goto out; 1202 } 1203 } 1204 1205 ret_val = e1000_configure_pcs_link_82575(hw); 1206 if (ret_val) 1207 goto out; 1208 1209 /* 1210 * Check link status. Wait up to 100 microseconds for link to become 1211 * valid. 1212 */ 1213 ret_val = e1000_phy_has_link_generic(hw, 1214 COPPER_LINK_UP_LIMIT, 1215 10, 1216 &link); 1217 if (ret_val) 1218 goto out; 1219 1220 if (link) { 1221 DEBUGOUT("Valid link established!!!\n"); 1222 /* Config the MAC and PHY after link is up */ 1223 e1000_config_collision_dist_generic(hw); 1224 ret_val = e1000_config_fc_after_link_up_generic(hw); 1225 } else { 1226 DEBUGOUT("Unable to establish link!!!\n"); 1227 } 1228 1229 out: 1230 return (ret_val); 1231 } 1232 1233 /* 1234 * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes 1235 * @hw: pointer to the HW structure 1236 * 1237 * Configures speed and duplex for fiber and serdes links. 1238 */ 1239 static s32 1240 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw) 1241 { 1242 u32 reg; 1243 1244 DEBUGFUNC("e1000_setup_fiber_serdes_link_82575"); 1245 1246 /* 1247 * On the 82575, SerDes loopback mode persists until it is 1248 * explicitly turned off or a power cycle is performed. A read to 1249 * the register does not indicate its status. Therefore, we ensure 1250 * loopback mode is disabled during initialization. 1251 */ 1252 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1253 1254 /* Force link up, set 1gb */ 1255 reg = E1000_READ_REG(hw, E1000_CTRL); 1256 reg |= E1000_CTRL_SLU | E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD; 1257 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { 1258 /* set both sw defined pins */ 1259 reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1260 } 1261 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1262 1263 /* Power on phy for 82576 fiber adapters */ 1264 if (hw->mac.type == e1000_82576) { 1265 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1266 reg &= ~E1000_CTRL_EXT_SDP7_DATA; 1267 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1268 } 1269 1270 /* Set switch control to serdes energy detect */ 1271 reg = E1000_READ_REG(hw, E1000_CONNSW); 1272 reg |= E1000_CONNSW_ENRGSRC; 1273 E1000_WRITE_REG(hw, E1000_CONNSW, reg); 1274 1275 /* 1276 * New SerDes mode allows for forcing speed or autonegotiating speed 1277 * at 1gb. Autoneg should be default set by most drivers. This is the 1278 * mode that will be compatible with older link partners and switches. 1279 * However, both are supported by the hardware and some drivers/tools. 1280 */ 1281 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1282 1283 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1284 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1285 1286 if (hw->mac.autoneg) { 1287 /* Set PCS register for autoneg */ 1288 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1289 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1290 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1291 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1292 DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); 1293 } else { 1294 /* Set PCS register for forced speed */ 1295 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1296 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1297 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1298 E1000_PCS_LCTL_FSD | /* Force Speed */ 1299 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1300 DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); 1301 } 1302 1303 if (hw->mac.type == e1000_82576) { 1304 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1305 e1000_force_mac_fc_generic(hw); 1306 } 1307 1308 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1309 1310 return (E1000_SUCCESS); 1311 } 1312 1313 /* 1314 * e1000_valid_led_default_82575 - Verify a valid default LED config 1315 * @hw: pointer to the HW structure 1316 * @data: pointer to the NVM (EEPROM) 1317 * 1318 * Read the EEPROM for the current default LED configuration. If the 1319 * LED configuration is not valid, set to a valid LED configuration. 1320 */ 1321 static s32 1322 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1323 { 1324 s32 ret_val; 1325 1326 DEBUGFUNC("e1000_valid_led_default_82575"); 1327 1328 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1329 if (ret_val) { 1330 DEBUGOUT("NVM Read Error\n"); 1331 goto out; 1332 } 1333 1334 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1335 switch (hw->phy.media_type) { 1336 case e1000_media_type_internal_serdes: 1337 *data = ID_LED_DEFAULT_82575_SERDES; 1338 break; 1339 case e1000_media_type_copper: 1340 default: 1341 *data = ID_LED_DEFAULT; 1342 break; 1343 } 1344 } 1345 out: 1346 return (ret_val); 1347 } 1348 1349 /* 1350 * e1000_configure_pcs_link_82575 - Configure PCS link 1351 * @hw: pointer to the HW structure 1352 * 1353 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1354 * only used on copper connections where the serialized gigabit media 1355 * independent interface (sgmii) is being used. Configures the link 1356 * for auto-negotiation or forces speed/duplex. 1357 */ 1358 static s32 1359 e1000_configure_pcs_link_82575(struct e1000_hw *hw) 1360 { 1361 struct e1000_mac_info *mac = &hw->mac; 1362 u32 reg = 0; 1363 1364 DEBUGFUNC("e1000_configure_pcs_link_82575"); 1365 1366 if (hw->phy.media_type != e1000_media_type_copper || 1367 !(e1000_sgmii_active_82575(hw))) 1368 goto out; 1369 1370 /* For SGMII, we need to issue a PCS autoneg restart */ 1371 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1372 1373 /* AN time out should be disabled for SGMII mode */ 1374 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1375 1376 if (mac->autoneg) { 1377 /* Make sure forced speed and force link are not set */ 1378 reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1379 1380 /* 1381 * The PHY should be setup prior to calling this function. 1382 * All we need to do is restart autoneg and enable autoneg. 1383 */ 1384 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE; 1385 } else { 1386 /* Set PCS register for forced speed */ 1387 1388 /* Turn off bits for full duplex, speed, and autoneg */ 1389 reg &= ~(E1000_PCS_LCTL_FSV_1000 | 1390 E1000_PCS_LCTL_FSV_100 | 1391 E1000_PCS_LCTL_FDV_FULL | 1392 E1000_PCS_LCTL_AN_ENABLE); 1393 1394 /* Check for duplex first */ 1395 if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX) 1396 reg |= E1000_PCS_LCTL_FDV_FULL; 1397 1398 /* Now set speed */ 1399 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) 1400 reg |= E1000_PCS_LCTL_FSV_100; 1401 1402 /* Force speed and force link */ 1403 reg |= E1000_PCS_LCTL_FSD | 1404 E1000_PCS_LCTL_FORCE_LINK | 1405 E1000_PCS_LCTL_FLV_LINK_UP; 1406 1407 DEBUGOUT1("Wrote 0x%08X to PCS_LCTL to configure forced link\n", 1408 reg); 1409 } 1410 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1411 1412 out: 1413 return (E1000_SUCCESS); 1414 } 1415 1416 /* 1417 * e1000_sgmii_active_82575 - Return sgmii state 1418 * @hw: pointer to the HW structure 1419 * 1420 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1421 * which can be enabled for use in the embedded applications. Simply 1422 * return the current state of the sgmii interface. 1423 */ 1424 static bool 1425 e1000_sgmii_active_82575(struct e1000_hw *hw) 1426 { 1427 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1428 return (dev_spec->sgmii_active); 1429 } 1430 1431 /* 1432 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1433 * @hw: pointer to the HW structure 1434 * 1435 * Inits recommended HW defaults after a reset when there is no EEPROM 1436 * detected. This is only for the 82575. 1437 */ 1438 static s32 1439 e1000_reset_init_script_82575(struct e1000_hw *hw) 1440 { 1441 DEBUGFUNC("e1000_reset_init_script_82575"); 1442 1443 if (hw->mac.type == e1000_82575) { 1444 DEBUGOUT("Running reset init script for 82575\n"); 1445 /* SerDes configuration via SERDESCTRL */ 1446 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 1447 0x00, 0x0C); 1448 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 1449 0x01, 0x78); 1450 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 1451 0x1B, 0x23); 1452 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 1453 0x23, 0x15); 1454 1455 /* CCM configuration via CCMCTL register */ 1456 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 1457 0x14, 0x00); 1458 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 1459 0x10, 0x00); 1460 1461 /* PCIe lanes configuration */ 1462 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 1463 0x00, 0xEC); 1464 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 1465 0x61, 0xDF); 1466 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 1467 0x34, 0x05); 1468 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 1469 0x2F, 0x81); 1470 1471 /* PCIe PLL Configuration */ 1472 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 1473 0x02, 0x47); 1474 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 1475 0x14, 0x00); 1476 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 1477 0x10, 0x00); 1478 } 1479 1480 return (E1000_SUCCESS); 1481 } 1482 1483 /* 1484 * e1000_read_mac_addr_82575 - Read device MAC address 1485 * @hw: pointer to the HW structure 1486 */ 1487 static s32 1488 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1489 { 1490 s32 ret_val = E1000_SUCCESS; 1491 1492 DEBUGFUNC("e1000_read_mac_addr_82575"); 1493 1494 /* 1495 * If there's an alternate MAC address place it in RAR0 1496 * so that it will override the Si installed default perm 1497 * address. 1498 */ 1499 ret_val = e1000_check_alt_mac_addr_generic(hw); 1500 if (ret_val) 1501 goto out; 1502 1503 ret_val = e1000_read_mac_addr_generic(hw); 1504 1505 out: 1506 return (ret_val); 1507 } 1508 1509 /* 1510 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1511 * @hw: pointer to the HW structure 1512 * 1513 * In the case of a PHY power down to save power, or to turn off link during a 1514 * driver unload, or wake on lan is not enabled, remove the link. 1515 */ 1516 static void 1517 e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1518 { 1519 struct e1000_phy_info *phy = &hw->phy; 1520 struct e1000_mac_info *mac = &hw->mac; 1521 1522 if (!(phy->ops.check_reset_block)) 1523 return; 1524 1525 /* If the management interface is not enabled, then power down */ 1526 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1527 e1000_power_down_phy_copper(hw); 1528 } 1529 1530 /* 1531 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1532 * @hw: pointer to the HW structure 1533 * 1534 * Clears the hardware counters by reading the counter registers. 1535 */ 1536 static void 1537 e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1538 { 1539 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1540 1541 e1000_clear_hw_cntrs_base_generic(hw); 1542 1543 (void) E1000_READ_REG(hw, E1000_PRC64); 1544 (void) E1000_READ_REG(hw, E1000_PRC127); 1545 (void) E1000_READ_REG(hw, E1000_PRC255); 1546 (void) E1000_READ_REG(hw, E1000_PRC511); 1547 (void) E1000_READ_REG(hw, E1000_PRC1023); 1548 (void) E1000_READ_REG(hw, E1000_PRC1522); 1549 (void) E1000_READ_REG(hw, E1000_PTC64); 1550 (void) E1000_READ_REG(hw, E1000_PTC127); 1551 (void) E1000_READ_REG(hw, E1000_PTC255); 1552 (void) E1000_READ_REG(hw, E1000_PTC511); 1553 (void) E1000_READ_REG(hw, E1000_PTC1023); 1554 (void) E1000_READ_REG(hw, E1000_PTC1522); 1555 1556 (void) E1000_READ_REG(hw, E1000_ALGNERRC); 1557 (void) E1000_READ_REG(hw, E1000_RXERRC); 1558 (void) E1000_READ_REG(hw, E1000_TNCRS); 1559 (void) E1000_READ_REG(hw, E1000_CEXTERR); 1560 (void) E1000_READ_REG(hw, E1000_TSCTC); 1561 (void) E1000_READ_REG(hw, E1000_TSCTFC); 1562 1563 (void) E1000_READ_REG(hw, E1000_MGTPRC); 1564 (void) E1000_READ_REG(hw, E1000_MGTPDC); 1565 (void) E1000_READ_REG(hw, E1000_MGTPTC); 1566 1567 (void) E1000_READ_REG(hw, E1000_IAC); 1568 (void) E1000_READ_REG(hw, E1000_ICRXOC); 1569 1570 (void) E1000_READ_REG(hw, E1000_ICRXPTC); 1571 (void) E1000_READ_REG(hw, E1000_ICRXATC); 1572 (void) E1000_READ_REG(hw, E1000_ICTXPTC); 1573 (void) E1000_READ_REG(hw, E1000_ICTXATC); 1574 (void) E1000_READ_REG(hw, E1000_ICTXQEC); 1575 (void) E1000_READ_REG(hw, E1000_ICTXQMTC); 1576 (void) E1000_READ_REG(hw, E1000_ICRXDMTC); 1577 1578 (void) E1000_READ_REG(hw, E1000_CBTMPC); 1579 (void) E1000_READ_REG(hw, E1000_HTDPMC); 1580 (void) E1000_READ_REG(hw, E1000_CBRMPC); 1581 (void) E1000_READ_REG(hw, E1000_RPTHC); 1582 (void) E1000_READ_REG(hw, E1000_HGPTC); 1583 (void) E1000_READ_REG(hw, E1000_HTCBDPC); 1584 (void) E1000_READ_REG(hw, E1000_HGORCL); 1585 (void) E1000_READ_REG(hw, E1000_HGORCH); 1586 (void) E1000_READ_REG(hw, E1000_HGOTCL); 1587 (void) E1000_READ_REG(hw, E1000_HGOTCH); 1588 (void) E1000_READ_REG(hw, E1000_LENERRS); 1589 1590 /* This register should not be read in copper configurations */ 1591 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1592 (void) E1000_READ_REG(hw, E1000_SCVPC); 1593 } 1594 1595 /* 1596 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1597 * @hw: pointer to the HW structure 1598 * 1599 * After rx enable if managability is enabled then there is likely some 1600 * bad data at the start of the fifo and possibly in the DMA fifo. This 1601 * function clears the fifos and flushes any packets that came in as rx was 1602 * being enabled. 1603 */ 1604 void 1605 e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 1606 { 1607 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1608 int i, ms_wait; 1609 1610 DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 1611 if (hw->mac.type != e1000_82575 || 1612 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1613 return; 1614 1615 /* Disable all RX queues */ 1616 for (i = 0; i < 4; i++) { 1617 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 1618 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 1619 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1620 } 1621 /* Poll all queues to verify they have shut down */ 1622 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1623 msec_delay(1); 1624 rx_enabled = 0; 1625 for (i = 0; i < 4; i++) 1626 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 1627 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1628 break; 1629 } 1630 1631 if (ms_wait == 10) 1632 DEBUGOUT("Queue disable timed out after 10ms\n"); 1633 1634 /* 1635 * Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1636 * incoming packets are rejected. Set enable and wait 2ms so that 1637 * any packet that was coming in as RCTL.EN was set is flushed 1638 */ 1639 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 1640 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1641 1642 rlpml = E1000_READ_REG(hw, E1000_RLPML); 1643 E1000_WRITE_REG(hw, E1000_RLPML, 0); 1644 1645 rctl = E1000_READ_REG(hw, E1000_RCTL); 1646 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1647 temp_rctl |= E1000_RCTL_LPE; 1648 1649 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 1650 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1651 E1000_WRITE_FLUSH(hw); 1652 msec_delay(2); 1653 1654 /* 1655 * Enable RX queues that were previously enabled and restore our 1656 * previous state 1657 */ 1658 for (i = 0; i < 4; i++) 1659 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 1660 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1661 E1000_WRITE_FLUSH(hw); 1662 1663 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 1664 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 1665 1666 /* Flush receive errors generated by workaround */ 1667 (void) E1000_READ_REG(hw, E1000_ROC); 1668 (void) E1000_READ_REG(hw, E1000_RNBC); 1669 (void) E1000_READ_REG(hw, E1000_MPC); 1670 } 1671 1672 /* 1673 * e1000_set_pcie_completion_timeout - set pci-e completion timeout 1674 * @hw: pointer to the HW structure 1675 * 1676 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 1677 * however the hardware default for these parts is 500us to 1ms which is less 1678 * than the 10ms recommended by the pci-e spec. To address this we need to 1679 * increase the value to either 10ms to 200ms for capability version 1 config, 1680 * or 16ms to 55ms for version 2. 1681 */ 1682 static s32 1683 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 1684 { 1685 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 1686 s32 ret_val = E1000_SUCCESS; 1687 u16 pcie_devctl2; 1688 1689 /* only take action if timeout value is defaulted to 0 */ 1690 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 1691 goto out; 1692 1693 /* 1694 * if capababilities version is type 1 we can write the 1695 * timeout of 10ms to 200ms through the GCR register 1696 */ 1697 if (!(gcr & E1000_GCR_CAP_VER2)) { 1698 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 1699 goto out; 1700 } 1701 1702 /* 1703 * for version 2 capabilities we need to write the config space 1704 * directly in order to set the completion timeout value for 1705 * 16ms to 55ms 1706 */ 1707 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1708 &pcie_devctl2); 1709 if (ret_val) 1710 goto out; 1711 1712 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 1713 1714 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1715 &pcie_devctl2); 1716 out: 1717 /* disable completion timeout resend */ 1718 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 1719 1720 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1721 return (ret_val); 1722 } 1723
Indexes created Sun Nov 22 02:52:53 UTC 2009
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