1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _HXGE_RDC_HW_H 27 #define _HXGE_RDC_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define RDC_BASE_ADDR 0X00300000 36 37 #define RDC_PAGE_HANDLE (RDC_BASE_ADDR + 0x8) 38 #define RDC_RX_CFG1 (RDC_BASE_ADDR + 0x20) 39 #define RDC_RX_CFG2 (RDC_BASE_ADDR + 0x28) 40 #define RDC_RBR_CFG_A (RDC_BASE_ADDR + 0x40) 41 #define RDC_RBR_CFG_B (RDC_BASE_ADDR + 0x48) 42 #define RDC_RBR_KICK (RDC_BASE_ADDR + 0x50) 43 #define RDC_RBR_QLEN (RDC_BASE_ADDR + 0x58) 44 #define RDC_RBR_HEAD (RDC_BASE_ADDR + 0x68) 45 #define RDC_RCR_CFG_A (RDC_BASE_ADDR + 0x80) 46 #define RDC_RCR_CFG_B (RDC_BASE_ADDR + 0x88) 47 #define RDC_RCR_QLEN (RDC_BASE_ADDR + 0x90) 48 #define RDC_RCR_TAIL (RDC_BASE_ADDR + 0xA0) 49 #define RDC_RCR_FLUSH (RDC_BASE_ADDR + 0xA8) 50 #define RDC_CLOCK_DIV (RDC_BASE_ADDR + 0xB0) 51 #define RDC_INT_MASK (RDC_BASE_ADDR + 0xB8) 52 #define RDC_STAT (RDC_BASE_ADDR + 0xC0) 53 #define RDC_PKT_COUNT (RDC_BASE_ADDR + 0xD0) 54 #define RDC_DROP_COUNT (RDC_BASE_ADDR + 0xD8) 55 #define RDC_BYTE_COUNT (RDC_BASE_ADDR + 0xE0) 56 #define RDC_PREF_CMD (RDC_BASE_ADDR + 0x100) 57 #define RDC_PREF_DATA (RDC_BASE_ADDR + 0x108) 58 #define RDC_SHADOW_CMD (RDC_BASE_ADDR + 0x110) 59 #define RDC_SHADOW_DATA (RDC_BASE_ADDR + 0x118) 60 #define RDC_SHADOW_PAR_DATA (RDC_BASE_ADDR + 0x120) 61 #define RDC_CTRL_FIFO_CMD (RDC_BASE_ADDR + 0x128) 62 #define RDC_CTRL_FIFO_DATA_LO (RDC_BASE_ADDR + 0x130) 63 #define RDC_CTRL_FIFO_DATA_HI (RDC_BASE_ADDR + 0x138) 64 #define RDC_CTRL_FIFO_DATA_ECC (RDC_BASE_ADDR + 0x140) 65 #define RDC_DATA_FIFO_CMD (RDC_BASE_ADDR + 0x148) 66 #define RDC_DATA_FIFO_DATA_LO (RDC_BASE_ADDR + 0x150) 67 #define RDC_DATA_FIFO_DATA_HI (RDC_BASE_ADDR + 0x158) 68 #define RDC_DATA_FIFO_DATA_ECC (RDC_BASE_ADDR + 0x160) 69 #define RDC_STAT_INT_DBG (RDC_BASE_ADDR + 0x200) 70 #define RDC_PREF_PAR_LOG (RDC_BASE_ADDR + 0x210) 71 #define RDC_SHADOW_PAR_LOG (RDC_BASE_ADDR + 0x218) 72 #define RDC_CTRL_FIFO_ECC_LOG (RDC_BASE_ADDR + 0x220) 73 #define RDC_DATA_FIFO_ECC_LOG (RDC_BASE_ADDR + 0x228) 74 #define RDC_FIFO_ERR_INT_MASK (RDC_BASE_ADDR + 0x230) 75 #define RDC_FIFO_ERR_STAT (RDC_BASE_ADDR + 0x238) 76 #define RDC_FIFO_ERR_INT_DBG (RDC_BASE_ADDR + 0x240) 77 #define RDC_PEU_TXN_LOG (RDC_BASE_ADDR + 0x250) 78 #define RDC_DBG_TRAINING_VEC (RDC_BASE_ADDR + 0x300) 79 #define RDC_DBG_GRP_SEL (RDC_BASE_ADDR + 0x308) 80 81 82 /* 83 * Register: RdcPageHandle 84 * Logical Page Handle 85 * Description: Logical page handle specifying upper bits of 64-bit 86 * PCIE addresses. Fields in this register are part of the dma 87 * configuration and cannot be changed once the dma is enabled. 88 * Fields: 89 * Bits [63:44] of a 64-bit address, used to concatenate to a 90 * 44-bit address when generating 64-bit addresses on the PCIE 91 * bus. 92 */ 93 typedef union { 94 uint64_t value; 95 struct { 96 #if defined(_BIG_ENDIAN) 97 uint32_t rsrvd:32; 98 uint32_t rsrvd_l:12; 99 uint32_t handle:20; 100 #else 101 uint32_t handle:20; 102 uint32_t rsrvd_l:12; 103 uint32_t rsrvd:32; 104 #endif 105 } bits; 106 } rdc_page_handle_t; 107 108 109 /* 110 * Register: RdcRxCfg1 111 * DMA Configuration 1 112 * Description: Configuration parameters for receive DMA block. 113 * Fields in this register are part of the dma configuration and 114 * cannot be changed once the dma is enabled. 115 * The usage of enable, reset, and qst is as follows. Software 116 * should use the following sequence to reset a DMA channel. First, 117 * set DMA.enable to 0, wait for DMA.qst=1 and then, set DMA.reset to 118 * 1. After DMA.reset is cleared by hardware and the DMA.qst is set 119 * to 1, software may then start configuring the DMA channel. The 120 * DMA.enable can be set or cleared while the DMA is in operation. 121 * The state machines of the DMA may not have returned to its initial 122 * states yet after the DMA.enable bit is cleared. This condition is 123 * indicated by the value of the DMA.qst. An example of DMA.enable 124 * being cleared during operation is when a fatal error occurs. 125 * Fields: 126 * Set to 1 to enable the Receive DMA. If set to 0, packets 127 * selecting this DMA will be discarded. On fatal errors, this 128 * bit will be cleared by hardware. This bit cannot be set if sw 129 * has not resolved any pending fatal error condition: i.e. any 130 * RdcStat ldf1 error bits remain set. 131 * Set to 1 to reset the DMA. Hardware will clear this bit after 132 * reset is completed. A reset will bring the sepecific DMA back 133 * to the power on state (including the DMA.en in this register). 134 * When set to 1, it indicates all state associated with the DMA 135 * are in its initial state following either dma reset or 136 * disable. Thus, once this is set to 1, sw could start to 137 * configure the DMA if needed. 138 * Bits [43:32] of the Mailbox address. 139 */ 140 typedef union { 141 uint64_t value; 142 struct { 143 #if defined(_BIG_ENDIAN) 144 uint32_t rsrvd:32; 145 uint32_t enable:1; 146 uint32_t reset:1; 147 uint32_t qst:1; 148 uint32_t rsrvd1:17; 149 uint32_t mbaddr_h:12; 150 #else 151 uint32_t mbaddr_h:12; 152 uint32_t rsrvd1:17; 153 uint32_t qst:1; 154 uint32_t reset:1; 155 uint32_t enable:1; 156 uint32_t rsrvd:32; 157 #endif 158 } bits; 159 } rdc_rx_cfg1_t; 160 161 162 /* 163 * Register: RdcRxCfg2 164 * DMA Configuration 2 165 * Description: Configuration parameters for receive DMA block. 166 * Fields in this register are part of the dma configuration and 167 * cannot be changed once the dma is enabled. 168 * Fields: 169 * Bits [31:6] of the Mailbox address. Bits [5:0] are assumed to 170 * be zero, or 64B aligned. 171 * Multiple of 64Bs, 0 means no offset, b01 means 64B, b10 means 172 * 128B. b11 is invalid, hardware behavior not specified. 173 * Set to 1 to select the entire header of 6B. 174 */ 175 typedef union { 176 uint64_t value; 177 struct { 178 #if defined(_BIG_ENDIAN) 179 uint32_t rsrvd:32; 180 uint32_t mbaddr_l:26; 181 uint32_t rsrvd1:3; 182 uint32_t offset:2; 183 uint32_t full_hdr:1; 184 #else 185 uint32_t full_hdr:1; 186 uint32_t offset:2; 187 uint32_t rsrvd1:3; 188 uint32_t mbaddr_l:26; 189 uint32_t rsrvd:32; 190 #endif 191 } bits; 192 } rdc_rx_cfg2_t; 193 194 195 /* 196 * Register: RdcRbrCfgA 197 * RBR Configuration A 198 * Description: The following registers are used to configure and 199 * manage the RBR. Note that the entire RBR must stay within the 200 * 'page' defined by staddrBase. The behavior of the hardware is 201 * undefined if the last entry is outside of the page (if bits 43:18 202 * of the address of the last entry are different from bits 43:18 of 203 * the base address). Hardware will support wrapping around at the 204 * end of the ring buffer defined by LEN. LEN must be a multiple of 205 * 64. Fields in this register are part of the dma configuration and 206 * cannot be changed once the dma is enabled. 207 * HW does not check for all configuration errors across different 208 * fields. 209 * 210 * Fields: 211 * Bits 15:6 of the maximum number of RBBs in the buffer ring. 212 * Bits 5:0 are hardcoded to zero. The maximum is (2^16 - 64) and 213 * is limited by the staddr value. (len + staddr) should not 214 * exceed (2^16 - 64). 215 * Bits [43:18] of the address for the RBR. This value remains 216 * fixed, and is used as the base address of the ring. All 217 * entries in the ring have this as their upper address bits. 218 * Bits [17:6] of the address of the RBR. staddrBase concatinated 219 * with staddr is the starting address of the RBR. (len + staddr) 220 * should not exceed (2^16 - 64). 221 */ 222 typedef union { 223 uint64_t value; 224 struct { 225 #if defined(_BIG_ENDIAN) 226 uint32_t len:10; 227 uint32_t len_lo:6; 228 uint32_t rsrvd:4; 229 uint32_t staddr_base:12; 230 uint32_t staddr_base_l:14; 231 uint32_t staddr:12; 232 uint32_t rsrvd1:6; 233 #else 234 uint32_t rsrvd1:6; 235 uint32_t staddr:12; 236 uint32_t staddr_base_l:14; 237 uint32_t staddr_base:12; 238 uint32_t rsrvd:4; 239 uint32_t len_lo:6; 240 uint32_t len:10; 241 #endif 242 } bits; 243 } rdc_rbr_cfg_a_t; 244 245 246 /* 247 * Register: RdcRbrCfgB 248 * RBR Configuration B 249 * Description: This register configures the block size, and the 250 * individual packet buffer sizes. The VLD bits of the three block 251 * sizes have to be set to 1 in normal operations. These bits may be 252 * turned off for debug purpose only. Fields in this register are 253 * part of the dma configuration and cannot be changed once the dma 254 * is enabled. 255 * Fields: 256 * Buffer Block Size. b0 - 4K; b1 - 8K. 257 * Set to 1 to indicate SIZE2 is valid, and enable hardware to 258 * allocate buffers of size 2. Always set to 1 in normal 259 * operation. 260 * Size 2 of packet buffer. b0 - 2K; b1 - 4K. 261 * Set to 1 to indicate SIZE1 is valid, and enable hardware to 262 * allocate buffers of size 1. Always set to 1 in normal 263 * operation. 264 * Size 1 of packet buffer. b0 - 1K; b1 - 2K. 265 * Set to 1 to indicate SIZE0 is valid, and enable hardware to 266 * allocate buffers of size 0. Always set to 1 in normal 267 * operation. 268 * Size 0 of packet buffer. b00 - 256; b01 - 512; b10 - 1K; b11 - 269 * reserved. 270 */ 271 typedef union { 272 uint64_t value; 273 struct { 274 #if defined(_BIG_ENDIAN) 275 uint32_t rsrvd:32; 276 uint32_t rsrvd_l:7; 277 uint32_t bksize:1; 278 uint32_t vld2:1; 279 uint32_t rsrvd1:6; 280 uint32_t bufsz2:1; 281 uint32_t vld1:1; 282 uint32_t rsrvd2:6; 283 uint32_t bufsz1:1; 284 uint32_t vld0:1; 285 uint32_t rsrvd3:5; 286 uint32_t bufsz0:2; 287 #else 288 uint32_t bufsz0:2; 289 uint32_t rsrvd3:5; 290 uint32_t vld0:1; 291 uint32_t bufsz1:1; 292 uint32_t rsrvd2:6; 293 uint32_t vld1:1; 294 uint32_t bufsz2:1; 295 uint32_t rsrvd1:6; 296 uint32_t vld2:1; 297 uint32_t bksize:1; 298 uint32_t rsrvd_l:7; 299 uint32_t rsrvd:32; 300 #endif 301 } bits; 302 } rdc_rbr_cfg_b_t; 303 304 305 /* 306 * Register: RdcRbrKick 307 * RBR Kick 308 * Description: Block buffer addresses are added to the ring buffer 309 * by software. When software writes to the Kick register, indicating 310 * the number of descriptors added, hardware will update the internal 311 * state of the corresponding buffer pool. 312 * HW does not check for all configuration errors across different 313 * fields. 314 * 315 * Fields: 316 * Number of Block Buffers added by software. Hardware effect 317 * will be triggered when the register is written to. 318 */ 319 typedef union { 320 uint64_t value; 321 struct { 322 #if defined(_BIG_ENDIAN) 323 uint32_t rsrvd:32; 324 uint32_t rsrvd_l:16; 325 uint32_t bkadd:16; 326 #else 327 uint32_t bkadd:16; 328 uint32_t rsrvd_l:16; 329 uint32_t rsrvd:32; 330 #endif 331 } bits; 332 } rdc_rbr_kick_t; 333 334 335 /* 336 * Register: RdcRbrQlen 337 * RBR Queue Length 338 * Description: The current number of entries in the RBR. 339 * Fields: 340 * Number of block addresses in the ring buffer. 341 */ 342 typedef union { 343 uint64_t value; 344 struct { 345 #if defined(_BIG_ENDIAN) 346 uint32_t rsrvd:32; 347 uint32_t rsrvd_l:16; 348 uint32_t qlen:16; 349 #else 350 uint32_t qlen:16; 351 uint32_t rsrvd_l:16; 352 uint32_t rsrvd:32; 353 #endif 354 } bits; 355 } rdc_rbr_qlen_t; 356 357 358 /* 359 * Register: RdcRbrHead 360 * RBR Head 361 * Description: Lower bits of the RBR head pointer. Software programs 362 * the upper bits, specified in rdcRbrConfigA.staddrBase. 363 * Fields: 364 * Bits [17:2] of the software posted address, 4B aligned. This 365 * pointer is updated by hardware after each block buffer is 366 * consumed. 367 */ 368 typedef union { 369 uint64_t value; 370 struct { 371 #if defined(_BIG_ENDIAN) 372 uint32_t rsrvd:32; 373 uint32_t rsrvd_l:14; 374 uint32_t head:16; 375 uint32_t rsrvd1:2; 376 #else 377 uint32_t rsrvd1:2; 378 uint32_t head:16; 379 uint32_t rsrvd_l:14; 380 uint32_t rsrvd:32; 381 #endif 382 } bits; 383 } rdc_rbr_head_t; 384 385 386 /* 387 * Register: RdcRcrCfgA 388 * RCR Configuration A 389 * Description: The RCR should be within the 'page' defined by the 390 * staddrBase, i.e. staddrBase concatenate with STADDR plus 8 x LEN 391 * should be within the last address of the 'page' defined by 392 * staddrBase. The length must be a multiple of 32. Fields in this 393 * register are part of the dma configuration and cannot be changed 394 * once the dma is enabled. 395 * HW does not check for all configuration errors across different 396 * fields. 397 * 398 * Fields: 399 * Bits 15:5 of the maximum number of 8B entries in RCR. Bits 4:0 400 * are hard-coded to zero. The maximum size is (2^16 - 32) and is 401 * limited by staddr value. (len + staddr) should not exceed 402 * (2^16 - 32). 403 * Bits [43:19] of the Start address for the RCR. 404 * Bits [18:6] of start address for the RCR. (len + staddr) 405 * should not exceed (2^16 - 32). 406 */ 407 typedef union { 408 uint64_t value; 409 struct { 410 #if defined(_BIG_ENDIAN) 411 uint32_t len:11; 412 uint32_t len_lo:5; 413 uint32_t rsrvd:4; 414 uint32_t staddr_base:12; 415 uint32_t staddr_base_l:13; 416 uint32_t staddr:13; 417 uint32_t rsrvd1:6; 418 #else 419 uint32_t rsrvd1:6; 420 uint32_t staddr:13; 421 uint32_t staddr_base_l:13; 422 uint32_t staddr_base:12; 423 uint32_t rsrvd:4; 424 uint32_t len_lo:5; 425 uint32_t len:11; 426 #endif 427 } bits; 428 } rdc_rcr_cfg_a_t; 429 430 431 /* 432 * Register: RdcRcrCfgB 433 * RCR Configuration B 434 * Description: RCR configuration settings. 435 * Fields: 436 * Packet Threshold; when the number of packets enqueued in RCR 437 * is strictly larger than PTHRES, the DMA MAY issue an interrupt 438 * if enabled. 439 * Enable timeout. If set to one, enable the timeout. A timeout 440 * will initiate an update of the software visible states. If 441 * interrupt is armed, in addition to the update, an interrupt to 442 * CPU will be generated, and the interrupt disarmed. 443 * Time out value. The system clock is divided down by the value 444 * programmed in the Receive DMA Clock Divider register. 445 */ 446 typedef union { 447 uint64_t value; 448 struct { 449 #if defined(_BIG_ENDIAN) 450 uint32_t rsrvd:32; 451 uint32_t pthres:16; 452 uint32_t entout:1; 453 uint32_t rsrvd1:9; 454 uint32_t timeout:6; 455 #else 456 uint32_t timeout:6; 457 uint32_t rsrvd1:9; 458 uint32_t entout:1; 459 uint32_t pthres:16; 460 uint32_t rsrvd:32; 461 #endif 462 } bits; 463 } rdc_rcr_cfg_b_t; 464 465 466 /* 467 * Register: RdcRcrQlen 468 * RCR Queue Length 469 * Description: The number of entries in the RCR. 470 * Fields: 471 * Number of packets queued. Initialize to zero after the RCR 472 * Configuration A register is written to. 473 */ 474 typedef union { 475 uint64_t value; 476 struct { 477 #if defined(_BIG_ENDIAN) 478 uint32_t rsrvd:32; 479 uint32_t rsrvd_l:16; 480 uint32_t qlen:16; 481 #else 482 uint32_t qlen:16; 483 uint32_t rsrvd_l:16; 484 uint32_t rsrvd:32; 485 #endif 486 } bits; 487 } rdc_rcr_qlen_t; 488 489 490 /* 491 * Register: RdcRcrTail 492 * RCR Tail 493 * Description: Lower bits of the RCR tail pointer. Software programs 494 * the upper bits, specified in rdcRcrConfigA.staddrBase. 495 * Fields: 496 * Address of the RCR Tail Pointer [18:3] (points to the next 497 * available location.) Initialized after the RCR Configuration A 498 * register is written to. 499 */ 500 typedef union { 501 uint64_t value; 502 struct { 503 #if defined(_BIG_ENDIAN) 504 uint32_t rsrvd:32; 505 uint32_t rsrvd_l:13; 506 uint32_t tail:16; 507 uint32_t rsrvd1:3; 508 #else 509 uint32_t rsrvd1:3; 510 uint32_t tail:16; 511 uint32_t rsrvd_l:13; 512 uint32_t rsrvd:32; 513 #endif 514 } bits; 515 } rdc_rcr_tail_t; 516 517 518 /* 519 * Register: RdcRcrFlush 520 * RCR Flush 521 * Description: This register will force an update to the RCR in 522 * system memory. 523 * Fields: 524 * Set to 1 to force the hardware to store the shadow tail block 525 * to DRAM if the hardware state (queue length and pointers) is 526 * different from the software visible state. Reset to 0 by 527 * hardware when done. 528 */ 529 typedef union { 530 uint64_t value; 531 struct { 532 #if defined(_BIG_ENDIAN) 533 uint32_t rsrvd:32; 534 uint32_t rsrvd_l:31; 535 uint32_t flush:1; 536 #else 537 uint32_t flush:1; 538 uint32_t rsrvd_l:31; 539 uint32_t rsrvd:32; 540 #endif 541 } bits; 542 } rdc_rcr_flush_t; 543 544 545 /* 546 * Register: RdcClockDiv 547 * Receive DMA Clock Divider 548 * Description: The granularity of the DMA timers is determined by 549 * the following counter. This is used to drive the DMA timeout 550 * counters. For a 250MHz system clock, a value of 25000 (decimal) 551 * will yield a granularity of 100 usec. 552 * Fields: 553 * System clock divider, determines the granularity of the DMA 554 * timeout count-down. The hardware count down is count+1. 555 */ 556 typedef union { 557 uint64_t value; 558 struct { 559 #if defined(_BIG_ENDIAN) 560 uint32_t rsrvd:32; 561 uint32_t rsrvd_l:16; 562 uint32_t count:16; 563 #else 564 uint32_t count:16; 565 uint32_t rsrvd_l:16; 566 uint32_t rsrvd:32; 567 #endif 568 } bits; 569 } rdc_clock_div_t; 570 571 572 /* 573 * Register: RdcIntMask 574 * RDC Interrupt Mask 575 * Description: RDC interrupt status register. RCRTHRES and RCRTO 576 * bits are used to keep track of normal DMA operations, while the 577 * remaining bits are primarily used to detect error conditions. 578 * Fields: 579 * Set to 0 to enable flagging when rdc receives a response 580 * completion timeout from peu. Part of LDF 1. 581 * Set to 1 to enable flagging when rdc receives a poisoned 582 * completion or non-zero (unsuccessful) completion status 583 * received from PEU. Part of LDF 1. 584 * Set to 0 to enable flagging when RCR threshold crossed. Part 585 * of LDF 0. 586 * Set to 0 to enable flagging when RCR timeout. Part of LDF 0. 587 * Set to 0 to enable flagging when read from rcr shadow ram 588 * generates a parity error Part of LDF 1. 589 * Set to 0 to enable flagging when read from rbr prefetch ram 590 * generates a parity error Part of LDF 1. 591 * Set to 0 to enable flagging when Receive Block Ring prefetch 592 * is empty (not enough buffer blocks available depending on 593 * incoming pkt size) when hardware tries to queue a packet. 594 * Incoming packets will be discarded. Non-fatal error. Part of 595 * LDF 1. 596 * Set to 0 to enable flagging when packet discard because of RCR 597 * shadow full. 598 * Set to 0 to enable flagging when Receive Completion Ring full 599 * when hardware tries to enqueue the completion status of a 600 * packet. Part of LDF 1. 601 * Set to 0 to enable flagging when RBR empty when hardware 602 * attempts to prefetch. Part of LDF 1. 603 * Set to 0 to enable flagging when Receive Block Ring full when 604 * software tries to post more blocks. Part of LDF 1. 605 */ 606 typedef union { 607 uint64_t value; 608 struct { 609 #if defined(_BIG_ENDIAN) 610 uint32_t rsrvd:10; 611 uint32_t rbr_cpl_to:1; 612 uint32_t peu_resp_err:1; 613 uint32_t rsrvd1:5; 614 uint32_t rcr_thres:1; 615 uint32_t rcr_to:1; 616 uint32_t rcr_shadow_par_err:1; 617 uint32_t rbr_prefetch_par_err:1; 618 uint32_t rsrvd2:2; 619 uint32_t rbr_pre_empty:1; 620 uint32_t rcr_shadow_full:1; 621 uint32_t rsrvd3:2; 622 uint32_t rcr_full:1; 623 uint32_t rbr_empty:1; 624 uint32_t rbr_full:1; 625 uint32_t rsrvd4:2; 626 uint32_t rsrvd5:32; 627 #else 628 uint32_t rsrvd5:32; 629 uint32_t rsrvd4:2; 630 uint32_t rbr_full:1; 631 uint32_t rbr_empty:1; 632 uint32_t rcr_full:1; 633 uint32_t rsrvd3:2; 634 uint32_t rcr_shadow_full:1; 635 uint32_t rbr_pre_empty:1; 636 uint32_t rsrvd2:2; 637 uint32_t rbr_prefetch_par_err:1; 638 uint32_t rcr_shadow_par_err:1; 639 uint32_t rcr_to:1; 640 uint32_t rcr_thres:1; 641 uint32_t rsrvd1:5; 642 uint32_t peu_resp_err:1; 643 uint32_t rbr_cpl_to:1; 644 uint32_t rsrvd:10; 645 #endif 646 } bits; 647 } rdc_int_mask_t; 648 649 650 /* 651 * Register: RdcStat 652 * RDC Control And Status 653 * Description: The DMA channels are controlled using this register. 654 * Fields: 655 * Set to 1 to indicate rdc received a response completion 656 * timeout from peu. Fatal error. Part of LDF 1. 657 * Set to 1 to indicate poisoned completion or non-zero 658 * (unsuccessful) completion status received from PEU. Part of 659 * LDF 1. 660 * Set to 1 to enable mailbox update. Hardware will reset to 0 661 * after one update. Software needs to set to 1 for each update. 662 * Write 0 has no effect. Note that once set by software, only 663 * hardware can reset the value. This bit is also used to keep 664 * track of the exclusivity between threshold triggered or 665 * timeout triggered interrupt. If this bit is not set, there 666 * will be no timer based interrupt, and threshold based 667 * interrupt will not issue a mailbox update. It is recommended 668 * that software should set this bit to one when arming the 669 * device for interrupt. 670 * Set to 1 to indicate RCR threshold crossed. This is a level 671 * event. Part of LDF 0. 672 * Set to 1 to indicate RCR time-outed if MEX bit is set and the 673 * queue length is non-zero when timeout occurs. When software 674 * writes 1 to this bit, RCRTO will be reset to 0. Part of LDF 0. 675 * Set to 1 to indicate read from rcr shadow ram generates a 676 * parity error Writing a 1 to this register also clears the 677 * rdcshadowParLog register Fatal error. Part of LDF 1. 678 * Set to 1 to indicate read from rbr prefetch ram generates 679 * parity error Writing a 1 to this register also clears the 680 * rdcPrefParLog register Fatal error. Part of LDF 1. 681 * Set to 1 to indicate Receive Block Ring prefetch is empty (not 682 * enough buffer blocks available depending on incoming pkt size) 683 * when hardware tries to queue a packet. Incoming packets will 684 * be discarded. Non-fatal error. Part of LDF 1. 685 * Set to 1 to indicate packet discard because of RCR shadow 686 * full. RCR Shadow full cannot be set to 1 in a normal 687 * operation. When set to 1, it indicates a fatal error. Part of 688 * LDF 1. 689 * Set to 1 to indicate Receive Completion Ring full when 690 * hardware tries to enqueue the completion status of a packet. 691 * Incoming packets will be discarded. No buffer consumed. Fatal 692 * error. Part of LDF 1. 693 * Set to 1 to indicate RBR empty when hardware attempts to 694 * prefetch. Part of LDF 1. 695 * Set to 1 to indicate Receive Buffer Ring full when software 696 * writes the kick register with a value greater than the length 697 * of the RBR length. Incoming packets will be discarded. Fatal 698 * error. Part of LDF 1. 699 * Number of buffer pointers read. Used to advance the RCR head 700 * pointer. 701 * Number of packets read; when written to, decrement the QLEN 702 * counter by PKTREAD. QLEN is lower bounded to zero. 703 */ 704 typedef union { 705 uint64_t value; 706 struct { 707 #if defined(_BIG_ENDIAN) 708 uint32_t rsrvd:10; 709 uint32_t rbr_cpl_to:1; 710 uint32_t peu_resp_err:1; 711 uint32_t rsrvd1:4; 712 uint32_t mex:1; 713 uint32_t rcr_thres:1; 714 uint32_t rcr_to:1; 715 uint32_t rcr_shadow_par_err:1; 716 uint32_t rbr_prefetch_par_err:1; 717 uint32_t rsrvd2:2; 718 uint32_t rbr_pre_empty:1; 719 uint32_t rcr_shadow_full:1; 720 uint32_t rsrvd3:2; 721 uint32_t rcr_full:1; 722 uint32_t rbr_empty:1; 723 uint32_t rbr_full:1; 724 uint32_t rsrvd4:2; 725 uint32_t ptrread:16; 726 uint32_t pktread:16; 727 #else 728 uint32_t pktread:16; 729 uint32_t ptrread:16; 730 uint32_t rsrvd4:2; 731 uint32_t rbr_full:1; 732 uint32_t rbr_empty:1; 733 uint32_t rcr_full:1; 734 uint32_t rsrvd3:2; 735 uint32_t rcr_shadow_full:1; 736 uint32_t rbr_pre_empty:1; 737 uint32_t rsrvd2:2; 738 uint32_t rbr_prefetch_par_err:1; 739 uint32_t rcr_shadow_par_err:1; 740 uint32_t rcr_to:1; 741 uint32_t rcr_thres:1; 742 uint32_t mex:1; 743 uint32_t rsrvd1:4; 744 uint32_t peu_resp_err:1; 745 uint32_t rbr_cpl_to:1; 746 uint32_t rsrvd:10; 747 #endif 748 } bits; 749 } rdc_stat_t; 750 751 752 /* 753 * Register: RdcPktCount 754 * Rx DMA Packet Counter 755 * Description: Counts the number of packets received from the Rx 756 * Virtual MAC for this DMA channel. 757 * Fields: 758 * Count of SYN packets received from RVM. This counter 759 * saturates. 760 * Count of packets received from RVM. This counter saturates. 761 */ 762 typedef union { 763 uint64_t value; 764 struct { 765 #if defined(_BIG_ENDIAN) 766 uint32_t syn_pkt_count:32; 767 uint32_t pkt_count:32; 768 #else 769 uint32_t pkt_count:32; 770 uint32_t syn_pkt_count:32; 771 #endif 772 } bits; 773 } rdc_pkt_count_t; 774 775 776 /* 777 * Register: RdcDropCount 778 * Rx DMA Dropped Packet Counters 779 * Description: Counts the number of packets dropped due to different 780 * types of errors. 781 * Fields: 782 * Count of packets dropped because they were longer than the 783 * maximum length. This counter saturates. 784 * Count of packets dropped because there was no block available 785 * in the RBR Prefetch Buffer. This counter saturates. 786 * Count of packets dropped because the RVM marked the packet as 787 * errored. This counter saturates. 788 * Count of packets dropped because there was a framing error 789 * from the RVM. This counter saturates. 790 * Count of packets dropped because the packet did not fit in the 791 * rx ram. This counter saturates. 792 */ 793 typedef union { 794 uint64_t value; 795 struct { 796 #if defined(_BIG_ENDIAN) 797 uint32_t rsrvd:16; 798 uint32_t too_long:8; 799 uint32_t no_rbr_avail:8; 800 uint32_t rvm_error:8; 801 uint32_t frame_error:8; 802 uint32_t rxram_error:8; 803 uint32_t rsrvd1:8; 804 #else 805 uint32_t rsrvd1:8; 806 uint32_t rxram_error:8; 807 uint32_t frame_error:8; 808 uint32_t rvm_error:8; 809 uint32_t no_rbr_avail:8; 810 uint32_t too_long:8; 811 uint32_t rsrvd:16; 812 #endif 813 } bits; 814 } rdc_drop_count_t; 815 816 817 /* 818 * Register: RdcByteCount 819 * Rx DMA Byte Counter 820 * Description: Counts the number of bytes transferred by dma for all 821 * channels. 822 * Fields: 823 * Count of bytes transferred by dma. This counter saturates. 824 */ 825 typedef union { 826 uint64_t value; 827 struct { 828 #if defined(_BIG_ENDIAN) 829 uint32_t rsrvd:32; 830 uint32_t count:32; 831 #else 832 uint32_t count:32; 833 uint32_t rsrvd:32; 834 #endif 835 } bits; 836 } rdc_byte_count_t; 837 838 839 /* 840 * Register: RdcPrefCmd 841 * Rx DMA Prefetch Buffer Command 842 * Description: Allows debug access to the entire prefetch buffer, 843 * along with the rdcPrefData register. Writing the rdcPrefCmd 844 * triggers the access. For writes, software writes the 32 bits of 845 * data to the rdcPrefData register before writing the write command 846 * to this register. For reads, software first writes the the read 847 * command to this register, then reads the 32-bit value from the 848 * rdcPrefData register. The status field should be polled by 849 * software until it goes low, indicating the read or write has 850 * completed. 851 * Fields: 852 * status of indirect access 0=busy 1=done 853 * Command type. 1 indicates a read command, 0 a write command. 854 * enable writing of parity bits 1=enabled, 0=disabled 855 * DMA channel of entry to read or write 856 * Entry in the prefetch buffer to read or write 857 */ 858 typedef union { 859 uint64_t value; 860 struct { 861 #if defined(_BIG_ENDIAN) 862 uint32_t rsrvd:32; 863 uint32_t status:1; 864 uint32_t cmd:1; 865 uint32_t par_en:1; 866 uint32_t rsrvd1:22; 867 uint32_t dmc:2; 868 uint32_t entry:5; 869 #else 870 uint32_t entry:5; 871 uint32_t dmc:2; 872 uint32_t rsrvd1:22; 873 uint32_t par_en:1; 874 uint32_t cmd:1; 875 uint32_t status:1; 876 uint32_t rsrvd:32; 877 #endif 878 } bits; 879 } rdc_pref_cmd_t; 880 881 882 /* 883 * Register: RdcPrefData 884 * Rx DMA Prefetch Buffer Data 885 * Description: See rdcPrefCmd register. 886 * Fields: 887 * For writes, parity bits is written into prefetch buffer. For 888 * reads, parity bits read from the prefetch buffer. 889 * For writes, data which is written into prefetch buffer. For 890 * reads, data read from the prefetch buffer. 891 */ 892 typedef union { 893 uint64_t value; 894 struct { 895 #if defined(_BIG_ENDIAN) 896 uint32_t rsrvd:28; 897 uint32_t par:4; 898 uint32_t data:32; 899 #else 900 uint32_t data:32; 901 uint32_t par:4; 902 uint32_t rsrvd:28; 903 #endif 904 } bits; 905 } rdc_pref_data_t; 906 907 908 /* 909 * Register: RdcShadowCmd 910 * Rx DMA Shadow Tail Command 911 * Description: Allows debug access to the entire shadow tail, along 912 * with the rdcShadowData register. Writing the rdcShadowCmd triggers 913 * the access. For writes, software writes the 64 bits of data to the 914 * rdcShadowData register before writing the write command to this 915 * register. For reads, software first writes the the read command to 916 * this register, then reads the 64-bit value from the rdcShadowData 917 * register. The valid field should be polled by software until it 918 * goes low, indicating the read or write has completed. 919 * Fields: 920 * status of indirect access 0=busy 1=done 921 * Command type. 1 indicates a read command, 0 a write command. 922 * enable writing of parity bits 1=enabled, 0=disabled 923 * DMA channel of entry to read or write 924 * Entry in the shadow tail to read or write 925 */ 926 typedef union { 927 uint64_t value; 928 struct { 929 #if defined(_BIG_ENDIAN) 930 uint32_t rsrvd:32; 931 uint32_t status:1; 932 uint32_t cmd:1; 933 uint32_t par_en:1; 934 uint32_t rsrvd1:23; 935 uint32_t dmc:2; 936 uint32_t entry:4; 937 #else 938 uint32_t entry:4; 939 uint32_t dmc:2; 940 uint32_t rsrvd1:23; 941 uint32_t par_en:1; 942 uint32_t cmd:1; 943 uint32_t status:1; 944 uint32_t rsrvd:32; 945 #endif 946 } bits; 947 } rdc_shadow_cmd_t; 948 949 950 /* 951 * Register: RdcShadowData 952 * Rx DMA Shadow Tail Data 953 * Description: See rdcShadowCmd register. 954 * Fields: 955 * For writes, data which is written into shadow tail. For reads, 956 * data read from the shadow tail. 957 */ 958 typedef union { 959 uint64_t value; 960 struct { 961 #if defined(_BIG_ENDIAN) 962 uint32_t data:32; 963 uint32_t data_l:32; 964 #else 965 uint32_t data_l:32; 966 uint32_t data:32; 967 #endif 968 } bits; 969 } rdc_shadow_data_t; 970 971 972 /* 973 * Register: RdcShadowParData 974 * Rx DMA Shadow Tail Parity Data 975 * Description: See rdcShadowCmd register. 976 * Fields: 977 * For writes, parity data is written into shadow tail. For 978 * reads, parity data read from the shadow tail. 979 */ 980 typedef union { 981 uint64_t value; 982 struct { 983 #if defined(_BIG_ENDIAN) 984 uint32_t rsrvd:32; 985 uint32_t rsrvd1:24; 986 uint32_t parity_data:8; 987 #else 988 uint32_t parity_data:8; 989 uint32_t rsrvd1:24; 990 uint32_t rsrvd:32; 991 #endif 992 } bits; 993 } rdc_shadow_par_data_t; 994 995 996 /* 997 * Register: RdcCtrlFifoCmd 998 * Rx DMA Control Fifo Command 999 * Description: Allows debug access to the entire Rx Ctl FIFO, along 1000 * with the rdcCtrlFifoData register. Writing the rdcCtrlFifoCmd 1001 * triggers the access. For writes, software writes the 128 bits of 1002 * data to the rdcCtrlFifoData registers before writing the write 1003 * command to this register. For reads, software first writes the the 1004 * read command to this register, then reads the 128-bit value from 1005 * the rdcCtrlFifoData registers. The valid field should be polled by 1006 * software until it goes low, indicating the read or write has 1007 * completed. 1008 * Fields: 1009 * status of indirect access 0=busy 1=done 1010 * Command type. 1 indicates a read command, 0 a write command. 1011 * enable writing of ECC bits 1=enabled, 0=disabled 1012 * Entry in the rx control ram to read or write 1013 */ 1014 typedef union { 1015 uint64_t value; 1016 struct { 1017 #if defined(_BIG_ENDIAN) 1018 uint32_t rsrvd:32; 1019 uint32_t status:1; 1020 uint32_t cmd:1; 1021 uint32_t ecc_en:1; 1022 uint32_t rsrvd1:20; 1023 uint32_t entry:9; 1024 #else 1025 uint32_t entry:9; 1026 uint32_t rsrvd1:20; 1027 uint32_t ecc_en:1; 1028 uint32_t cmd:1; 1029 uint32_t status:1; 1030 uint32_t rsrvd:32; 1031 #endif 1032 } bits; 1033 } rdc_ctrl_fifo_cmd_t; 1034 1035 1036 /* 1037 * Register: RdcCtrlFifoDataLo 1038 * Rx DMA Control Fifo Data Lo 1039 * Description: Lower 64 bits read or written to the Rx Ctl FIFO. See 1040 * rdcCtrlFifoCmd register. 1041 * Fields: 1042 * For writes, data which is written into rx control ram. For 1043 * reads, data read from the rx control ram. 1044 */ 1045 typedef union { 1046 uint64_t value; 1047 struct { 1048 #if defined(_BIG_ENDIAN) 1049 uint32_t data:32; 1050 uint32_t data_l:32; 1051 #else 1052 uint32_t data_l:32; 1053 uint32_t data:32; 1054 #endif 1055 } bits; 1056 } rdc_ctrl_fifo_data_lo_t; 1057 1058 1059 /* 1060 * Register: RdcCtrlFifoDataHi 1061 * Rx DMA Control Fifo Data Hi 1062 * Description: Upper 64 bits read or written to the Rx Ctl FIFO. See 1063 * rdcCtrlFifoCmd register. 1064 * Fields: 1065 * For writes, data which is written into rx control ram. For 1066 * reads, data read from the rx control ram. 1067 */ 1068 typedef union { 1069 uint64_t value; 1070 struct { 1071 #if defined(_BIG_ENDIAN) 1072 uint32_t data:32; 1073 uint32_t data_l:32; 1074 #else 1075 uint32_t data_l:32; 1076 uint32_t data:32; 1077 #endif 1078 } bits; 1079 } rdc_ctrl_fifo_data_hi_t; 1080 1081 1082 /* 1083 * Register: RdcCtrlFifoDataEcc 1084 * Rx DMA Control Fifo Data ECC 1085 * Description: 16 bits ECC data read or written to the Rx Ctl FIFO. 1086 * See rdcCtrlFifoCmd register. 1087 * Fields: 1088 * For writes, data which is written into rx control ram. For 1089 * reads, data read from the rx control ram. 1090 * For writes, data which is written into rx control ram. For 1091 * reads, data read from the rx control ram. 1092 */ 1093 typedef union { 1094 uint64_t value; 1095 struct { 1096 #if defined(_BIG_ENDIAN) 1097 uint32_t rsrvd:32; 1098 uint32_t rsrvd1:16; 1099 uint32_t ecc_data_hi:8; 1100 uint32_t ecc_data_lo:8; 1101 #else 1102 uint32_t ecc_data_lo:8; 1103 uint32_t ecc_data_hi:8; 1104 uint32_t rsrvd1:16; 1105 uint32_t rsrvd:32; 1106 #endif 1107 } bits; 1108 } rdc_ctrl_fifo_data_ecc_t; 1109 1110 1111 /* 1112 * Register: RdcDataFifoCmd 1113 * Rx DMA Data Fifo Command 1114 * Description: Allows debug access to the entire Rx Data FIFO, along 1115 * with the rdcDataFifoData register. Writing the rdcCtrlFifoCmd 1116 * triggers the access. For writes, software writes the 128 bits of 1117 * data to the rdcDataFifoData registers before writing the write 1118 * command to this register. For reads, software first writes the the 1119 * read command to this register, then reads the 128-bit value from 1120 * the rdcDataFifoData registers. The valid field should be polled by 1121 * software until it goes low, indicating the read or write has 1122 * completed. 1123 * Fields: 1124 * status of indirect access 0=busy 1=done 1125 * Command type. 1 indicates a read command, 0 a write command. 1126 * enable writing of ECC bits 1=enabled, 0=disabled 1127 * Entry in the rx data ram to read or write 1128 */ 1129 typedef union { 1130 uint64_t value; 1131 struct { 1132 #if defined(_BIG_ENDIAN) 1133 uint32_t rsrvd:32; 1134 uint32_t status:1; 1135 uint32_t cmd:1; 1136 uint32_t ecc_en:1; 1137 uint32_t rsrvd1:18; 1138 uint32_t entry:11; 1139 #else 1140 uint32_t entry:11; 1141 uint32_t rsrvd1:18; 1142 uint32_t ecc_en:1; 1143 uint32_t cmd:1; 1144 uint32_t status:1; 1145 uint32_t rsrvd:32; 1146 #endif 1147 } bits; 1148 } rdc_data_fifo_cmd_t; 1149 1150 1151 /* 1152 * Register: RdcDataFifoDataLo 1153 * Rx DMA Data Fifo Data Lo 1154 * Description: Lower 64 bits read or written to the Rx Data FIFO. 1155 * See rdcDataFifoCmd register. 1156 * Fields: 1157 * For writes, data which is written into rx data ram. For reads, 1158 * data read from the rx data ram. 1159 */ 1160 typedef union { 1161 uint64_t value; 1162 struct { 1163 #if defined(_BIG_ENDIAN) 1164 uint32_t data:32; 1165 uint32_t data_l:32; 1166 #else 1167 uint32_t data_l:32; 1168 uint32_t data:32; 1169 #endif 1170 } bits; 1171 } rdc_data_fifo_data_lo_t; 1172 1173 1174 /* 1175 * Register: RdcDataFifoDataHi 1176 * Rx DMA Data Fifo Data Hi 1177 * Description: Upper 64 bits read or written to the Rx Data FIFO. 1178 * See rdcDataFifoCmd register. 1179 * Fields: 1180 * For writes, data which is written into rx data ram. For reads, 1181 * data read from the rx data ram. 1182 */ 1183 typedef union { 1184 uint64_t value; 1185 struct { 1186 #if defined(_BIG_ENDIAN) 1187 uint32_t data:32; 1188 uint32_t data_l:32; 1189 #else 1190 uint32_t data_l:32; 1191 uint32_t data:32; 1192 #endif 1193 } bits; 1194 } rdc_data_fifo_data_hi_t; 1195 1196 1197 /* 1198 * Register: RdcDataFifoDataEcc 1199 * Rx DMA Data Fifo ECC Data 1200 * Description: 16 bits ECC data read or written to the Rx Data FIFO. 1201 * See rdcDataFifoCmd register. 1202 * Fields: 1203 * For writes, data which is written into rx data ram. For reads, 1204 * data read from the rx data ram. 1205 * For writes, data which is written into rx data ram. For reads, 1206 * data read from the rx data ram. 1207 */ 1208 typedef union { 1209 uint64_t value; 1210 struct { 1211 #if defined(_BIG_ENDIAN) 1212 uint32_t rsrvd:32; 1213 uint32_t rsrvd1:16; 1214 uint32_t ecc_data_hi:8; 1215 uint32_t ecc_data_lo:8; 1216 #else 1217 uint32_t ecc_data_lo:8; 1218 uint32_t ecc_data_hi:8; 1219 uint32_t rsrvd1:16; 1220 uint32_t rsrvd:32; 1221 #endif 1222 } bits; 1223 } rdc_data_fifo_data_ecc_t; 1224 1225 1226 /* 1227 * Register: RdcStatIntDbg 1228 * RDC Debug Control and Status Interrupt 1229 * Description: RDC debug control and status interrupt register. 1230 * Debug RDC control and status register bits to check if interrupt 1231 * is asserted used to detect error conditions. 1232 * Fields: 1233 * Set to 1 to enable interrupt Part of LDF 1. 1234 * Set to 1 to enable interrupt Part of LDF 1. 1235 * Set to 1 to enable interrupt Part of LDF 0. 1236 * Set to 1 to enable interrupt Part of LDF 0. 1237 * Set to 1 to enable interrupt Part of LDF 1. 1238 * Set to 1 to enable interrupt Part of LDF 1. 1239 * Set to 1 to enable interrupt Part of LDF 1. 1240 * Set to 1 to enable interrupt 1241 * Set to 1 to enable interrupt Part of LDF 1. 1242 * Set to 1 to enable interrupt Part of LDF 1. 1243 * Set to 1 to enable interrupt Part of LDF 1. 1244 */ 1245 typedef union { 1246 uint64_t value; 1247 struct { 1248 #if defined(_BIG_ENDIAN) 1249 uint32_t rsrvd:10; 1250 uint32_t rbr_cpl_to:1; 1251 uint32_t peu_resp_err:1; 1252 uint32_t rsrvd1:5; 1253 uint32_t rcr_thres:1; 1254 uint32_t rcr_to:1; 1255 uint32_t rcr_shadow_par_err:1; 1256 uint32_t rbr_prefetch_par_err:1; 1257 uint32_t rsrvd2:2; 1258 uint32_t rbr_pre_empty:1; 1259 uint32_t rcr_shadow_full:1; 1260 uint32_t rsrvd3:2; 1261 uint32_t rcr_full:1; 1262 uint32_t rbr_empty:1; 1263 uint32_t rbr_full:1; 1264 uint32_t rsrvd4:2; 1265 uint32_t rsrvd5:32; 1266 #else 1267 uint32_t rsrvd5:32; 1268 uint32_t rsrvd4:2; 1269 uint32_t rbr_full:1; 1270 uint32_t rbr_empty:1; 1271 uint32_t rcr_full:1; 1272 uint32_t rsrvd3:2; 1273 uint32_t rcr_shadow_full:1; 1274 uint32_t rbr_pre_empty:1; 1275 uint32_t rsrvd2:2; 1276 uint32_t rbr_prefetch_par_err:1; 1277 uint32_t rcr_shadow_par_err:1; 1278 uint32_t rcr_to:1; 1279 uint32_t rcr_thres:1; 1280 uint32_t rsrvd1:5; 1281 uint32_t peu_resp_err:1; 1282 uint32_t rbr_cpl_to:1; 1283 uint32_t rsrvd:10; 1284 #endif 1285 } bits; 1286 } rdc_stat_int_dbg_t; 1287 1288 1289 /* 1290 * Register: RdcPrefParLog 1291 * Rx DMA Prefetch Buffer Parity Log 1292 * Description: RDC DMA Prefetch Buffer parity log register This 1293 * register logs the first parity error that is encountered. Writing 1294 * a 1 to RdcStat::rbrPrefetchParErr clears this register 1295 * Fields: 1296 * Address of parity error 1297 */ 1298 typedef union { 1299 uint64_t value; 1300 struct { 1301 #if defined(_BIG_ENDIAN) 1302 uint32_t rsrvd:32; 1303 uint32_t rsrvd_l:25; 1304 uint32_t address:7; 1305 #else 1306 uint32_t address:7; 1307 uint32_t rsrvd_l:25; 1308 uint32_t rsrvd:32; 1309 #endif 1310 } bits; 1311 } rdc_pref_par_log_t; 1312 1313 1314 /* 1315 * Register: RdcShadowParLog 1316 * Rx DMA Shadow Tail Parity Log 1317 * Description: RDC DMA Shadow Tail parity log register This register 1318 * logs the first parity error that is encountered. Writing a 1 to 1319 * RdcStat::rcrShadowParErr clears this register 1320 * Fields: 1321 * Address of parity error 1322 */ 1323 typedef union { 1324 uint64_t value; 1325 struct { 1326 #if defined(_BIG_ENDIAN) 1327 uint32_t rsrvd:32; 1328 uint32_t rsrvd1:26; 1329 uint32_t address:6; 1330 #else 1331 uint32_t address:6; 1332 uint32_t rsrvd1:26; 1333 uint32_t rsrvd:32; 1334 #endif 1335 } bits; 1336 } rdc_shadow_par_log_t; 1337 1338 1339 /* 1340 * Register: RdcCtrlFifoEccLog 1341 * Rx DMA Control Fifo ECC Log 1342 * Description: RDC DMA Control FIFO ECC log register This register 1343 * logs the first ECC error that is encountered. A double-bit ecc 1344 * error over writes any single-bit ecc error previously logged 1345 * Fields: 1346 * Address of ECC error for upper 64 bits Writing a 1 to 1347 * RdcFifoErrStat::rxCtrlFifoDed[1] or 1348 * RdcFifoErrStat::rxCtrlFifoSec[1] clears this register 1349 * Address of ECC error for lower 64 bits Writing a 1 to 1350 * RdcFifoErrStat::rxCtrlFifoDed[0] or 1351 * RdcFifoErrStat::rxCtrlFifoSec[0] clears this register 1352 * ECC syndrome for upper 64 bits Writing a 1 to 1353 * RdcFifoErrStat::rxCtrlFifoDed[1] or 1354 * RdcFifoErrStat::rxCtrlFifoSec[1] clears this register 1355 * ECC syndrome for lower 64 bits Writing a 1 to 1356 * RdcFifoErrStat::rxCtrlFifoDed[0] or 1357 * RdcFifoErrStat::rxCtrlFifoSec[0] clears this register 1358 */ 1359 typedef union { 1360 uint64_t value; 1361 struct { 1362 #if defined(_BIG_ENDIAN) 1363 uint32_t rsrvd:7; 1364 uint32_t address_hi:9; 1365 uint32_t rsrvd1:7; 1366 uint32_t address_lo:9; 1367 uint32_t rsrvd2:8; 1368 uint32_t syndrome_hi:8; 1369 uint32_t rsrvd3:8; 1370 uint32_t syndrome_lo:8; 1371 #else 1372 uint32_t syndrome_lo:8; 1373 uint32_t rsrvd3:8; 1374 uint32_t syndrome_hi:8; 1375 uint32_t rsrvd2:8; 1376 uint32_t address_lo:9; 1377 uint32_t rsrvd1:7; 1378 uint32_t address_hi:9; 1379 uint32_t rsrvd:7; 1380 #endif 1381 } bits; 1382 } rdc_ctrl_fifo_ecc_log_t; 1383 1384 1385 /* 1386 * Register: RdcDataFifoEccLog 1387 * Rx DMA Data Fifo ECC Log 1388 * Description: RDC DMA data FIFO ECC log register This register logs 1389 * the first ECC error that is encountered. A double-bit ecc error 1390 * over writes any single-bit ecc error previously logged 1391 * Fields: 1392 * Address of ECC error for upper 64 bits Writing a 1 to 1393 * RdcFifoErrStat::rxDataFifoDed[1] or 1394 * RdcFifoErrStat::rxDataFifoSec[1] clears this register 1395 * Address of ECC error for lower 64 bits Writing a 1 to 1396 * RdcFifoErrStat::rxDataFifoDed[0] or 1397 * RdcFifoErrStat::rxDataFifoSec[0] clears this register 1398 * ECC syndrome for upper 64 bits Writing a 1 to 1399 * RdcFifoErrStat::rxDataFifoDed[1] or 1400 * RdcFifoErrStat::rxDataFifoSec[1] clears this register 1401 * ECC syndrome for lower 64 bits Writing a 1 to 1402 * RdcFifoErrStat::rxDataFifoDed[0] or 1403 * RdcFifoErrStat::rxDataFifoSec[0] clears this register 1404 */ 1405 typedef union { 1406 uint64_t value; 1407 struct { 1408 #if defined(_BIG_ENDIAN) 1409 uint32_t rsrvd:5; 1410 uint32_t address_hi:11; 1411 uint32_t rsrvd1:5; 1412 uint32_t address_lo:11; 1413 uint32_t rsrvd2:8; 1414 uint32_t syndrome_hi:8; 1415 uint32_t rsrvd3:8; 1416 uint32_t syndrome_lo:8; 1417 #else 1418 uint32_t syndrome_lo:8; 1419 uint32_t rsrvd3:8; 1420 uint32_t syndrome_hi:8; 1421 uint32_t rsrvd2:8; 1422 uint32_t address_lo:11; 1423 uint32_t rsrvd1:5; 1424 uint32_t address_hi:11; 1425 uint32_t rsrvd:5; 1426 #endif 1427 } bits; 1428 } rdc_data_fifo_ecc_log_t; 1429 1430 1431 /* 1432 * Register: RdcFifoErrIntMask 1433 * FIFO Error Interrupt Mask 1434 * Description: FIFO Error interrupt mask register. Control the 1435 * interrupt assertion of FIFO Errors. see FIFO Error Status register 1436 * for more description 1437 * Fields: 1438 * Set to 0 to enable flagging when rx ctrl ram logs ecc single 1439 * bit error Part of Device Error 0. 1440 * Set to 0 to enable flagging when rx ctrl ram logs ecc double 1441 * bit error Part of Device Error 1. 1442 * Set to 0 to enable flagging when rx data ram logs ecc single 1443 * bit error Part of Device Error 0. 1444 * Set to 0 to enable flagging when rx data ram logs ecc double 1445 * bit error Part of Device Error 1. 1446 */ 1447 typedef union { 1448 uint64_t value; 1449 struct { 1450 #if defined(_BIG_ENDIAN) 1451 uint32_t rsrvd:32; 1452 uint32_t rsrvd1:24; 1453 uint32_t rx_ctrl_fifo_sec:2; 1454 uint32_t rx_ctrl_fifo_ded:2; 1455 uint32_t rx_data_fifo_sec:2; 1456 uint32_t rx_data_fifo_ded:2; 1457 #else 1458 uint32_t rx_data_fifo_ded:2; 1459 uint32_t rx_data_fifo_sec:2; 1460 uint32_t rx_ctrl_fifo_ded:2; 1461 uint32_t rx_ctrl_fifo_sec:2; 1462 uint32_t rsrvd1:24; 1463 uint32_t rsrvd:32; 1464 #endif 1465 } bits; 1466 } rdc_fifo_err_int_mask_t; 1467 1468 1469 /* 1470 * Register: RdcFifoErrStat 1471 * FIFO Error Status 1472 * Description: FIFO Error Status register. Log status of FIFO 1473 * Errors. Rx Data buffer is physically two seperate memory, each of 1474 * the two error bits point to one of the memory. Each entry in the 1475 * rx ctrl point to 2 buffer locations and they are read seperatly. 1476 * The two error bits point to each half of the entry. 1477 * Fields: 1478 * Set to 1 by HW to indicate rx control ram received a ecc 1479 * single bit error Writing a 1 to either bit clears the 1480 * RdcCtrlFifoEccLog register Non-Fatal error. Part of Device 1481 * Error 0 1482 * Set to 1 by HW to indicate rx control ram received a ecc 1483 * double bit error Writing a 1 to either bit clears the 1484 * RdcCtrlFifoEccLog register Fatal error. Part of Device Error 1 1485 * Set to 1 by HW to indicate rx data ram received a ecc single 1486 * bit error Writing a 1 to either bit clears the 1487 * RdcDataFifoEccLog register Non-Fatal error. Part of Device 1488 * Error 0 1489 * Set to 1 by HW to indicate rx data ram received a ecc double 1490 * bit error Writing a 1 to either bit clears the 1491 * RdcDataFifoEccLog register Fatal error. Part of Device Error 1 1492 */ 1493 typedef union { 1494 uint64_t value; 1495 struct { 1496 #if defined(_BIG_ENDIAN) 1497 uint32_t rsrvd:32; 1498 uint32_t rsrvd_l:24; 1499 uint32_t rx_ctrl_fifo_sec:2; 1500 uint32_t rx_ctrl_fifo_ded:2; 1501 uint32_t rx_data_fifo_sec:2; 1502 uint32_t rx_data_fifo_ded:2; 1503 #else 1504 uint32_t rx_data_fifo_ded:2; 1505 uint32_t rx_data_fifo_sec:2; 1506 uint32_t rx_ctrl_fifo_ded:2; 1507 uint32_t rx_ctrl_fifo_sec:2; 1508 uint32_t rsrvd_l:24; 1509 uint32_t rsrvd:32; 1510 #endif 1511 } bits; 1512 } rdc_fifo_err_stat_t; 1513 1514 1515 /* 1516 * Register: RdcFifoErrIntDbg 1517 * FIFO Error Interrupt Debug 1518 * Description: FIFO Error interrupt Debug register. Debug Control 1519 * the interrupt assertion of FIFO Errors. 1520 * Fields: 1521 * Set to 1 to enable interrupt Part of Device Error 0. 1522 * Set to 1 to enable interrupt Part of Device Error 1. 1523 * Set to 1 to enable interrupt Part of Device Error 0. 1524 * Set to 1 to enable interrupt Part of Device Error 1. 1525 */ 1526 typedef union { 1527 uint64_t value; 1528 struct { 1529 #if defined(_BIG_ENDIAN) 1530 uint32_t rsrvd:32; 1531 uint32_t rsrvd1:24; 1532 uint32_t rx_ctrl_fifo_sec:2; 1533 uint32_t rx_ctrl_fifo_ded:2; 1534 uint32_t rx_data_fifo_sec:2; 1535 uint32_t rx_data_fifo_ded:2; 1536 #else 1537 uint32_t rx_data_fifo_ded:2; 1538 uint32_t rx_data_fifo_sec:2; 1539 uint32_t rx_ctrl_fifo_ded:2; 1540 uint32_t rx_ctrl_fifo_sec:2; 1541 uint32_t rsrvd1:24; 1542 uint32_t rsrvd:32; 1543 #endif 1544 } bits; 1545 } rdc_fifo_err_int_dbg_t; 1546 1547 1548 /* 1549 * Register: RdcPeuTxnLog 1550 * PEU Transaction Log 1551 * Description: PEU Transaction Log register. Counts the memory read 1552 * and write requests sent to peu block. For debug only. 1553 * Fields: 1554 * Counts the memory write transactions sent to peu block. This 1555 * counter saturates. This counter increments when vnmDbg is on 1556 * Counts the memory read transactions sent to peu block. This 1557 * counter saturates. This counter increments when vnmDbg is on 1558 */ 1559 typedef union { 1560 uint64_t value; 1561 struct { 1562 #if defined(_BIG_ENDIAN) 1563 uint32_t rsrvd:32; 1564 uint32_t rsrvd1:16; 1565 uint32_t peu_mem_wr_count:8; 1566 uint32_t peu_mem_rd_count:8; 1567 #else 1568 uint32_t peu_mem_rd_count:8; 1569 uint32_t peu_mem_wr_count:8; 1570 uint32_t rsrvd1:16; 1571 uint32_t rsrvd:32; 1572 #endif 1573 } bits; 1574 } rdc_peu_txn_log_t; 1575 1576 1577 /* 1578 * Register: RdcDbgTrainingVec 1579 * Debug Training Vector 1580 * Description: Debug Training Vector register Debug Training Vector 1581 * for the coreClk domain. For the pcieClk domain, the dbgxMsb and 1582 * dbgyMsb values are flipped on the debug bus. 1583 * Fields: 1584 * Blade Number, the value read depends on the blade this block 1585 * resides 1586 * debug training vector the sub-group select value of 0 selects 1587 * this vector 1588 * Blade Number, the value read depends on the blade this block 1589 * resides 1590 * debug training vector the sub-group select value of 0 selects 1591 * this vector 1592 */ 1593 typedef union { 1594 uint64_t value; 1595 struct { 1596 #if defined(_BIG_ENDIAN) 1597 uint32_t rsrvd:32; 1598 uint32_t dbgx_msb:1; 1599 uint32_t dbgx_bld_num:3; 1600 uint32_t dbgx_training_vec:12; 1601 uint32_t dbgy_msb:1; 1602 uint32_t dbgy_bld_num:3; 1603 uint32_t dbgy_training_vec:12; 1604 #else 1605 uint32_t dbgy_training_vec:12; 1606 uint32_t dbgy_bld_num:3; 1607 uint32_t dbgy_msb:1; 1608 uint32_t dbgx_training_vec:12; 1609 uint32_t dbgx_bld_num:3; 1610 uint32_t dbgx_msb:1; 1611 uint32_t rsrvd:32; 1612 #endif 1613 } bits; 1614 } rdc_dbg_training_vec_t; 1615 1616 1617 /* 1618 * Register: RdcDbgGrpSel 1619 * Debug Group Select 1620 * Description: Debug Group Select register. Debug Group Select 1621 * register selects the group of signals brought out on the debug 1622 * port 1623 * Fields: 1624 * high 32b sub-group select 1625 * low 32b sub-group select 1626 */ 1627 typedef union { 1628 uint64_t value; 1629 struct { 1630 #if defined(_BIG_ENDIAN) 1631 uint32_t rsrvd:32; 1632 uint32_t rsrvd_l:16; 1633 uint32_t dbg_h32_sub_sel:8; 1634 uint32_t dbg_l32_sub_sel:8; 1635 #else 1636 uint32_t dbg_l32_sub_sel:8; 1637 uint32_t dbg_h32_sub_sel:8; 1638 uint32_t rsrvd_l:16; 1639 uint32_t rsrvd:32; 1640 #endif 1641 } bits; 1642 } rdc_dbg_grp_sel_t; 1643 1644 1645 #ifdef __cplusplus 1646 } 1647 #endif 1648 1649 #endif /* _HXGE_RDC_HW_H */ 1650
Indexes created Sun Nov 22 02:16:54 UTC 2009
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