1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _HXGE_PFC_HW_H 27 #define _HXGE_PFC_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define PFC_BASE_ADDR 0X0200000 36 37 #define PFC_VLAN_TABLE (PFC_BASE_ADDR + 0x0) 38 #define PFC_VLAN_CTRL (PFC_BASE_ADDR + 0x9000) 39 #define PFC_MAC_ADDR (PFC_BASE_ADDR + 0x10000) 40 #define PFC_MAC_ADDR_MASK (PFC_BASE_ADDR + 0x10080) 41 #define PFC_HASH_TABLE (PFC_BASE_ADDR + 0x10100) 42 #define PFC_L2_CLASS_CONFIG (PFC_BASE_ADDR + 0x20000) 43 #define PFC_L3_CLASS_CONFIG (PFC_BASE_ADDR + 0x20030) 44 #define PFC_TCAM_KEY0 (PFC_BASE_ADDR + 0x20090) 45 #define PFC_TCAM_KEY1 (PFC_BASE_ADDR + 0x20098) 46 #define PFC_TCAM_MASK0 (PFC_BASE_ADDR + 0x200B0) 47 #define PFC_TCAM_MASK1 (PFC_BASE_ADDR + 0x200B8) 48 #define PFC_TCAM_CTRL (PFC_BASE_ADDR + 0x200D0) 49 #define PFC_CONFIG (PFC_BASE_ADDR + 0x20100) 50 #define TCP_CTRL_MASK (PFC_BASE_ADDR + 0x20108) 51 #define SRC_HASH_VAL (PFC_BASE_ADDR + 0x20110) 52 #define PFC_INT_STATUS (PFC_BASE_ADDR + 0x30000) 53 #define PFC_DBG_INT_STATUS (PFC_BASE_ADDR + 0x30008) 54 #define PFC_INT_MASK (PFC_BASE_ADDR + 0x30100) 55 #define PFC_DROP_LOG (PFC_BASE_ADDR + 0x30200) 56 #define PFC_DROP_LOG_MASK (PFC_BASE_ADDR + 0x30208) 57 #define PFC_VLAN_PAR_ERR_LOG (PFC_BASE_ADDR + 0x30210) 58 #define PFC_TCAM_PAR_ERR_LOG (PFC_BASE_ADDR + 0x30218) 59 #define PFC_BAD_CS_COUNTER (PFC_BASE_ADDR + 0x30220) 60 #define PFC_DROP_COUNTER (PFC_BASE_ADDR + 0x30228) 61 #define PFC_AUTO_INIT (PFC_BASE_ADDR + 0x30300) 62 63 64 /* 65 * Register: PfcVlanTable 66 * VLAN Table Registers 67 * Description: VLAN membership table. CPU programs in the VLANs that 68 * it wants to belong to. A blade may be a member of multiple VLANs. 69 * Bits [31:0] of the first entry corresponds to vlan members [31:0], 70 * bits [31:0] of the second entry corresponds to vlan members 71 * [63:32] and so on. 72 * Fields: 73 * Odd parities of member[31:24], member[23:16], member[17:8], 74 * member[7:0]. These parity bits are ignored when parEn in the 75 * VLAN Control register is set to '0'. 76 * Set to 1 to indicate that blade is a member of the VLAN IDs 77 * (32 to 0) * entry number 78 */ 79 typedef union { 80 uint64_t value; 81 struct { 82 #if defined(_BIG_ENDIAN) 83 uint32_t rsrvd:28; 84 uint32_t parity:4; 85 uint32_t member:32; 86 #else 87 uint32_t member:32; 88 uint32_t parity:4; 89 uint32_t rsrvd:28; 90 #endif 91 } bits; 92 } pfc_vlan_table_t; 93 94 95 /* 96 * Register: PfcVlanCtrl 97 * VLAN Control Register 98 * Description: VLAN control register. Controls VLAN table properties 99 * and implicit VLAN properties for non-VLAN tagged packets. 100 * Fields: 101 * VLAN table parity debug write enable. When set to 1, software 102 * writes the parity bits together with the data during a VLAN 103 * table write. Otherwise, hardware automatically generates the 104 * parity bits from the data. 105 * Set to 1 to indicate the implicit VLAN ID is valid for use in 106 * non-VLAN tagged packets filtering 107 * Implicit VLAN ID for non-VLAN tagged packets 108 */ 109 typedef union { 110 uint64_t value; 111 struct { 112 #if defined(_BIG_ENDIAN) 113 uint32_t rsrvd:32; 114 uint32_t rsrvd_l:18; 115 uint32_t par_en:1; 116 uint32_t valid:1; 117 uint32_t id:12; 118 #else 119 uint32_t id:12; 120 uint32_t valid:1; 121 uint32_t par_en:1; 122 uint32_t rsrvd_l:18; 123 uint32_t rsrvd:32; 124 #endif 125 } bits; 126 } pfc_vlan_ctrl_t; 127 128 129 /* 130 * Register: PfcMacAddr 131 * MAC Address 132 * Description: MAC Address - Contains a station's 48 bit MAC 133 * address. The first register corresponds to MAC address 0, the 134 * second register corresponds to MAC address 1 and so on. For a MAC 135 * address of format aa-bb-cc-dd-ee-ff, addr[47:0] corresponds to 136 * "aabbccddeeff". When used in conjunction with the MAC address 137 * filter mask registers, these registers can be used to construct 138 * either a unicast or multicast address. An address is considered 139 * matched if (DA & ~mask) == (MAC address & ~mask) 140 * Fields: 141 * 48 bits of stations's MAC address 142 */ 143 typedef union { 144 uint64_t value; 145 struct { 146 #if defined(_BIG_ENDIAN) 147 uint32_t rsrvd:16; 148 uint32_t addr:16; 149 uint32_t addr_l:32; 150 #else 151 uint32_t addr_l:32; 152 uint32_t addr:16; 153 uint32_t rsrvd:16; 154 #endif 155 } bits; 156 } pfc_mac_addr_t; 157 158 159 /* 160 * Register: PfcMacAddrMask 161 * MAC Address Filter 162 * Description: MAC Address Filter Mask - Contains the station's 48 163 * bit MAC address filter mask. The first register corresponds to MAC 164 * address 0 filter mask, the second register corresponds to MAC 165 * address 1 filter mask and so on. These filter masks cover MAC 166 * address bits 47:0 in the same order as the address registers 167 * Fields: 168 * 48 bits of stations's MAC address filter mask 169 */ 170 typedef union { 171 uint64_t value; 172 struct { 173 #if defined(_BIG_ENDIAN) 174 uint32_t rsrvd:16; 175 uint32_t mask:16; 176 uint32_t mask_l:32; 177 #else 178 uint32_t mask_l:32; 179 uint32_t mask:16; 180 uint32_t rsrvd:16; 181 #endif 182 } bits; 183 } pfc_mac_addr_mask_t; 184 185 186 /* 187 * Register: PfcHashTable 188 * MAC Multicast Hash Filter 189 * Description: MAC multicast hash table filter. The multicast 190 * destination address is used to perform Ethernet CRC-32 hashing 191 * with seed value 0xffffFfff. Bits 47:40 of the hash result are used 192 * to index one bit of this multicast hash table. If the bit is '1', 193 * the multicast hash matches. 194 * Fields: 195 * 16 bits of 256 bit hash table. First entry contains bits 196 * [15:0], last entry contains bits [255:240] 197 */ 198 typedef union { 199 uint64_t value; 200 struct { 201 #if defined(_BIG_ENDIAN) 202 uint32_t rsrvd:32; 203 uint32_t rsrvd_l:16; 204 uint32_t hash_val:16; 205 #else 206 uint32_t hash_val:16; 207 uint32_t rsrvd_l:16; 208 uint32_t rsrvd:32; 209 #endif 210 } bits; 211 } pfc_hash_table_t; 212 213 214 /* 215 * Register: PfcL2ClassConfig 216 * L2 Class Configuration 217 * Description: Programmable EtherType for class codes 2 and 3. The 218 * first register is class 2, and the second class 3 219 * Fields: 220 * Set to 1 to indicate that the entry is valid for use in 221 * classification 222 * EtherType value 223 */ 224 typedef union { 225 uint64_t value; 226 struct { 227 #if defined(_BIG_ENDIAN) 228 uint32_t rsrvd:32; 229 uint32_t rsrvd_l:15; 230 uint32_t valid:1; 231 uint32_t etype:16; 232 #else 233 uint32_t etype:16; 234 uint32_t valid:1; 235 uint32_t rsrvd_l:15; 236 uint32_t rsrvd:32; 237 #endif 238 } bits; 239 } pfc_l2_class_config_t; 240 241 242 /* 243 * Register: PfcL3ClassConfig 244 * L3 Class Configuration 245 * Description: Configuration for class codes 0x8-0xF. PFC can be set 246 * to discard certain classes of traffic, or to not initiate a TCAM 247 * match for that class 248 * Fields: 249 * Set to 1 to discard all packets of this class code 250 * Set to 1 to indicate that packets of this class should be sent 251 * to the TCAM for perfect match 252 */ 253 typedef union { 254 uint64_t value; 255 struct { 256 #if defined(_BIG_ENDIAN) 257 uint32_t rsrvd:32; 258 uint32_t rsrvd_l:28; 259 uint32_t discard:1; 260 uint32_t tsel:1; 261 uint32_t rsrvd1:2; 262 #else 263 uint32_t rsrvd1:2; 264 uint32_t tsel:1; 265 uint32_t discard:1; 266 uint32_t rsrvd_l:28; 267 uint32_t rsrvd:32; 268 #endif 269 } bits; 270 } pfc_l3_class_config_t; 271 272 273 /* 274 * Register: PfcTcamKey0 275 * TCAM Key 0 276 * Description: TCAM key value. Holds bit 63:0 of the TCAM key 277 * Fields: 278 * bits 63:0 of tcam key 279 */ 280 typedef union { 281 uint64_t value; 282 struct { 283 #if defined(_BIG_ENDIAN) 284 uint32_t key:32; 285 uint32_t key_l:32; 286 #else 287 uint32_t key_l:32; 288 uint32_t key:32; 289 #endif 290 } bits; 291 } pfc_tcam_key0_t; 292 293 294 /* 295 * Register: PfcTcamKey1 296 * TCAM Key 1 297 * Description: TCAM key value. Holds bit 99:64 of the TCAM key 298 * Fields: 299 * bits 99:64 of tcam key 300 */ 301 typedef union { 302 uint64_t value; 303 struct { 304 #if defined(_BIG_ENDIAN) 305 uint32_t rsrvd:28; 306 uint32_t key:4; 307 uint32_t key_l:32; 308 #else 309 uint32_t key_l:32; 310 uint32_t key:4; 311 uint32_t rsrvd:28; 312 #endif 313 } bits; 314 } pfc_tcam_key1_t; 315 316 317 /* 318 * Register: PfcTcamMask0 319 * TCAM Mask 0 320 * Description: TCAM mask value. Holds bit 63:0 of the TCAM mask 321 * Fields: 322 * bits 63:0 of tcam mask 323 */ 324 typedef union { 325 uint64_t value; 326 struct { 327 #if defined(_BIG_ENDIAN) 328 uint32_t mask:32; 329 uint32_t mask_l:32; 330 #else 331 uint32_t mask_l:32; 332 uint32_t mask:32; 333 #endif 334 } bits; 335 } pfc_tcam_mask0_t; 336 337 338 /* 339 * Register: PfcTcamMask1 340 * TCAM Mask 1 341 * Description: TCAM mask value. Holds bit 99:64 of the TCAM mask 342 * Fields: 343 * bits 99:64 of tcam mask 344 */ 345 typedef union { 346 uint64_t value; 347 struct { 348 #if defined(_BIG_ENDIAN) 349 uint32_t rsrvd:28; 350 uint32_t mask:4; 351 uint32_t mask_l:32; 352 #else 353 uint32_t mask_l:32; 354 uint32_t mask:4; 355 uint32_t rsrvd:28; 356 #endif 357 } bits; 358 } pfc_tcam_mask1_t; 359 360 361 /* 362 * Register: PfcTcamCtrl 363 * TCAM Control 364 * Description: TCAM and TCAM lookup memory access control register. 365 * Controls how TCAM and result lookup table are accessed by blade 366 * CPU. For a TCAM write, the data in the TCAM key and mask registers 367 * will be written to the TCAM. A compare will initiate a TCAM match 368 * with the data stored in the TCAM key register. The match bit is 369 * toggled, and the matching address is reported in the addr field. 370 * For an access to the TCAM result lookup memory, the TCAM 0 key 371 * register is used for the read/write data. 372 * Fields: 373 * TCAM lookup table debug parity bit write enable. When a '1' is 374 * written, software writes the parity bit together with the data 375 * during a TCAM result lookup write. Otherwise, hardware 376 * automatically generates the parity bit from the data. 377 * 3'b000 = TCAM write 3'b001 = reserved 3'b010 = TCAM compare 378 * 3'b011 = reserved 3'b100 = TCAM result lookup write 3'b101 = 379 * TCAM result lookup read 3'b110 = reserved 3'b111 = reserved 380 * Status of read/write/compare operation. When a zero is 381 * written, hardware initiates access. Hardware writes a '1' to 382 * the bit when it completes 383 * Set to 1 if there is a TCAM match for compare command. Zero 384 * otherwise 385 * Address location for access of TCAM or RAM (valid values 386 * 0-42). For a compare, the location of the match is written 387 * here by hardware. 388 */ 389 typedef union { 390 uint64_t value; 391 struct { 392 #if defined(_BIG_ENDIAN) 393 uint32_t rsrvd:32; 394 uint32_t rsrvd_l:13; 395 uint32_t par_en:1; 396 uint32_t cmd:3; 397 uint32_t status:1; 398 uint32_t match:1; 399 uint32_t rsrvd1:5; 400 uint32_t addr:8; 401 #else 402 uint32_t addr:8; 403 uint32_t rsrvd1:5; 404 uint32_t match:1; 405 uint32_t status:1; 406 uint32_t cmd:3; 407 uint32_t par_en:1; 408 uint32_t rsrvd_l:13; 409 uint32_t rsrvd:32; 410 #endif 411 } bits; 412 } pfc_tcam_ctrl_t; 413 414 415 /* 416 * Register: PfcConfig 417 * PFC General Configuration 418 * Description: PFC configuration options that are under the control 419 * of a blade CPU 420 * Fields: 421 * MAC address enable mask. Each bit corresponds to one MAC 422 * adress (lsb = addr0). With 16 MAC addresses, only the lower 16 423 * bits are valid. 424 * default DMA channel number 425 * force TCP/UDP checksum result to always match 426 * Enable for TCP/UDP checksum. If not enabled, the result will 427 * never match. 428 * Enable TCAM matching. If TCAM matching is not enabled, traffic 429 * will be sent to the default DMA channel. 430 * Enable L2 Multicast hash 431 */ 432 typedef union { 433 uint64_t value; 434 struct { 435 #if defined(_BIG_ENDIAN) 436 uint32_t rsrvd:24; 437 uint32_t mac_addr_en:8; 438 uint32_t mac_addr_en_l:24; 439 uint32_t default_dma:4; 440 uint32_t force_cs_en:1; 441 uint32_t tcp_cs_en:1; 442 uint32_t tcam_en:1; 443 uint32_t l2_hash_en:1; 444 #else 445 uint32_t l2_hash_en:1; 446 uint32_t tcam_en:1; 447 uint32_t tcp_cs_en:1; 448 uint32_t force_cs_en:1; 449 uint32_t default_dma:4; 450 uint32_t mac_addr_en_l:24; 451 uint32_t mac_addr_en:8; 452 uint32_t rsrvd:24; 453 #endif 454 } bits; 455 } pfc_config_t; 456 457 458 /* 459 * Register: TcpCtrlMask 460 * TCP control bits mask 461 * Description: Mask of TCP control bits to forward onto downstream 462 * blocks The TCP packet's control bits are masked, and then bitwise 463 * OR'd to produce a signal to the Rx DMA. Normally, all bits are 464 * masked off except the TCP SYN bit. The Rx DMA uses this bitwise OR 465 * for statistics. When discard = 1, the packet will be dropped if 466 * the bitwise OR = 1. 467 * Fields: 468 * Drop the packet if bitwise OR of the TCP control bits masked 469 * on = 1 470 * TCP end of data flag 471 * TCP SYN flag 472 * TCP reset flag 473 * TCP push flag 474 * TCP ack flag 475 * TCP urgent flag 476 */ 477 typedef union { 478 uint64_t value; 479 struct { 480 #if defined(_BIG_ENDIAN) 481 uint32_t rsrvd:32; 482 uint32_t rsrvd_l:25; 483 uint32_t discard:1; 484 uint32_t fin:1; 485 uint32_t syn:1; 486 uint32_t rst:1; 487 uint32_t psh:1; 488 uint32_t ack:1; 489 uint32_t urg:1; 490 #else 491 uint32_t urg:1; 492 uint32_t ack:1; 493 uint32_t psh:1; 494 uint32_t rst:1; 495 uint32_t syn:1; 496 uint32_t fin:1; 497 uint32_t discard:1; 498 uint32_t rsrvd_l:25; 499 uint32_t rsrvd:32; 500 #endif 501 } bits; 502 } tcp_ctrl_mask_t; 503 504 505 /* 506 * Register: SrcHashVal 507 * Source hash Seed Value 508 * Hash CRC seed value 509 */ 510 typedef union { 511 uint64_t value; 512 struct { 513 #if defined(_BIG_ENDIAN) 514 uint32_t rsrvd:32; 515 uint32_t seed:32; 516 #else 517 uint32_t seed:32; 518 uint32_t rsrvd:32; 519 #endif 520 } bits; 521 } src_hash_val_t; 522 523 524 /* 525 * Register: PfcIntStatus 526 * PFC Interrupt Status 527 * Description: PFC interrupt status register 528 * Fields: 529 * triggered when packet drop log captured a drop. Part of LDF 0. 530 * Write 1 to clear. 531 * TCAM result lookup table parity error. Part of LDF 0. Write 1 532 * to clear. 533 * VLAN table parity error. Part of LDF 0. Write 1 to clear. 534 */ 535 typedef union { 536 uint64_t value; 537 struct { 538 #if defined(_BIG_ENDIAN) 539 uint32_t rsrvd:32; 540 uint32_t rsrvd_l:29; 541 uint32_t pkt_drop:1; 542 uint32_t tcam_parity_err:1; 543 uint32_t vlan_parity_err:1; 544 #else 545 uint32_t vlan_parity_err:1; 546 uint32_t tcam_parity_err:1; 547 uint32_t pkt_drop:1; 548 uint32_t rsrvd_l:29; 549 uint32_t rsrvd:32; 550 #endif 551 } bits; 552 } pfc_int_status_t; 553 554 555 /* 556 * Register: PfcDbgIntStatus 557 * PFC Debug Interrupt Status 558 * Description: PFC debug interrupt status mirror register. This 559 * debug register triggers the same interrupts as those in the PFC 560 * Interrupt Status register. Interrupts in this mirror register are 561 * subject to the filtering of the PFC Interrupt Mask register. 562 * Fields: 563 * Packet drop. Part of LDF 0. 564 * TCAM result lookup table parity error. Part of LDF 0. 565 * VLAN table parity error. Part of LDF 0. 566 */ 567 typedef union { 568 uint64_t value; 569 struct { 570 #if defined(_BIG_ENDIAN) 571 uint32_t rsrvd:32; 572 uint32_t rsrvd_l:29; 573 uint32_t pkt_drop:1; 574 uint32_t tcam_parity_err:1; 575 uint32_t vlan_parity_err:1; 576 #else 577 uint32_t vlan_parity_err:1; 578 uint32_t tcam_parity_err:1; 579 uint32_t pkt_drop:1; 580 uint32_t rsrvd_l:29; 581 uint32_t rsrvd:32; 582 #endif 583 } bits; 584 } pfc_dbg_int_status_t; 585 586 587 /* 588 * Register: PfcIntMask 589 * PFC Interrupt Mask 590 * Description: PFC interrupt status mask register 591 * Fields: 592 * mask for pktDrop capture; 593 * TCAM result lookup table parity error mask; 594 * VLAN table parity error mask; 595 */ 596 typedef union { 597 uint64_t value; 598 struct { 599 #if defined(_BIG_ENDIAN) 600 uint32_t rsrvd:32; 601 uint32_t rsrvd_l:29; 602 uint32_t pkt_drop_mask:1; 603 uint32_t tcam_parity_err_mask:1; 604 uint32_t vlan_parity_err_mask:1; 605 #else 606 uint32_t vlan_parity_err_mask:1; 607 uint32_t tcam_parity_err_mask:1; 608 uint32_t pkt_drop_mask:1; 609 uint32_t rsrvd_l:29; 610 uint32_t rsrvd:32; 611 #endif 612 } bits; 613 } pfc_int_mask_t; 614 615 616 /* 617 * Register: PfcDropLog 618 * Packet Drop Log 619 * Description: Packet drop log. Log for capturing packet drops. Log 620 * is re-armed when associated interrupt bit is cleared. 621 * Fields: 622 * drop because bitwise OR of the tcp control bits masked on = 1 623 * drop because L2 address did not match 624 * drop because class code indicated drop 625 * drop because TCAM result indicated drop 626 * drop because blade was not a member of VLAN 627 */ 628 typedef union { 629 uint64_t value; 630 struct { 631 #if defined(_BIG_ENDIAN) 632 uint32_t rsrvd:32; 633 uint32_t rsrvd_l:27; 634 uint32_t tcp_ctrl_drop:1; 635 uint32_t l2_addr_drop:1; 636 uint32_t class_code_drop:1; 637 uint32_t tcam_drop:1; 638 uint32_t vlan_drop:1; 639 #else 640 uint32_t vlan_drop:1; 641 uint32_t tcam_drop:1; 642 uint32_t class_code_drop:1; 643 uint32_t l2_addr_drop:1; 644 uint32_t tcp_ctrl_drop:1; 645 uint32_t rsrvd_l:27; 646 uint32_t rsrvd:32; 647 #endif 648 } bits; 649 } pfc_drop_log_t; 650 651 652 /* 653 * Register: PfcDropLogMask 654 * Packet Drop Log Mask 655 * Description: Mask for logging packet drop. If the drop type is 656 * masked off, it will not trigger the drop log to capture the packet 657 * drop 658 * Fields: 659 * mask drop because bitwise OR of the tcp control bits masked on 660 * = 1 661 * mask drop because L2 address did not match 662 * mask drop because class code indicated 663 * mask drop because TCAM result indicated drop 664 * mask drop because blade was not a member of VLAN 665 */ 666 typedef union { 667 uint64_t value; 668 struct { 669 #if defined(_BIG_ENDIAN) 670 uint32_t rsrvd:32; 671 uint32_t rsrvd_l:27; 672 uint32_t tcp_ctrl_drop_mask:1; 673 uint32_t l2_addr_drop_mask:1; 674 uint32_t class_code_drop_mask:1; 675 uint32_t tcam_drop_mask:1; 676 uint32_t vlan_drop_mask:1; 677 #else 678 uint32_t vlan_drop_mask:1; 679 uint32_t tcam_drop_mask:1; 680 uint32_t class_code_drop_mask:1; 681 uint32_t l2_addr_drop_mask:1; 682 uint32_t tcp_ctrl_drop_mask:1; 683 uint32_t rsrvd_l:27; 684 uint32_t rsrvd:32; 685 #endif 686 } bits; 687 } pfc_drop_log_mask_t; 688 689 690 /* 691 * Register: PfcVlanParErrLog 692 * VLAN Parity Error Log 693 * Description: Log of parity errors in VLAN table. 694 * Fields: 695 * address of parity error. Log is cleared when corresponding 696 * interrupt bit is cleared by writing '1'. 697 */ 698 typedef union { 699 uint64_t value; 700 struct { 701 #if defined(_BIG_ENDIAN) 702 uint32_t rsrvd:32; 703 uint32_t rsrvd_l:20; 704 uint32_t addr:12; 705 #else 706 uint32_t addr:12; 707 uint32_t rsrvd_l:20; 708 uint32_t rsrvd:32; 709 #endif 710 } bits; 711 } pfc_vlan_par_err_log_t; 712 713 714 /* 715 * Register: PfcTcamParErrLog 716 * TCAM Parity Error Log 717 * Description: Log of parity errors in TCAM result lookup table. 718 * Fields: 719 * address of parity error. Log is cleared when corresponding 720 * interrupt bit is cleared by writing '1'. 721 */ 722 typedef union { 723 uint64_t value; 724 struct { 725 #if defined(_BIG_ENDIAN) 726 uint32_t rsrvd:32; 727 uint32_t rsrvd_l:24; 728 uint32_t addr:8; 729 #else 730 uint32_t addr:8; 731 uint32_t rsrvd_l:24; 732 uint32_t rsrvd:32; 733 #endif 734 } bits; 735 } pfc_tcam_par_err_log_t; 736 737 738 /* 739 * Register: PfcBadCsCounter 740 * PFC Bad Checksum Counter 741 * Description: Count number of bad TCP/UDP checksum. Only counted if 742 * L2 adddress matched 743 * Fields: 744 * count of number of bad TCP/UDP checksums received. Clear on 745 * read 746 */ 747 typedef union { 748 uint64_t value; 749 struct { 750 #if defined(_BIG_ENDIAN) 751 uint32_t rsrvd:32; 752 uint32_t bad_cs_count:32; 753 #else 754 uint32_t bad_cs_count:32; 755 uint32_t rsrvd:32; 756 #endif 757 } bits; 758 } pfc_bad_cs_counter_t; 759 760 761 /* 762 * Register: PfcDropCounter 763 * PFC Drop Counter 764 * Description: Count number of packets dropped due to VLAN 765 * membership, class code, TCP control bits, or TCAM results Only 766 * counted if L2 address matched. 767 * Fields: 768 * Count of number of packets dropped due to VLAN, TCAM results. 769 * Clear on read 770 */ 771 typedef union { 772 uint64_t value; 773 struct { 774 #if defined(_BIG_ENDIAN) 775 uint32_t rsrvd:32; 776 uint32_t drop_count:32; 777 #else 778 uint32_t drop_count:32; 779 uint32_t rsrvd:32; 780 #endif 781 } bits; 782 } pfc_drop_counter_t; 783 784 785 /* 786 * Register: PfcAutoInit 787 * PFC Auto Init 788 * Description: PFC Auto Initialization. Writing to this register 789 * triggers the auto initialization of the blade's TCAM entries with 790 * 100 bits of '0' for both key and mask. TCAM lookup is disabled 791 * during auto initialization. 792 * Fields: 793 * TCAM auto initialization status. 0=busy, 1=done. 794 */ 795 typedef union { 796 uint64_t value; 797 struct { 798 #if defined(_BIG_ENDIAN) 799 uint32_t rsrvd:32; 800 uint32_t rsrvd_l:31; 801 uint32_t auto_init_status:1; 802 #else 803 uint32_t auto_init_status:1; 804 uint32_t rsrvd_l:31; 805 uint32_t rsrvd:32; 806 #endif 807 } bits; 808 } pfc_auto_init_t; 809 810 811 #ifdef __cplusplus 812 } 813 #endif 814 815 #endif /* _HXGE_PFC_HW_H */ 816
Indexes created Sun Nov 22 02:16:54 UTC 2009
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