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      1 /*
      2  * CDDL HEADER START
      3  *
      4  * The contents of this file are subject to the terms of the
      5  * Common Development and Distribution License (the "License").
      6  * You may not use this file except in compliance with the License.
      7  *
      8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
      9  * or http://www.opensolaris.org/os/licensing.
     10  * See the License for the specific language governing permissions
     11  * and limitations under the License.
     12  *
     13  * When distributing Covered Code, include this CDDL HEADER in each
     14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
     15  * If applicable, add the following below this CDDL HEADER, with the
     16  * fields enclosed by brackets "[]" replaced with your own identifying
     17  * information: Portions Copyright [yyyy] [name of copyright owner]
     18  *
     19  * CDDL HEADER END
     20  */
     21 /*
     22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
     23  * Use is subject to license terms.
     24  */
     25 
     26 #ifndef _HPI_RXDMA_H
     27 #define	_HPI_RXDMA_H
     28 
     29 #ifdef	__cplusplus
     30 extern "C" {
     31 #endif
     32 
     33 #include <hpi.h>
     34 #include <hxge_defs.h>
     35 #include <hxge_pfc.h>
     36 #include <hxge_pfc_hw.h>
     37 #include <hxge_rdc_hw.h>
     38 
     39 #define	RXDMA_CFIG2_MBADDR_L_SHIFT	6	/* bit 31:6 */
     40 #define	RXDMA_CFIG2_MBADDR_L_MASK	0x00000000ffffffc0ULL
     41 
     42 #define	RBR_CFIG_A_STDADDR_MASK		0x000000000003ffc0ULL
     43 #define	RBR_CFIG_A_STDADDR_BASE_MASK    0x00000ffffffc0000ULL
     44 
     45 #define	RCRCFIG_A_STADDR_SHIFT		6	/* bit 18:6 */
     46 #define	RCRCFIG_A_STADDR_MASK		0x000000000007FFC0ULL
     47 #define	RCRCFIG_A_STADDR_BASE_SHIF	19	/* bit 43:19 */
     48 #define	RCRCFIG_A_STADDR_BASE_MASK	0x00000FFFFFF80000ULL
     49 #define	RCRCFIG_A_LEN_SHIF		48	/* bit 63:48 */
     50 #define	RCRCFIG_A_LEN_MASK		0xFFFF000000000000ULL
     51 
     52 #define	RCR_FLSH_SHIFT			0	/* RW, bit 0:0 */
     53 #define	RCR_FLSH_SET			0x0000000000000001ULL
     54 #define	RCR_FLSH_MASK			0x0000000000000001ULL
     55 
     56 #define	RBR_CFIG_A_LEN_SHIFT		48	/* bits 63:48 */
     57 #define	RBR_CFIG_A_LEN_MASK		0xFFFF000000000000ULL
     58 
     59 /*
     60  * Buffer block descriptor
     61  */
     62 typedef struct _rx_desc_t {
     63 	uint32_t	block_addr;
     64 } rx_desc_t, *p_rx_desc_t;
     65 
     66 typedef enum _bsize {
     67 	SIZE_0B = 0x0,
     68 	SIZE_64B,
     69 	SIZE_128B,
     70 	SIZE_192B,
     71 	SIZE_256B,
     72 	SIZE_512B,
     73 	SIZE_1KB,
     74 	SIZE_2KB,
     75 	SIZE_4KB,
     76 	SIZE_8KB,
     77 	SIZE_16KB,
     78 	SIZE_32KB
     79 } bsize_t;
     80 
     81 typedef struct _rdc_desc_cfg_t {
     82 	uint8_t mbox_enable;		/* Enable full (18b) header */
     83 	uint8_t full_hdr;		/* Enable full (18b) header */
     84 	uint8_t offset;			/* 64 byte offsets */
     85 	uint8_t valid2;			/* size 2 is valid */
     86 	bsize_t size2;			/* Size 2 length */
     87 	uint8_t valid1;			/* size 1 is valid */
     88 	bsize_t size1;			/* Size 1 length */
     89 	uint8_t valid0;			/* size 0 is valid */
     90 	bsize_t size0;			/* Size 1 length */
     91 	bsize_t page_size;		/* Page or buffer Size */
     92 	uint8_t	rcr_timeout_enable;
     93 	uint8_t	rcr_timeout;
     94 	uint16_t rcr_threshold;
     95 	uint16_t rcr_len;		/* RBR Descriptor size (entries) */
     96 	uint16_t rbr_len;		/* RBR Descriptor size (entries) */
     97 	uint64_t mbox_addr;		/* Mailbox Address */
     98 	uint64_t rcr_addr;		/* RCR Address */
     99 	uint64_t rbr_addr;		/* RBB Address */
    100 } rdc_desc_cfg_t;
    101 
    102 
    103 /*
    104  * Register offset (0x800 bytes for each channel) for receive ring registers.
    105  */
    106 #define	HXGE_RXDMA_OFFSET(x, v, channel) (x + \
    107 		(!v ? DMC_OFFSET(channel) : \
    108 		    RDMC_PIOVADDR_OFFSET(channel)))
    109 
    110 #define	RXDMA_REG_READ64(handle, reg, channel, data_p) {\
    111 	HXGE_REG_RD64(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
    112 		channel)), (data_p))\
    113 }
    114 
    115 #define	RXDMA_REG_READ32(handle, reg, channel, data_p) \
    116 	HXGE_REG_RD32(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
    117 		channel)), (data_p))
    118 
    119 #define	RXDMA_REG_WRITE64(handle, reg, channel, data) {\
    120 	HXGE_REG_WR64(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
    121 		channel)), (data))\
    122 }
    123 
    124 /*
    125  * RX HPI error codes
    126  */
    127 #define	RXDMA_ER_ST			(RXDMA_BLK_ID << HPI_BLOCK_ID_SHIFT)
    128 #define	RXDMA_ID_SHIFT(n)		(n << HPI_PORT_CHAN_SHIFT)
    129 
    130 #define	HPI_RXDMA_ERROR			RXDMA_ER_ST
    131 
    132 #define	HPI_RXDMA_SW_PARAM_ERROR	(HPI_RXDMA_ERROR | 0x40)
    133 #define	HPI_RXDMA_HW_ERROR		(HPI_RXDMA_ERROR | 0x80)
    134 
    135 #define	HPI_RXDMA_RDC_INVALID		(HPI_RXDMA_ERROR | CHANNEL_INVALID)
    136 #define	HPI_RXDMA_RESET_ERR		(HPI_RXDMA_HW_ERROR | RESET_FAILED)
    137 #define	HPI_RXDMA_BUFSZIE_INVALID	(HPI_RXDMA_SW_PARAM_ERROR | 0x0000b)
    138 #define	HPI_RXDMA_RBRSZIE_INVALID	(HPI_RXDMA_SW_PARAM_ERROR | 0x0000c)
    139 #define	HPI_RXDMA_RCRSZIE_INVALID	(HPI_RXDMA_SW_PARAM_ERROR | 0x0000d)
    140 
    141 #define	HPI_RXDMA_CHANNEL_INVALID(n)	(RXDMA_ID_SHIFT(n) |	\
    142 					HPI_RXDMA_ERROR | CHANNEL_INVALID)
    143 #define	HPI_RXDMA_OPCODE_INVALID(n)	(RXDMA_ID_SHIFT(n) |	\
    144 					HPI_RXDMA_ERROR | OPCODE_INVALID)
    145 
    146 #define	HPI_RXDMA_ERROR_ENCODE(err, rdc)	\
    147 	(RXDMA_ID_SHIFT(rdc) | RXDMA_ER_ST | err)
    148 
    149 #define	RXDMA_CHANNEL_VALID(rdc) \
    150 	((rdc < HXGE_MAX_RDCS))
    151 
    152 #define	RXDMA_BUFF_OFFSET_VALID(offset) \
    153 	((offset == SW_OFFSET_NO_OFFSET) || \
    154 	    (offset == SW_OFFSET_64) || \
    155 	    (offset == SW_OFFSET_128))
    156 
    157 #define	RXDMA_RCR_TO_VALID(tov) ((tov) && (tov < 64))
    158 #define	RXDMA_RCR_THRESH_VALID(thresh) ((thresh <= 0x8000))
    159 
    160 #define	hpi_rxdma_rdc_rcr_flush(handle, rdc) \
    161 	RXDMA_REG_WRITE64(handle, RDC_RCR_FLUSH, rdc, \
    162 		    (RCR_FLSH_SET << RCR_FLSH_SHIFT))
    163 #define	hpi_rxdma_rdc_rbr_kick(handle, rdc, num_buffers) \
    164 	RXDMA_REG_WRITE64(handle, RDC_RBR_KICK, rdc, num_buffers)
    165 
    166 hpi_status_t hpi_rxdma_cfg_rdc_wait_for_qst(hpi_handle_t handle, uint8_t rdc);
    167 hpi_status_t hpi_rxdma_cfg_rdc_ring(hpi_handle_t handle, uint8_t rdc,
    168     rdc_desc_cfg_t *rdc_desc_params);
    169 hpi_status_t hpi_rxdma_cfg_clock_div_set(hpi_handle_t handle, uint16_t count);
    170 hpi_status_t hpi_rxdma_cfg_logical_page_handle(hpi_handle_t handle, uint8_t rdc,
    171     uint64_t pg_handle);
    172 
    173 hpi_status_t hpi_rxdma_rdc_rbr_stat_get(hpi_handle_t handle, uint8_t rdc,
    174     rdc_rbr_qlen_t *rbr_stat);
    175 hpi_status_t hpi_rxdma_cfg_rdc_reset(hpi_handle_t handle, uint8_t rdc);
    176 hpi_status_t hpi_rxdma_cfg_rdc_enable(hpi_handle_t handle, uint8_t rdc);
    177 hpi_status_t hpi_rxdma_cfg_rdc_disable(hpi_handle_t handle, uint8_t rdc);
    178 hpi_status_t hpi_rxdma_cfg_rdc_rcr_timeout(hpi_handle_t handle, uint8_t rdc,
    179     uint8_t rcr_timeout);
    180 
    181 hpi_status_t hpi_rxdma_cfg_rdc_rcr_threshold(hpi_handle_t handle, uint8_t rdc,
    182     uint16_t rcr_threshold);
    183 hpi_status_t hpi_rxdma_rdc_rcr_qlen_get(hpi_handle_t handle,
    184     uint8_t rdc,  uint16_t *qlen);
    185 
    186 hpi_status_t hpi_rxdma_ring_perr_stat_get(hpi_handle_t handle,
    187     rdc_pref_par_log_t *pre_log, rdc_pref_par_log_t *sha_log);
    188 
    189 hpi_status_t hpi_rxdma_control_status(hpi_handle_t handle, io_op_t op_mode,
    190     uint8_t channel, rdc_stat_t *cs_p);
    191 hpi_status_t hpi_rxdma_event_mask(hpi_handle_t handle, io_op_t op_mode,
    192     uint8_t channel, rdc_int_mask_t *mask_p);
    193 hpi_status_t hpi_rxdma_channel_rbr_empty_clear(hpi_handle_t handle,
    194     uint8_t channel);
    195 
    196 #ifdef	__cplusplus
    197 }
    198 #endif
    199 
    200 #endif	/* _HPI_RXDMA_H */
    201