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      1 /*
      2  * This file is provided under a CDDLv1 license.  When using or
      3  * redistributing this file, you may do so under this license.
      4  * In redistributing this file this license must be included
      5  * and no other modification of this header file is permitted.
      6  *
      7  * CDDL LICENSE SUMMARY
      8  *
      9  * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
     10  *
     11  * The contents of this file are subject to the terms of Version
     12  * 1.0 of the Common Development and Distribution License (the "License").
     13  *
     14  * You should have received a copy of the License with this software.
     15  * You can obtain a copy of the License at
     16  *	http://www.opensolaris.org/os/licensing.
     17  * See the License for the specific language governing permissions
     18  * and limitations under the License.
     19  */
     20 
     21 /*
     22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
     23  * Use is subject to license terms of the CDDLv1.
     24  */
     25 
     26 /*
     27  * IntelVersion: 1.74 v3-1-10-1_2009-9-18_Release14-6
     28  */
     29 #ifndef _E1000_PHY_H_
     30 #define	_E1000_PHY_H_
     31 
     32 #ifdef __cplusplus
     33 extern "C" {
     34 #endif
     35 
     36 void e1000_init_phy_ops_generic(struct e1000_hw *hw);
     37 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
     38 void e1000_null_phy_generic(struct e1000_hw *hw);
     39 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active);
     40 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
     41 s32 e1000_check_downshift_generic(struct e1000_hw *hw);
     42 s32 e1000_check_polarity_m88(struct e1000_hw *hw);
     43 s32 e1000_check_polarity_igp(struct e1000_hw *hw);
     44 s32 e1000_check_polarity_ife(struct e1000_hw *hw);
     45 s32 e1000_check_reset_block_generic(struct e1000_hw *hw);
     46 s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
     47 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw);
     48 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw);
     49 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
     50 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
     51 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
     52 s32 e1000_get_cable_length_m88(struct e1000_hw *hw);
     53 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw);
     54 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw);
     55 s32 e1000_get_phy_id(struct e1000_hw *hw);
     56 s32 e1000_get_phy_info_igp(struct e1000_hw *hw);
     57 s32 e1000_get_phy_info_m88(struct e1000_hw *hw);
     58 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw);
     59 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
     60 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw);
     61 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
     62 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
     63 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
     64 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
     65 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
     66 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
     67 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
     68 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
     69 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw);
     70 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw);
     71 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
     72 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
     73 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
     74 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
     75 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
     76 s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
     77 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
     78     u32 usec_interval, bool *success);
     79 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
     80 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
     81 s32 e1000_determine_phy_address(struct e1000_hw *hw);
     82 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
     83 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
     84 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
     85 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
     86 void e1000_power_up_phy_copper(struct e1000_hw *hw);
     87 void e1000_power_down_phy_copper(struct e1000_hw *hw);
     88 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
     89 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
     90 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
     91 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
     92 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
     93 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
     94 s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow);
     95 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
     96 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
     97 s32 e1000_check_polarity_82577(struct e1000_hw *hw);
     98 s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
     99 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
    100 s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
    101 
    102 #define	E1000_MAX_PHY_ADDR		4
    103 
    104 /* IGP01E1000 Specific Registers */
    105 #define	IGP01E1000_PHY_PORT_CONFIG	0x10 /* Port Config */
    106 #define	IGP01E1000_PHY_PORT_STATUS	0x11 /* Status */
    107 #define	IGP01E1000_PHY_PORT_CTRL	0x12 /* Control */
    108 #define	IGP01E1000_PHY_LINK_HEALTH	0x13 /* PHY Link Health */
    109 #define	IGP01E1000_GMII_FIFO		0x14 /* GMII FIFO */
    110 #define	IGP01E1000_PHY_CHANNEL_QUALITY	0x15 /* PHY Channel Quality */
    111 #define	IGP02E1000_PHY_POWER_MGMT	0x19 /* Power Management */
    112 #define	IGP01E1000_PHY_PAGE_SELECT	0x1F /* Page Select */
    113 #define	BM_PHY_PAGE_SELECT		22   /* Page Select for BM */
    114 #define	IGP_PAGE_SHIFT			5
    115 #define	PHY_REG_MASK			0x1F
    116 
    117 /* BM/HV Specific Registers */
    118 #define	BM_PORT_CTRL_PAGE		769
    119 #define	BM_PCIE_PAGE			770
    120 #define	BM_WUC_PAGE			800
    121 #define	BM_WUC_ADDRESS_OPCODE		0x11
    122 #define	BM_WUC_DATA_OPCODE		0x12
    123 #define	BM_WUC_ENABLE_PAGE		BM_PORT_CTRL_PAGE
    124 #define	BM_WUC_ENABLE_REG		17
    125 #define	BM_WUC_ENABLE_BIT		(1 << 2)
    126 #define	BM_WUC_HOST_WU_BIT		(1 << 4)
    127 
    128 #define	PHY_UPPER_SHIFT			21
    129 #define	BM_PHY_REG(page, reg) \
    130 	(((reg) & MAX_PHY_REG_ADDRESS) |\
    131 	(((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
    132 	(((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
    133 #define	BM_PHY_REG_PAGE(offset) \
    134 	((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
    135 #define	BM_PHY_REG_NUM(offset) \
    136 	((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
    137 	(((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
    138 	~MAX_PHY_REG_ADDRESS)))
    139 
    140 #define	HV_INTC_FC_PAGE_START		768
    141 #define	I82578_ADDR_REG			29
    142 #define	I82577_ADDR_REG			16
    143 #define	I82577_CFG_REG			22
    144 #define	I82577_CFG_ASSERT_CRS_ON_TX	(1 << 15)
    145 #define	I82577_CFG_ENABLE_DOWNSHIFT	(3 << 10) /* auto downshift 100/10 */
    146 #define	I82577_CTRL_REG			23
    147 #define	I82577_CTRL_DOWNSHIFT_MASK	(7 << 10)
    148 
    149 /* 82577 specific PHY registers */
    150 #define	I82577_PHY_CTRL_2		18
    151 #define	I82577_PHY_LBK_CTRL		19
    152 #define	I82577_PHY_STATUS_2		26
    153 #define	I82577_PHY_DIAG_STATUS		31
    154 
    155 /* I82577 PHY Status 2 */
    156 #define	I82577_PHY_STATUS2_REV_POLARITY		0x0400
    157 #define	I82577_PHY_STATUS2_MDIX			0x0800
    158 #define	I82577_PHY_STATUS2_SPEED_MASK		0x0300
    159 #define	I82577_PHY_STATUS2_SPEED_1000MBPS	0x0200
    160 #define	I82577_PHY_STATUS2_SPEED_100MBPS	0x0100
    161 
    162 /* I82577 PHY Control 2 */
    163 #define	I82577_PHY_CTRL2_AUTO_MDIX		0x0400
    164 #define	I82577_PHY_CTRL2_FORCE_MDI_MDIX		0x0200
    165 
    166 /* I82577 PHY Diagnostics Status */
    167 #define	I82577_DSTATUS_CABLE_LENGTH		0x03FC
    168 #define	I82577_DSTATUS_CABLE_LENGTH_SHIFT	2
    169 
    170 /* BM PHY Copper Specific Control 1 */
    171 #define	BM_CS_CTRL1			16
    172 #define	BM_CS_CTRL1_ENERGY_DETECT	0x0300	/* Enable Energy Detect */
    173 
    174 /* BM PHY Copper Specific Status */
    175 #define	BM_CS_STATUS			17
    176 #define	BM_CS_STATUS_ENERGY_DETECT	0x0010	/* Energy Detect Status */
    177 #define	BM_CS_STATUS_LINK_UP		0x0400
    178 #define	BM_CS_STATUS_RESOLVED		0x0800
    179 #define	BM_CS_STATUS_SPEED_MASK		0xC000
    180 #define	BM_CS_STATUS_SPEED_1000		0x8000
    181 
    182 /* 82577 Mobile Phy Status Register */
    183 #define	HV_M_STATUS			26
    184 #define	HV_M_STATUS_AUTONEG_COMPLETE	0x1000
    185 #define	HV_M_STATUS_SPEED_MASK		0x0300
    186 #define	HV_M_STATUS_SPEED_1000		0x0200
    187 #define	HV_M_STATUS_LINK_UP		0x0040
    188 
    189 #define	IGP01E1000_PHY_PCS_INIT_REG	0x00B4
    190 #define	IGP01E1000_PHY_POLARITY_MASK	0x0078
    191 
    192 #define	IGP01E1000_PSCR_AUTO_MDIX	0x1000
    193 #define	IGP01E1000_PSCR_FORCE_MDI_MDIX	0x2000	/* 0=MDI, 1=MDIX */
    194 
    195 #define	IGP01E1000_PSCFR_SMART_SPEED	0x0080
    196 
    197 /* Enable flexible speed on link-up */
    198 #define	IGP01E1000_GMII_FLEX_SPD	0x0010
    199 #define	IGP01E1000_GMII_SPD		0x0020	/* Enable SPD */
    200 
    201 #define	IGP02E1000_PM_SPD		0x0001	/* Smart Power Down */
    202 #define	IGP02E1000_PM_D0_LPLU		0x0002	/* For D0a states */
    203 #define	IGP02E1000_PM_D3_LPLU		0x0004	/* For all other states */
    204 
    205 #define	IGP01E1000_PLHR_SS_DOWNGRADE	0x8000
    206 
    207 #define	IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
    208 #define	IGP01E1000_PSSR_MDIX		0x0800
    209 #define	IGP01E1000_PSSR_SPEED_MASK	0xC000
    210 #define	IGP01E1000_PSSR_SPEED_1000MBPS	0xC000
    211 
    212 #define	IGP02E1000_PHY_CHANNEL_NUM	4
    213 #define	IGP02E1000_PHY_AGC_A		0x11B1
    214 #define	IGP02E1000_PHY_AGC_B		0x12B1
    215 #define	IGP02E1000_PHY_AGC_C		0x14B1
    216 #define	IGP02E1000_PHY_AGC_D		0x18B1
    217 
    218 #define	IGP02E1000_AGC_LENGTH_SHIFT	9 /* Course - 15:13, Fine - 12:9 */
    219 #define	IGP02E1000_AGC_LENGTH_MASK	0x7F
    220 #define	IGP02E1000_AGC_RANGE		15
    221 
    222 #define	IGP03E1000_PHY_MISC_CTRL	0x1B
    223 #define	IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */
    224 
    225 #define	E1000_CABLE_LENGTH_UNDEFINED	0xFF
    226 
    227 #define	E1000_KMRNCTRLSTA_OFFSET	0x001F0000
    228 #define	E1000_KMRNCTRLSTA_OFFSET_SHIFT	16
    229 #define	E1000_KMRNCTRLSTA_REN		0x00200000
    230 #define	E1000_KMRNCTRLSTA_DIAG_OFFSET	0x3	/* Kumeran Diagnostic */
    231 #define	E1000_KMRNCTRLSTA_TIMEOUTS	0x4	/* Kumeran Timeouts */
    232 #define	E1000_KMRNCTRLSTA_INBAND_PARAM	0x9	/* Kumeran InBand Parameters */
    233 #define	E1000_KMRNCTRLSTA_DIAG_NELPBK	0x1000	/* Nearend Loopback mode */
    234 #define	E1000_KMRNCTRLSTA_K1_CONFIG	0x7
    235 #define	E1000_KMRNCTRLSTA_K1_ENABLE	0x0002
    236 
    237 #define	IFE_PHY_EXTENDED_STATUS_CONTROL	0x10
    238 #define	IFE_PHY_SPECIAL_CONTROL		0x11 /* 100BaseTx PHY Special Control */
    239 #define	IFE_PHY_SPECIAL_CONTROL_LED	0x1B /* PHY Special and LED Control */
    240 #define	IFE_PHY_MDIX_CONTROL		0x1C /* MDI/MDI-X Control */
    241 
    242 /* IFE PHY Extended Status Control */
    243 #define	IFE_PESC_POLARITY_REVERSED	0x0100
    244 
    245 /* IFE PHY Special Control */
    246 #define	IFE_PSC_AUTO_POLARITY_DISABLE	0x0010
    247 #define	IFE_PSC_FORCE_POLARITY		0x0020
    248 #define	IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
    249 
    250 /* IFE PHY Special Control and LED Control */
    251 #define	IFE_PSCL_PROBE_MODE		0x0020
    252 #define	IFE_PSCL_PROBE_LEDS_OFF		0x0006 /* Force LEDs 0 and 2 off */
    253 #define	IFE_PSCL_PROBE_LEDS_ON		0x0007 /* Force LEDs 0 and 2 on */
    254 
    255 /* IFE PHY MDIX Control */
    256 #define	IFE_PMC_MDIX_STATUS	0x0020 /* 1=MDI-X, 0=MDI */
    257 #define	IFE_PMC_FORCE_MDIX	0x0040 /* 1=force MDI-X, 0=force MDI */
    258 #define	IFE_PMC_AUTO_MDIX	0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
    259 
    260 #ifdef __cplusplus
    261 }
    262 #endif
    263 
    264 #endif	/* _E1000_PHY_H_ */
    265