1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 /* 27 * IntelVersion: 1.108 v3-1-10-1_2009-9-18_Release14-6 28 */ 29 #include "e1000_api.h" 30 31 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 32 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 33 34 /* 35 * e1000_init_mac_ops_generic - Initialize MAC function pointers 36 * @hw: pointer to the HW structure 37 * 38 * Setups up the function pointers to no-op functions 39 */ 40 void 41 e1000_init_mac_ops_generic(struct e1000_hw *hw) 42 { 43 struct e1000_mac_info *mac = &hw->mac; 44 DEBUGFUNC("e1000_init_mac_ops_generic"); 45 46 /* General Setup */ 47 mac->ops.init_params = e1000_null_ops_generic; 48 mac->ops.init_hw = e1000_null_ops_generic; 49 mac->ops.reset_hw = e1000_null_ops_generic; 50 mac->ops.setup_physical_interface = e1000_null_ops_generic; 51 mac->ops.get_bus_info = e1000_null_ops_generic; 52 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 53 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 54 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 55 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 56 /* LED */ 57 mac->ops.cleanup_led = e1000_null_ops_generic; 58 mac->ops.setup_led = e1000_null_ops_generic; 59 mac->ops.blink_led = e1000_null_ops_generic; 60 mac->ops.led_on = e1000_null_ops_generic; 61 mac->ops.led_off = e1000_null_ops_generic; 62 /* LINK */ 63 mac->ops.setup_link = e1000_null_ops_generic; 64 mac->ops.get_link_up_info = e1000_null_link_info; 65 mac->ops.check_for_link = e1000_null_ops_generic; 66 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 67 /* Management */ 68 mac->ops.check_mng_mode = e1000_null_mng_mode; 69 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 70 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 71 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 72 /* VLAN, MC, etc. */ 73 mac->ops.update_mc_addr_list = e1000_null_update_mc; 74 mac->ops.clear_vfta = e1000_null_mac_generic; 75 mac->ops.write_vfta = e1000_null_write_vfta; 76 mac->ops.mta_set = e1000_null_mta_set; 77 mac->ops.rar_set = e1000_rar_set_generic; 78 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 79 } 80 81 /* 82 * e1000_null_ops_generic - No-op function, returns 0 83 * @hw: pointer to the HW structure 84 */ 85 s32 86 e1000_null_ops_generic(struct e1000_hw *hw) 87 { 88 DEBUGFUNC("e1000_null_ops_generic"); 89 UNREFERENCED_1PARAMETER(hw); 90 return (E1000_SUCCESS); 91 } 92 93 /* 94 * e1000_null_mac_generic - No-op function, return void 95 * @hw: pointer to the HW structure 96 */ 97 void 98 e1000_null_mac_generic(struct e1000_hw *hw) 99 { 100 DEBUGFUNC("e1000_null_mac_generic"); 101 UNREFERENCED_1PARAMETER(hw); 102 } 103 104 /* 105 * e1000_null_link_info - No-op function, return 0 106 * @hw: pointer to the HW structure 107 */ 108 s32 109 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 110 { 111 DEBUGFUNC("e1000_null_link_info"); 112 UNREFERENCED_3PARAMETER(hw, s, d); 113 return (E1000_SUCCESS); 114 } 115 116 /* 117 * e1000_null_mng_mode - No-op function, return false 118 * @hw: pointer to the HW structure 119 */ 120 bool 121 e1000_null_mng_mode(struct e1000_hw *hw) 122 { 123 DEBUGFUNC("e1000_null_mng_mode"); 124 UNREFERENCED_1PARAMETER(hw); 125 return (false); 126 } 127 128 /* 129 * e1000_null_update_mc - No-op function, return void 130 * @hw: pointer to the HW structure 131 */ 132 void 133 e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 134 { 135 DEBUGFUNC("e1000_null_update_mc"); 136 UNREFERENCED_3PARAMETER(hw, h, a); 137 } 138 139 /* 140 * e1000_null_write_vfta - No-op function, return void 141 * @hw: pointer to the HW structure 142 */ 143 void 144 e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 145 { 146 DEBUGFUNC("e1000_null_write_vfta"); 147 UNREFERENCED_3PARAMETER(hw, a, b); 148 } 149 150 /* 151 * e1000_null_set_mta - No-op function, return void 152 * @hw: pointer to the HW structure 153 */ 154 void 155 e1000_null_mta_set(struct e1000_hw *hw, u32 a) 156 { 157 DEBUGFUNC("e1000_null_mta_set"); 158 UNREFERENCED_2PARAMETER(hw, a); 159 } 160 161 /* 162 * e1000_null_rar_set - No-op function, return void 163 * @hw: pointer to the HW structure 164 */ 165 void 166 e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 167 { 168 DEBUGFUNC("e1000_null_rar_set"); 169 UNREFERENCED_3PARAMETER(hw, h, a); 170 } 171 172 /* 173 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 174 * @hw: pointer to the HW structure 175 * 176 * Determines and stores the system bus information for a particular 177 * network interface. The following bus information is determined and stored: 178 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 179 */ 180 s32 181 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 182 { 183 struct e1000_mac_info *mac = &hw->mac; 184 struct e1000_bus_info *bus = &hw->bus; 185 u32 status = E1000_READ_REG(hw, E1000_STATUS); 186 s32 ret_val = E1000_SUCCESS; 187 188 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 189 190 /* PCI or PCI-X? */ 191 bus->type = (status & E1000_STATUS_PCIX_MODE) 192 ? e1000_bus_type_pcix 193 : e1000_bus_type_pci; 194 195 /* Bus speed */ 196 if (bus->type == e1000_bus_type_pci) { 197 bus->speed = (status & E1000_STATUS_PCI66) 198 ? e1000_bus_speed_66 199 : e1000_bus_speed_33; 200 } else { 201 switch (status & E1000_STATUS_PCIX_SPEED) { 202 case E1000_STATUS_PCIX_SPEED_66: 203 bus->speed = e1000_bus_speed_66; 204 break; 205 case E1000_STATUS_PCIX_SPEED_100: 206 bus->speed = e1000_bus_speed_100; 207 break; 208 case E1000_STATUS_PCIX_SPEED_133: 209 bus->speed = e1000_bus_speed_133; 210 break; 211 default: 212 bus->speed = e1000_bus_speed_reserved; 213 break; 214 } 215 } 216 217 /* Bus width */ 218 bus->width = (status & E1000_STATUS_BUS64) 219 ? e1000_bus_width_64 220 : e1000_bus_width_32; 221 222 /* Which PCI(-X) function? */ 223 mac->ops.set_lan_id(hw); 224 225 return (ret_val); 226 } 227 228 /* 229 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 230 * @hw: pointer to the HW structure 231 * 232 * Determines and stores the system bus information for a particular 233 * network interface. The following bus information is determined and stored: 234 * bus speed, bus width, type (PCIe), and PCIe function. 235 */ 236 s32 237 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 238 { 239 struct e1000_mac_info *mac = &hw->mac; 240 struct e1000_bus_info *bus = &hw->bus; 241 s32 ret_val; 242 u16 pcie_link_status; 243 244 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 245 246 bus->type = e1000_bus_type_pci_express; 247 bus->speed = e1000_bus_speed_2500; 248 249 ret_val = e1000_read_pcie_cap_reg(hw, 250 PCIE_LINK_STATUS, 251 &pcie_link_status); 252 if (ret_val) 253 bus->width = e1000_bus_width_unknown; 254 else 255 bus->width = (enum e1000_bus_width)((pcie_link_status & 256 PCIE_LINK_WIDTH_MASK) >> 257 PCIE_LINK_WIDTH_SHIFT); 258 259 mac->ops.set_lan_id(hw); 260 261 return (E1000_SUCCESS); 262 } 263 264 /* 265 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 266 * 267 * @hw: pointer to the HW structure 268 * 269 * Determines the LAN function id by reading memory-mapped registers 270 * and swaps the port value if requested. 271 */ 272 static void 273 e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 274 { 275 struct e1000_bus_info *bus = &hw->bus; 276 u32 reg; 277 278 /* 279 * The status register reports the correct function number 280 * for the device regardless of function swap state. 281 */ 282 reg = E1000_READ_REG(hw, E1000_STATUS); 283 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 284 } 285 286 /* 287 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 288 * @hw: pointer to the HW structure 289 * 290 * Determines the LAN function id by reading PCI config space. 291 */ 292 void 293 e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 294 { 295 struct e1000_bus_info *bus = &hw->bus; 296 u16 pci_header_type; 297 u32 status; 298 299 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 300 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 301 status = E1000_READ_REG(hw, E1000_STATUS); 302 bus->func = (status & E1000_STATUS_FUNC_MASK) 303 >> E1000_STATUS_FUNC_SHIFT; 304 } else { 305 bus->func = 0; 306 } 307 } 308 309 /* 310 * e1000_set_lan_id_single_port - Set LAN id for a single port device 311 * @hw: pointer to the HW structure 312 * 313 * Sets the LAN function id to zero for a single port device. 314 */ 315 void 316 e1000_set_lan_id_single_port(struct e1000_hw *hw) 317 { 318 struct e1000_bus_info *bus = &hw->bus; 319 320 bus->func = 0; 321 } 322 323 /* 324 * e1000_clear_vfta_generic - Clear VLAN filter table 325 * @hw: pointer to the HW structure 326 * 327 * Clears the register array which contains the VLAN filter table by 328 * setting all the values to 0. 329 */ 330 void 331 e1000_clear_vfta_generic(struct e1000_hw *hw) 332 { 333 u32 offset; 334 335 DEBUGFUNC("e1000_clear_vfta_generic"); 336 337 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 338 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 339 E1000_WRITE_FLUSH(hw); 340 } 341 } 342 343 /* 344 * e1000_write_vfta_generic - Write value to VLAN filter table 345 * @hw: pointer to the HW structure 346 * @offset: register offset in VLAN filter table 347 * @value: register value written to VLAN filter table 348 * 349 * Writes value at the given offset in the register array which stores 350 * the VLAN filter table. 351 */ 352 void 353 e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 354 { 355 DEBUGFUNC("e1000_write_vfta_generic"); 356 357 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 358 E1000_WRITE_FLUSH(hw); 359 } 360 361 /* 362 * e1000_init_rx_addrs_generic - Initialize receive address's 363 * @hw: pointer to the HW structure 364 * @rar_count: receive address registers 365 * 366 * Setups the receive address registers by setting the base receive address 367 * register to the devices MAC address and clearing all the other receive 368 * address registers to 0. 369 */ 370 void 371 e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 372 { 373 u32 i; 374 u8 mac_addr[ETH_ADDR_LEN] = {0}; 375 376 DEBUGFUNC("e1000_init_rx_addrs_generic"); 377 378 /* Setup the receive address */ 379 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 380 381 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 382 383 /* Zero out the other (rar_entry_count - 1) receive addresses */ 384 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count - 1); 385 for (i = 1; i < rar_count; i++) 386 hw->mac.ops.rar_set(hw, mac_addr, i); 387 388 } 389 390 /* 391 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 392 * @hw: pointer to the HW structure 393 * 394 * Checks the nvm for an alternate MAC address. An alternate MAC address 395 * can be setup by pre-boot software and must be treated like a permanent 396 * address and must override the actual permanent MAC address. If an 397 * alternate MAC address is found it is programmed into RAR0, replacing 398 * the permanent address that was installed into RAR0 by the Si on reset. 399 * This function will return SUCCESS unless it encounters an error while 400 * reading the EEPROM. 401 */ 402 s32 403 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 404 { 405 u32 i; 406 s32 ret_val = E1000_SUCCESS; 407 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 408 u8 alt_mac_addr[ETH_ADDR_LEN]; 409 410 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 411 412 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 413 &nvm_alt_mac_addr_offset); 414 if (ret_val) { 415 DEBUGOUT("NVM Read Error\n"); 416 goto out; 417 } 418 419 if (nvm_alt_mac_addr_offset == 0xFFFF) { 420 /* There is no Alternate MAC Address */ 421 goto out; 422 } 423 424 if (hw->bus.func == E1000_FUNC_1) 425 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 426 427 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 428 offset = nvm_alt_mac_addr_offset + (i >> 1); 429 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 430 if (ret_val) { 431 DEBUGOUT("NVM Read Error\n"); 432 goto out; 433 } 434 435 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 436 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 437 } 438 439 /* if multicast bit is set, the alternate address will not be used */ 440 if (alt_mac_addr[0] & 0x01) { 441 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 442 goto out; 443 } 444 445 /* 446 * We have a valid alternate MAC address, and we want to treat it the 447 * same as the normal permanent MAC address stored by the HW into the 448 * RAR. Do this by mapping this address into RAR0. 449 */ 450 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 451 452 out: 453 return (ret_val); 454 } 455 456 /* 457 * e1000_rar_set_generic - Set receive address register 458 * @hw: pointer to the HW structure 459 * @addr: pointer to the receive address 460 * @index: receive address array register 461 * 462 * Sets the receive address array register at index to the address passed 463 * in by addr. 464 */ 465 void 466 e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 467 { 468 u32 rar_low, rar_high; 469 470 DEBUGFUNC("e1000_rar_set_generic"); 471 472 /* 473 * HW expects these in little endian so we reverse the byte order from 474 * network order (big endian) to little endian 475 */ 476 rar_low = ((u32) addr[0] | 477 ((u32) addr[1] << 8) | 478 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 479 480 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 481 482 /* If MAC address zero, no need to set the AV bit */ 483 if (rar_low || rar_high) 484 rar_high |= E1000_RAH_AV; 485 486 /* 487 * Some bridges will combine consecutive 32-bit writes into 488 * a single burst write, which will malfunction on some parts. 489 * The flushes avoid this. 490 */ 491 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 492 E1000_WRITE_FLUSH(hw); 493 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 494 E1000_WRITE_FLUSH(hw); 495 } 496 497 /* 498 * e1000_mta_set_generic - Set multicast filter table address 499 * @hw: pointer to the HW structure 500 * @hash_value: determines the MTA register and bit to set 501 * 502 * The multicast table address is a register array of 32-bit registers. 503 * The hash_value is used to determine what register the bit is in, the 504 * current value is read, the new bit is OR'd in and the new value is 505 * written back into the register. 506 */ 507 void 508 e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 509 { 510 u32 hash_bit, hash_reg, mta; 511 512 DEBUGFUNC("e1000_mta_set_generic"); 513 /* 514 * The MTA is a register array of 32-bit registers. It is treated like 515 * an array of (32*mta_reg_count) bits. We want to set bit 516 * BitArray[hash_value]. So we figure out what register the bit is in, 517 * read it, OR in the new bit, then write back the new value. The 518 * (hw->mac.mta_reg_count - 1) serves as a mask to bits 31:5 of the 519 * hash value which gives us the register we're modifying. The hash 520 * bit within that register is determined by the lower 5 bits of the 521 * hash value. 522 */ 523 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 524 hash_bit = hash_value & 0x1F; 525 526 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 527 528 mta |= (1 << hash_bit); 529 530 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 531 E1000_WRITE_FLUSH(hw); 532 } 533 534 /* 535 * e1000_update_mc_addr_list_generic - Update Multicast addresses 536 * @hw: pointer to the HW structure 537 * @mc_addr_list: array of multicast addresses to program 538 * @mc_addr_count: number of multicast addresses to program 539 * 540 * Updates entire Multicast Table Array. 541 * The caller must have a packed mc_addr_list of multicast addresses. 542 */ 543 void 544 e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 545 u8 *mc_addr_list, u32 mc_addr_count) 546 { 547 u32 hash_value, hash_bit, hash_reg; 548 int i; 549 550 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 551 552 /* clear mta_shadow */ 553 (void) memset(&hw->mac.mta_shadow, 0, sizeof (hw->mac.mta_shadow)); 554 555 /* update mta_shadow from mc_addr_list */ 556 for (i = 0; (u32) i < mc_addr_count; i++) { 557 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 558 559 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 560 hash_bit = hash_value & 0x1F; 561 562 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 563 mc_addr_list += (ETH_ADDR_LEN); 564 } 565 566 /* replace the entire MTA table */ 567 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 568 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 569 E1000_WRITE_FLUSH(hw); 570 } 571 572 /* 573 * e1000_hash_mc_addr_generic - Generate a multicast hash value 574 * @hw: pointer to the HW structure 575 * @mc_addr: pointer to a multicast address 576 * 577 * Generates a multicast address hash value which is used to determine 578 * the multicast filter table array address and new table value. See 579 * e1000_mta_set_generic() 580 */ 581 u32 582 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 583 { 584 u32 hash_value, hash_mask; 585 u8 bit_shift = 0; 586 587 DEBUGFUNC("e1000_hash_mc_addr_generic"); 588 589 /* Register count multiplied by bits per register */ 590 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 591 592 /* 593 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 594 * where 0xFF would still fall within the hash mask. 595 */ 596 while (hash_mask >> bit_shift != 0xFF) 597 bit_shift++; 598 599 /* 600 * The portion of the address that is used for the hash table is 601 * determined by the mc_filter_type setting. The algorithm is such 602 * that there is a total of 8 bits of shifting. The bit_shift for a 603 * mc_filter_type of 0 represents the number of left-shifts where the 604 * MSB of mc_addr[5] would still fall within the hash_mask. Case 0 605 * does this exactly. Since there are a total of 8 bits of shifting, 606 * then mc_addr[4] will shift right the remaining number of bits. Thus 607 * 8 - bit_shift. The rest of the cases are a variation of this 608 * algorithm...essentially raising the number of bits to shift 609 * mc_addr[5] left, while still keeping the 8-bit shifting total. 610 * 611 * For example, given the following Destination MAC Address and an mta 612 * register count of 128 (thus a 4096-bit vector and 0xFFF mask), we 613 * can see that the bit_shift for case 0 is 4. These are the hash 614 * values resulting from each mc_filter_type... 615 * [0] [1] [2] [3] [4] [5] 616 * 01 AA 00 12 34 56 617 * LSB MSB 618 * 619 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 620 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 621 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 622 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 623 */ 624 switch (hw->mac.mc_filter_type) { 625 default: 626 case 0: 627 break; 628 case 1: 629 bit_shift += 1; 630 break; 631 case 2: 632 bit_shift += 2; 633 break; 634 case 3: 635 bit_shift += 4; 636 break; 637 } 638 639 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 640 (((u16) mc_addr[5]) << bit_shift))); 641 642 return (hash_value); 643 } 644 645 /* 646 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 647 * @hw: pointer to the HW structure 648 * 649 * In certain situations, a system BIOS may report that the PCIx maximum 650 * memory read byte count (MMRBC) value is higher than than the actual 651 * value. We check the PCIx command register with the current PCIx status 652 * register. 653 */ 654 void 655 e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 656 { 657 u16 cmd_mmrbc; 658 u16 pcix_cmd; 659 u16 pcix_stat_hi_word; 660 u16 stat_mmrbc; 661 662 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 663 664 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 665 if (hw->bus.type != e1000_bus_type_pcix) 666 return; 667 668 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 669 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 670 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 671 PCIX_COMMAND_MMRBC_SHIFT; 672 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 673 PCIX_STATUS_HI_MMRBC_SHIFT; 674 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 675 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 676 if (cmd_mmrbc > stat_mmrbc) { 677 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 678 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 679 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 680 } 681 } 682 683 /* 684 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 685 * @hw: pointer to the HW structure 686 * 687 * Clears the base hardware counters by reading the counter registers. 688 */ 689 void 690 e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 691 { 692 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 693 694 (void) E1000_READ_REG(hw, E1000_CRCERRS); 695 (void) E1000_READ_REG(hw, E1000_SYMERRS); 696 (void) E1000_READ_REG(hw, E1000_MPC); 697 (void) E1000_READ_REG(hw, E1000_SCC); 698 (void) E1000_READ_REG(hw, E1000_ECOL); 699 (void) E1000_READ_REG(hw, E1000_MCC); 700 (void) E1000_READ_REG(hw, E1000_LATECOL); 701 (void) E1000_READ_REG(hw, E1000_COLC); 702 (void) E1000_READ_REG(hw, E1000_DC); 703 (void) E1000_READ_REG(hw, E1000_SEC); 704 (void) E1000_READ_REG(hw, E1000_RLEC); 705 (void) E1000_READ_REG(hw, E1000_XONRXC); 706 (void) E1000_READ_REG(hw, E1000_XONTXC); 707 (void) E1000_READ_REG(hw, E1000_XOFFRXC); 708 (void) E1000_READ_REG(hw, E1000_XOFFTXC); 709 (void) E1000_READ_REG(hw, E1000_FCRUC); 710 (void) E1000_READ_REG(hw, E1000_GPRC); 711 (void) E1000_READ_REG(hw, E1000_BPRC); 712 (void) E1000_READ_REG(hw, E1000_MPRC); 713 (void) E1000_READ_REG(hw, E1000_GPTC); 714 (void) E1000_READ_REG(hw, E1000_GORCL); 715 (void) E1000_READ_REG(hw, E1000_GORCH); 716 (void) E1000_READ_REG(hw, E1000_GOTCL); 717 (void) E1000_READ_REG(hw, E1000_GOTCH); 718 (void) E1000_READ_REG(hw, E1000_RNBC); 719 (void) E1000_READ_REG(hw, E1000_RUC); 720 (void) E1000_READ_REG(hw, E1000_RFC); 721 (void) E1000_READ_REG(hw, E1000_ROC); 722 (void) E1000_READ_REG(hw, E1000_RJC); 723 (void) E1000_READ_REG(hw, E1000_TORL); 724 (void) E1000_READ_REG(hw, E1000_TORH); 725 (void) E1000_READ_REG(hw, E1000_TOTL); 726 (void) E1000_READ_REG(hw, E1000_TOTH); 727 (void) E1000_READ_REG(hw, E1000_TPR); 728 (void) E1000_READ_REG(hw, E1000_TPT); 729 (void) E1000_READ_REG(hw, E1000_MPTC); 730 (void) E1000_READ_REG(hw, E1000_BPTC); 731 } 732 733 /* 734 * e1000_check_for_copper_link_generic - Check for link (Copper) 735 * @hw: pointer to the HW structure 736 * 737 * Checks to see of the link status of the hardware has changed. If a 738 * change in link status has been detected, then we read the PHY registers 739 * to get the current speed/duplex if link exists. 740 */ 741 s32 742 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 743 { 744 struct e1000_mac_info *mac = &hw->mac; 745 s32 ret_val; 746 bool link; 747 748 DEBUGFUNC("e1000_check_for_copper_link"); 749 750 /* 751 * We only want to go out to the PHY registers to see if Auto-Neg has 752 * completed and/or if our link status has changed. The 753 * get_link_status flag is set upon receiving a Link Status Change or 754 * Rx Sequence Error interrupt. 755 */ 756 if (!mac->get_link_status) { 757 ret_val = E1000_SUCCESS; 758 goto out; 759 } 760 761 /* 762 * First we want to see if the MII Status Register reports link. If 763 * so, then we want to get the current speed/duplex of the PHY. 764 */ 765 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 766 if (ret_val) 767 goto out; 768 769 if (!link) 770 goto out; /* No link detected */ 771 772 mac->get_link_status = false; 773 774 /* 775 * Check if there was DownShift, must be checked immediately after 776 * link-up 777 */ 778 (void) e1000_check_downshift_generic(hw); 779 780 /* 781 * If we are forcing speed/duplex, then we simply return since we have 782 * already determined whether we have link or not. 783 */ 784 if (!mac->autoneg) { 785 ret_val = -E1000_ERR_CONFIG; 786 goto out; 787 } 788 789 /* 790 * Auto-Neg is enabled. Auto Speed Detection takes care of MAC 791 * speed/duplex configuration. So we only need to configure Collision 792 * Distance in the MAC. 793 */ 794 e1000_config_collision_dist_generic(hw); 795 796 /* 797 * Configure Flow Control now that Auto-Neg has completed. First, we 798 * need to restore the desired flow control settings because we may 799 * have had to re-autoneg with a different link partner. 800 */ 801 ret_val = e1000_config_fc_after_link_up_generic(hw); 802 if (ret_val) { 803 /* EMPTY */ 804 DEBUGOUT("Error configuring flow control\n"); 805 } 806 807 out: 808 return (ret_val); 809 } 810 811 /* 812 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 813 * @hw: pointer to the HW structure 814 * 815 * Checks for link up on the hardware. If link is not up and we have 816 * a signal, then we need to force link up. 817 */ 818 s32 819 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 820 { 821 struct e1000_mac_info *mac = &hw->mac; 822 u32 rxcw; 823 u32 ctrl; 824 u32 status; 825 s32 ret_val = E1000_SUCCESS; 826 827 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 828 829 ctrl = E1000_READ_REG(hw, E1000_CTRL); 830 status = E1000_READ_REG(hw, E1000_STATUS); 831 rxcw = E1000_READ_REG(hw, E1000_RXCW); 832 833 /* 834 * If we don't have link (auto-negotiation failed or link partner 835 * cannot auto-negotiate), the cable is plugged in (we have signal), 836 * and our link partner is not trying to auto-negotiate with us (we 837 * are receiving idles or data), we need to force link up. We also 838 * need to give auto-negotiation time to complete, in case the cable 839 * was just plugged in. The autoneg_failed flag does this. 840 */ 841 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 842 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 843 (!(rxcw & E1000_RXCW_C))) { 844 if (mac->autoneg_failed == 0) { 845 mac->autoneg_failed = 1; 846 goto out; 847 } 848 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 849 850 /* Disable auto-negotiation in the TXCW register */ 851 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 852 853 /* Force link-up and also force full-duplex. */ 854 ctrl = E1000_READ_REG(hw, E1000_CTRL); 855 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 856 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 857 858 /* Configure Flow Control after forcing link up. */ 859 ret_val = e1000_config_fc_after_link_up_generic(hw); 860 if (ret_val) { 861 DEBUGOUT("Error configuring flow control\n"); 862 goto out; 863 } 864 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 865 /* 866 * If we are forcing link and we are receiving /C/ ordered 867 * sets, re-enable auto-negotiation in the TXCW register and 868 * disable forced link in the Device Control register in an 869 * attempt to auto-negotiate with our link partner. 870 */ 871 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 872 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 873 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 874 875 mac->serdes_has_link = true; 876 } 877 878 out: 879 return (ret_val); 880 } 881 882 /* 883 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 884 * @hw: pointer to the HW structure 885 * 886 * Checks for link up on the hardware. If link is not up and we have 887 * a signal, then we need to force link up. 888 */ 889 s32 890 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 891 { 892 struct e1000_mac_info *mac = &hw->mac; 893 u32 rxcw; 894 u32 ctrl; 895 u32 status; 896 s32 ret_val = E1000_SUCCESS; 897 898 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 899 900 ctrl = E1000_READ_REG(hw, E1000_CTRL); 901 status = E1000_READ_REG(hw, E1000_STATUS); 902 rxcw = E1000_READ_REG(hw, E1000_RXCW); 903 904 /* 905 * If we don't have link (auto-negotiation failed or link partner 906 * cannot auto-negotiate), and our link partner is not trying to 907 * auto-negotiate with us (we are receiving idles or data), we need to 908 * force link up. We also need to give auto-negotiation time to 909 * complete. 910 */ 911 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 912 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 913 if (mac->autoneg_failed == 0) { 914 mac->autoneg_failed = 1; 915 goto out; 916 } 917 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 918 919 /* Disable auto-negotiation in the TXCW register */ 920 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 921 922 /* Force link-up and also force full-duplex. */ 923 ctrl = E1000_READ_REG(hw, E1000_CTRL); 924 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 925 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 926 927 /* Configure Flow Control after forcing link up. */ 928 ret_val = e1000_config_fc_after_link_up_generic(hw); 929 if (ret_val) { 930 DEBUGOUT("Error configuring flow control\n"); 931 goto out; 932 } 933 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 934 /* 935 * If we are forcing link and we are receiving /C/ ordered 936 * sets, re-enable auto-negotiation in the TXCW register and 937 * disable forced link in the Device Control register in an 938 * attempt to auto-negotiate with our link partner. 939 */ 940 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 941 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 942 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 943 944 mac->serdes_has_link = true; 945 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 946 /* 947 * If we force link for non-auto-negotiation switch, check 948 * link status based on MAC synchronization for internal 949 * serdes media type. 950 */ 951 /* SYNCH bit and IV bit are sticky. */ 952 usec_delay(10); 953 rxcw = E1000_READ_REG(hw, E1000_RXCW); 954 if (rxcw & E1000_RXCW_SYNCH) { 955 if (!(rxcw & E1000_RXCW_IV)) { 956 mac->serdes_has_link = true; 957 DEBUGOUT("SERDES: Link up - forced.\n"); 958 } 959 } else { 960 mac->serdes_has_link = false; 961 DEBUGOUT("SERDES: Link down - force failed.\n"); 962 } 963 } 964 965 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 966 status = E1000_READ_REG(hw, E1000_STATUS); 967 if (status & E1000_STATUS_LU) { 968 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 969 usec_delay(10); 970 rxcw = E1000_READ_REG(hw, E1000_RXCW); 971 if (rxcw & E1000_RXCW_SYNCH) { 972 if (!(rxcw & E1000_RXCW_IV)) { 973 mac->serdes_has_link = true; 974 DEBUGOUT("SERDES: Link up - autoneg " 975 "completed sucessfully.\n"); 976 } else { 977 mac->serdes_has_link = false; 978 DEBUGOUT("SERDES: Link down - invalid" 979 "codewords detected in autoneg.\n"); 980 } 981 } else { 982 mac->serdes_has_link = false; 983 DEBUGOUT("SERDES: Link down - no sync.\n"); 984 } 985 } else { 986 mac->serdes_has_link = false; 987 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 988 } 989 } 990 991 out: 992 return (ret_val); 993 } 994 995 /* 996 * e1000_setup_link_generic - Setup flow control and link settings 997 * @hw: pointer to the HW structure 998 * 999 * Determines which flow control settings to use, then configures flow 1000 * control. Calls the appropriate media-specific link configuration 1001 * function. Assuming the adapter has a valid link partner, a valid link 1002 * should be established. Assumes the hardware has previously been reset 1003 * and the transmitter and receiver are not enabled. 1004 */ 1005 s32 1006 e1000_setup_link_generic(struct e1000_hw *hw) 1007 { 1008 s32 ret_val = E1000_SUCCESS; 1009 1010 DEBUGFUNC("e1000_setup_link_generic"); 1011 1012 /* 1013 * In the case of the phy reset being blocked, we already have a link. 1014 * We do not need to set it up again. 1015 */ 1016 if (hw->phy.ops.check_reset_block) 1017 if (hw->phy.ops.check_reset_block(hw)) 1018 goto out; 1019 1020 /* 1021 * If requested flow control is set to default, set flow control 1022 * based on the EEPROM flow control settings. 1023 */ 1024 if (hw->fc.requested_mode == e1000_fc_default) { 1025 ret_val = e1000_set_default_fc_generic(hw); 1026 if (ret_val) 1027 goto out; 1028 } 1029 1030 /* 1031 * Save off the requested flow control mode for use later. Depending 1032 * on the link partner's capabilities, we may or may not use this mode. 1033 */ 1034 hw->fc.current_mode = hw->fc.requested_mode; 1035 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1036 hw->fc.current_mode); 1037 1038 /* Call the necessary media_type subroutine to configure the link. */ 1039 ret_val = hw->mac.ops.setup_physical_interface(hw); 1040 if (ret_val) 1041 goto out; 1042 1043 /* 1044 * Initialize the flow control address, type, and PAUSE timer 1045 * registers to their default values. This is done even if flow 1046 * control is disabled, because it does not hurt anything to 1047 * initialize these registers. 1048 */ 1049 DEBUGOUT("Initializing Flow Control address, type and timer regs\n"); 1050 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1051 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1052 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1053 1054 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1055 1056 ret_val = e1000_set_fc_watermarks_generic(hw); 1057 1058 out: 1059 return (ret_val); 1060 } 1061 1062 /* 1063 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1064 * @hw: pointer to the HW structure 1065 * 1066 * Configures collision distance and flow control for fiber and serdes 1067 * links. Upon successful setup, poll for link. 1068 */ 1069 s32 1070 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1071 { 1072 u32 ctrl; 1073 s32 ret_val = E1000_SUCCESS; 1074 1075 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1076 1077 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1078 1079 /* Take the link out of reset */ 1080 ctrl &= ~E1000_CTRL_LRST; 1081 1082 e1000_config_collision_dist_generic(hw); 1083 1084 ret_val = e1000_commit_fc_settings_generic(hw); 1085 if (ret_val) 1086 goto out; 1087 1088 /* 1089 * Since auto-negotiation is enabled, take the link out of reset (the 1090 * link will be in reset, because we previously reset the chip). This 1091 * will restart auto-negotiation. If auto-negotiation is successful 1092 * then the link-up status bit will be set and the flow control enable 1093 * bits (RFCE and TFCE) will be set according to their negotiated value. 1094 */ 1095 DEBUGOUT("Auto-negotiation enabled\n"); 1096 1097 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1098 E1000_WRITE_FLUSH(hw); 1099 msec_delay(1); 1100 1101 /* 1102 * For these adapters, the SW definable pin 1 is set when the optics 1103 * detect a signal. If we have a signal, then poll for a "Link-Up" 1104 * indication. 1105 */ 1106 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1107 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1108 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1109 } else { 1110 /* EMPTY */ 1111 DEBUGOUT("No signal detected\n"); 1112 } 1113 1114 out: 1115 return (ret_val); 1116 } 1117 1118 /* 1119 * e1000_config_collision_dist_generic - Configure collision distance 1120 * @hw: pointer to the HW structure 1121 * 1122 * Configures the collision distance to the default value and is used 1123 * during link setup. Currently no func pointer exists and all 1124 * implementations are handled in the generic version of this function. 1125 */ 1126 void 1127 e1000_config_collision_dist_generic(struct e1000_hw *hw) 1128 { 1129 u32 tctl; 1130 1131 DEBUGFUNC("e1000_config_collision_dist_generic"); 1132 1133 tctl = E1000_READ_REG(hw, E1000_TCTL); 1134 1135 tctl &= ~E1000_TCTL_COLD; 1136 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1137 1138 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1139 E1000_WRITE_FLUSH(hw); 1140 } 1141 1142 /* 1143 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1144 * @hw: pointer to the HW structure 1145 * 1146 * Polls for link up by reading the status register, if link fails to come 1147 * up with auto-negotiation, then the link is forced if a signal is detected. 1148 */ 1149 s32 1150 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1151 { 1152 struct e1000_mac_info *mac = &hw->mac; 1153 u32 i, status; 1154 s32 ret_val = E1000_SUCCESS; 1155 1156 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1157 1158 /* 1159 * If we have a signal (the cable is plugged in, or assumed true for 1160 * serdes media) then poll for a "Link-Up" indication in the Device 1161 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1162 * seconds (Auto-negotiation should complete in less than 500 1163 * milliseconds even if the other end is doing it in SW). 1164 */ 1165 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1166 msec_delay(10); 1167 status = E1000_READ_REG(hw, E1000_STATUS); 1168 if (status & E1000_STATUS_LU) 1169 break; 1170 } 1171 if (i == FIBER_LINK_UP_LIMIT) { 1172 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1173 mac->autoneg_failed = 1; 1174 /* 1175 * AutoNeg failed to achieve a link, so we'll call 1176 * mac->check_for_link. This routine will force the link up if 1177 * we detect a signal. This will allow us to communicate with 1178 * non-autonegotiating link partners. 1179 */ 1180 ret_val = hw->mac.ops.check_for_link(hw); 1181 if (ret_val) { 1182 DEBUGOUT("Error while checking for link\n"); 1183 goto out; 1184 } 1185 mac->autoneg_failed = 0; 1186 } else { 1187 mac->autoneg_failed = 0; 1188 DEBUGOUT("Valid Link Found\n"); 1189 } 1190 1191 out: 1192 return (ret_val); 1193 } 1194 1195 /* 1196 * e1000_commit_fc_settings_generic - Configure flow control 1197 * @hw: pointer to the HW structure 1198 * 1199 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1200 * base on the flow control settings in e1000_mac_info. 1201 */ 1202 s32 1203 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1204 { 1205 struct e1000_mac_info *mac = &hw->mac; 1206 u32 txcw; 1207 s32 ret_val = E1000_SUCCESS; 1208 1209 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1210 1211 /* 1212 * Check for a software override of the flow control settings, and 1213 * setup the device accordingly. If auto-negotiation is enabled, then 1214 * software will have to set the "PAUSE" bits to the correct value in 1215 * the Transmit Config Word Register (TXCW) and re-start auto- 1216 * negotiation. However, if auto-negotiation is disabled, then 1217 * software will have to manually configure the two flow control enable 1218 * bits in the CTRL register. 1219 * 1220 * The possible values of the "fc" parameter are: 1221 * 0: Flow control is completely disabled 1222 * 1: Rx flow control is enabled (we can receive pause frames, 1223 * but not send pause frames). 1224 * 2: Tx flow control is enabled (we can send pause frames but we 1225 * do not support receiving pause frames). 1226 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1227 */ 1228 switch (hw->fc.current_mode) { 1229 case e1000_fc_none: 1230 /* Flow control completely disabled by a software over-ride. */ 1231 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1232 break; 1233 case e1000_fc_rx_pause: 1234 /* 1235 * Rx Flow control is enabled and Tx Flow control is disabled 1236 * by a software over-ride. Since there really isn't a way to 1237 * advertise that we are capable of Rx Pause ONLY, we will 1238 * advertise that we support both symmetric and asymmetric RX 1239 * PAUSE. Later, we will disable the adapter's ability to send 1240 * PAUSE frames. 1241 */ 1242 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1243 break; 1244 case e1000_fc_tx_pause: 1245 /* 1246 * Tx Flow control is enabled, and Rx Flow control is disabled, 1247 * by a software over-ride. 1248 */ 1249 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1250 break; 1251 case e1000_fc_full: 1252 /* 1253 * Flow control (both Rx and Tx) is enabled by a software 1254 * over-ride. 1255 */ 1256 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1257 break; 1258 default: 1259 DEBUGOUT("Flow control param set incorrectly\n"); 1260 ret_val = -E1000_ERR_CONFIG; 1261 goto out; 1262 } 1263 1264 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1265 mac->txcw = txcw; 1266 1267 out: 1268 return (ret_val); 1269 } 1270 1271 /* 1272 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1273 * @hw: pointer to the HW structure 1274 * 1275 * Sets the flow control high/low threshold (watermark) registers. If 1276 * flow control XON frame transmission is enabled, then set XON frame 1277 * transmission as well. 1278 */ 1279 s32 1280 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1281 { 1282 s32 ret_val = E1000_SUCCESS; 1283 u32 fcrtl = 0, fcrth = 0; 1284 1285 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1286 1287 /* 1288 * Set the flow control receive threshold registers. Normally, these 1289 * registers will be set to a default threshold that may be adjusted 1290 * later by the driver's runtime code. However, if the ability to 1291 * transmit pause frames is not enabled, then these registers will be 1292 * set to 0. 1293 */ 1294 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1295 /* 1296 * We need to set up the Receive Threshold high and low water 1297 * marks as well as (optionally) enabling the transmission of 1298 * XON frames. 1299 */ 1300 fcrtl = hw->fc.low_water; 1301 if (hw->fc.send_xon) 1302 fcrtl |= E1000_FCRTL_XONE; 1303 1304 fcrth = hw->fc.high_water; 1305 } 1306 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1307 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1308 1309 return (ret_val); 1310 } 1311 1312 /* 1313 * e1000_set_default_fc_generic - Set flow control default values 1314 * @hw: pointer to the HW structure 1315 * 1316 * Read the EEPROM for the default values for flow control and store the 1317 * values. 1318 */ 1319 s32 1320 e1000_set_default_fc_generic(struct e1000_hw *hw) 1321 { 1322 s32 ret_val = E1000_SUCCESS; 1323 u16 nvm_data; 1324 1325 DEBUGFUNC("e1000_set_default_fc_generic"); 1326 1327 /* 1328 * Read and store word 0x0F of the EEPROM. This word contains bits 1329 * that determine the hardware's default PAUSE (flow control) mode, a 1330 * bit that determines whether the HW defaults to enabling or 1331 * disabling auto-negotiation, and the direction of the SW defined 1332 * pins. If there is no SW over-ride of the flow control setting, then 1333 * the variable hw->fc will be initialized based on a value in the 1334 * EEPROM. 1335 */ 1336 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1337 1338 if (ret_val) { 1339 DEBUGOUT("NVM Read Error\n"); 1340 goto out; 1341 } 1342 1343 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1344 hw->fc.requested_mode = e1000_fc_none; 1345 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1346 NVM_WORD0F_ASM_DIR) 1347 hw->fc.requested_mode = e1000_fc_tx_pause; 1348 else 1349 hw->fc.requested_mode = e1000_fc_full; 1350 1351 out: 1352 return (ret_val); 1353 } 1354 1355 /* 1356 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1357 * @hw: pointer to the HW structure 1358 * 1359 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1360 * device control register to reflect the adapter settings. TFCE and RFCE 1361 * need to be explicitly set by software when a copper PHY is used because 1362 * autonegotiation is managed by the PHY rather than the MAC. Software must 1363 * also configure these bits when link is forced on a fiber connection. 1364 */ 1365 s32 1366 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1367 { 1368 u32 ctrl; 1369 s32 ret_val = E1000_SUCCESS; 1370 1371 DEBUGFUNC("e1000_force_mac_fc_generic"); 1372 1373 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1374 1375 /* 1376 * Because we didn't get link via the internal auto-negotiation 1377 * mechanism (we either forced link or we got link via PHY auto-neg), 1378 * we have to manually enable/disable transmit an receive flow 1379 * control. 1380 * 1381 * The "Case" statement below enables/disable flow control according to 1382 * the "hw->fc.current_mode" parameter. 1383 * 1384 * The possible values of the "fc" parameter are: 1385 * 0: Flow control is completely disabled 1386 * 1: Rx flow control is enabled (we can receive pause 1387 * frames but not send pause frames). 1388 * 2: Tx flow control is enabled (we can send pause frames 1389 * frames but we do not receive pause frames). 1390 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1391 * other: No other values should be possible at this point. 1392 */ 1393 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1394 1395 switch (hw->fc.current_mode) { 1396 case e1000_fc_none: 1397 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1398 break; 1399 case e1000_fc_rx_pause: 1400 ctrl &= (~E1000_CTRL_TFCE); 1401 ctrl |= E1000_CTRL_RFCE; 1402 break; 1403 case e1000_fc_tx_pause: 1404 ctrl &= (~E1000_CTRL_RFCE); 1405 ctrl |= E1000_CTRL_TFCE; 1406 break; 1407 case e1000_fc_full: 1408 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1409 break; 1410 default: 1411 DEBUGOUT("Flow control param set incorrectly\n"); 1412 ret_val = -E1000_ERR_CONFIG; 1413 goto out; 1414 } 1415 1416 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1417 1418 out: 1419 return (ret_val); 1420 } 1421 1422 /* 1423 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1424 * @hw: pointer to the HW structure 1425 * 1426 * Checks the status of auto-negotiation after link up to ensure that the 1427 * speed and duplex were not forced. If the link needed to be forced, then 1428 * flow control needs to be forced also. If auto-negotiation is enabled 1429 * and did not fail, then we configure flow control based on our link 1430 * partner. 1431 */ 1432 s32 1433 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1434 { 1435 struct e1000_mac_info *mac = &hw->mac; 1436 s32 ret_val = E1000_SUCCESS; 1437 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1438 u16 speed, duplex; 1439 1440 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1441 1442 /* 1443 * Check for the case where we have fiber media and auto-neg failed so 1444 * we had to force link. In this case, we need to force the 1445 * configuration of the MAC to match the "fc" parameter. 1446 */ 1447 if (mac->autoneg_failed) { 1448 if (hw->phy.media_type == e1000_media_type_fiber || 1449 hw->phy.media_type == e1000_media_type_internal_serdes) 1450 ret_val = e1000_force_mac_fc_generic(hw); 1451 } else { 1452 if (hw->phy.media_type == e1000_media_type_copper) 1453 ret_val = e1000_force_mac_fc_generic(hw); 1454 } 1455 1456 if (ret_val) { 1457 DEBUGOUT("Error forcing flow control settings\n"); 1458 goto out; 1459 } 1460 1461 /* 1462 * Check for the case where we have copper media and auto-neg is 1463 * enabled. In this case, we need to check and see if Auto-Neg has 1464 * completed, and if so, how the PHY and link partner has flow control 1465 * configured. 1466 */ 1467 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1468 /* 1469 * Read the MII Status Register and check to see if AutoNeg 1470 * has completed. We read this twice because this reg has 1471 * some "sticky" (latched) bits. 1472 */ 1473 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1474 if (ret_val) 1475 goto out; 1476 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1477 if (ret_val) 1478 goto out; 1479 1480 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1481 DEBUGOUT("Copper PHY and Auto Neg " 1482 "has not completed.\n"); 1483 goto out; 1484 } 1485 /* 1486 * The AutoNeg process has completed, so we now need to read 1487 * both the Auto Negotiation Advertisement Register (Address 1488 * 4) and the Auto_Negotiation Base Page Ability Register 1489 * (Address 5) to determine how flow control was negotiated. 1490 */ 1491 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1492 &mii_nway_adv_reg); 1493 if (ret_val) 1494 goto out; 1495 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1496 &mii_nway_lp_ability_reg); 1497 if (ret_val) 1498 goto out; 1499 1500 /* 1501 * Two bits in the Auto Negotiation Advertisement Register 1502 * (Address 4) and two bits in the Auto Negotiation Base 1503 * Page Ability Register (Address 5) determine flow control 1504 * for both the PHY and the link partner. The following 1505 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1506 * 1999, describes these PAUSE resolution bits and how flow 1507 * control is determined based upon these settings. 1508 * NOTE: DC = Don't Care 1509 * 1510 * LOCAL DEVICE | LINK PARTNER 1511 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1512 * ------|---------|-------|---------|-------------------- 1513 * 0 | 0 | DC | DC | e1000_fc_none 1514 * 0 | 1 | 0 | DC | e1000_fc_none 1515 * 0 | 1 | 1 | 0 | e1000_fc_none 1516 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1517 * 1 | 0 | 0 | DC | e1000_fc_none 1518 * 1 | DC | 1 | DC | e1000_fc_full 1519 * 1 | 1 | 0 | 0 | e1000_fc_none 1520 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1521 * 1522 * Are both PAUSE bits set to 1? If so, this implies 1523 * Symmetric Flow Control is enabled at both ends. The 1524 * ASM_DIR bits are irrelevant per the spec. 1525 * 1526 * For Symmetric Flow Control: 1527 * 1528 * LOCAL DEVICE | LINK PARTNER 1529 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1530 * ------|---------|-------|---------|-------------------- 1531 * 1 | DC | 1 | DC | E1000_fc_full 1532 * 1533 */ 1534 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1535 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1536 /* 1537 * Now we need to check if the user selected Rx ONLY 1538 * of pause frames. In this case, we had to advertise 1539 * FULL flow control because we could not advertise RX 1540 * ONLY. Hence, we must now check to see if we need to 1541 * turn OFF the TRANSMISSION of PAUSE frames. 1542 */ 1543 if (hw->fc.requested_mode == e1000_fc_full) { 1544 hw->fc.current_mode = e1000_fc_full; 1545 DEBUGOUT("Flow Control = FULL.\r\n"); 1546 } else { 1547 hw->fc.current_mode = e1000_fc_rx_pause; 1548 DEBUGOUT("Flow Control = " 1549 "RX PAUSE frames only.\r\n"); 1550 } 1551 } 1552 /* 1553 * For receiving PAUSE frames ONLY. 1554 * 1555 * LOCAL DEVICE | LINK PARTNER 1556 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1557 * ------|---------|-------|---------|-------------------- 1558 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1559 */ 1560 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1561 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1562 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1563 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1564 hw->fc.current_mode = e1000_fc_tx_pause; 1565 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1566 } 1567 /* 1568 * For transmitting PAUSE frames ONLY. 1569 * 1570 * LOCAL DEVICE | LINK PARTNER 1571 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1572 * ------|---------|-------|---------|-------------------- 1573 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1574 */ 1575 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1576 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1577 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1578 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1579 hw->fc.current_mode = e1000_fc_rx_pause; 1580 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1581 } else { 1582 /* 1583 * Per the IEEE spec, at this point flow control 1584 * should be disabled. 1585 */ 1586 hw->fc.current_mode = e1000_fc_none; 1587 DEBUGOUT("Flow Control = NONE.\r\n"); 1588 } 1589 1590 /* 1591 * Now we need to do one last check... If we auto- negotiated 1592 * to HALF DUPLEX, flow control should not be enabled per IEEE 1593 * 802.3 spec. 1594 */ 1595 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1596 if (ret_val) { 1597 DEBUGOUT("Error getting link speed and duplex\n"); 1598 goto out; 1599 } 1600 1601 if (duplex == HALF_DUPLEX) 1602 hw->fc.current_mode = e1000_fc_none; 1603 1604 /* 1605 * Now we call a subroutine to actually force the MAC 1606 * controller to use the correct flow control settings. 1607 */ 1608 ret_val = e1000_force_mac_fc_generic(hw); 1609 if (ret_val) { 1610 DEBUGOUT("Error forcing flow control settings\n"); 1611 goto out; 1612 } 1613 } 1614 1615 out: 1616 return (ret_val); 1617 } 1618 1619 /* 1620 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1621 * @hw: pointer to the HW structure 1622 * @speed: stores the current speed 1623 * @duplex: stores the current duplex 1624 * 1625 * Read the status register for the current speed/duplex and store the current 1626 * speed and duplex for copper connections. 1627 */ 1628 s32 1629 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1630 u16 *duplex) 1631 { 1632 u32 status; 1633 1634 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1635 1636 status = E1000_READ_REG(hw, E1000_STATUS); 1637 if (status & E1000_STATUS_SPEED_1000) { 1638 *speed = SPEED_1000; 1639 DEBUGOUT("1000 Mbs, "); 1640 } else if (status & E1000_STATUS_SPEED_100) { 1641 *speed = SPEED_100; 1642 DEBUGOUT("100 Mbs, "); 1643 } else { 1644 *speed = SPEED_10; 1645 DEBUGOUT("10 Mbs, "); 1646 } 1647 1648 if (status & E1000_STATUS_FD) { 1649 *duplex = FULL_DUPLEX; 1650 DEBUGOUT("Full Duplex\n"); 1651 } else { 1652 *duplex = HALF_DUPLEX; 1653 DEBUGOUT("Half Duplex\n"); 1654 } 1655 1656 return (E1000_SUCCESS); 1657 } 1658 1659 /* 1660 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1661 * @hw: pointer to the HW structure 1662 * @speed: stores the current speed 1663 * @duplex: stores the current duplex 1664 * 1665 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1666 * for fiber/serdes links. 1667 */ 1668 s32 1669 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1670 u16 *speed, u16 *duplex) 1671 { 1672 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1673 UNREFERENCED_1PARAMETER(hw); 1674 1675 *speed = SPEED_1000; 1676 *duplex = FULL_DUPLEX; 1677 1678 return (E1000_SUCCESS); 1679 } 1680 1681 /* 1682 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1683 * @hw: pointer to the HW structure 1684 * 1685 * Acquire the HW semaphore to access the PHY or NVM 1686 */ 1687 s32 1688 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1689 { 1690 u32 swsm; 1691 s32 ret_val = E1000_SUCCESS; 1692 s32 timeout = hw->nvm.word_size + 1; 1693 s32 i = 0; 1694 1695 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1696 1697 /* Get the SW semaphore */ 1698 while (i < timeout) { 1699 swsm = E1000_READ_REG(hw, E1000_SWSM); 1700 if (!(swsm & E1000_SWSM_SMBI)) 1701 break; 1702 1703 usec_delay(50); 1704 i++; 1705 } 1706 1707 if (i == timeout) { 1708 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1709 ret_val = -E1000_ERR_NVM; 1710 goto out; 1711 } 1712 1713 /* Get the FW semaphore. */ 1714 for (i = 0; i < timeout; i++) { 1715 swsm = E1000_READ_REG(hw, E1000_SWSM); 1716 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1717 1718 /* Semaphore acquired if bit latched */ 1719 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1720 break; 1721 1722 usec_delay(50); 1723 } 1724 1725 if (i == timeout) { 1726 /* Release semaphores */ 1727 e1000_put_hw_semaphore_generic(hw); 1728 DEBUGOUT("Driver can't access the NVM\n"); 1729 ret_val = -E1000_ERR_NVM; 1730 goto out; 1731 } 1732 1733 out: 1734 return (ret_val); 1735 } 1736 1737 /* 1738 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1739 * @hw: pointer to the HW structure 1740 * 1741 * Release hardware semaphore used to access the PHY or NVM 1742 */ 1743 void 1744 e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1745 { 1746 u32 swsm; 1747 1748 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1749 1750 swsm = E1000_READ_REG(hw, E1000_SWSM); 1751 1752 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1753 1754 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1755 } 1756 1757 /* 1758 * e1000_get_auto_rd_done_generic - Check for auto read completion 1759 * @hw: pointer to the HW structure 1760 * 1761 * Check EEPROM for Auto Read done bit. 1762 */ 1763 s32 1764 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1765 { 1766 s32 i = 0; 1767 s32 ret_val = E1000_SUCCESS; 1768 1769 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1770 1771 while (i < AUTO_READ_DONE_TIMEOUT) { 1772 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1773 break; 1774 msec_delay(1); 1775 i++; 1776 } 1777 1778 if (i == AUTO_READ_DONE_TIMEOUT) { 1779 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1780 ret_val = -E1000_ERR_RESET; 1781 goto out; 1782 } 1783 1784 out: 1785 return (ret_val); 1786 } 1787 1788 /* 1789 * e1000_valid_led_default_generic - Verify a valid default LED config 1790 * @hw: pointer to the HW structure 1791 * @data: pointer to the NVM (EEPROM) 1792 * 1793 * Read the EEPROM for the current default LED configuration. If the 1794 * LED configuration is not valid, set to a valid LED configuration. 1795 */ 1796 s32 1797 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1798 { 1799 s32 ret_val; 1800 1801 DEBUGFUNC("e1000_valid_led_default_generic"); 1802 1803 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1804 if (ret_val) { 1805 DEBUGOUT("NVM Read Error\n"); 1806 goto out; 1807 } 1808 1809 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1810 *data = ID_LED_DEFAULT; 1811 1812 out: 1813 return (ret_val); 1814 } 1815 1816 /* 1817 * e1000_id_led_init_generic - 1818 * @hw: pointer to the HW structure 1819 * 1820 */ 1821 s32 1822 e1000_id_led_init_generic(struct e1000_hw *hw) 1823 { 1824 struct e1000_mac_info *mac = &hw->mac; 1825 s32 ret_val; 1826 const u32 ledctl_mask = 0x000000FF; 1827 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1828 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1829 u16 data, i, temp; 1830 const u16 led_mask = 0x0F; 1831 1832 DEBUGFUNC("e1000_id_led_init_generic"); 1833 1834 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1835 if (ret_val) 1836 goto out; 1837 1838 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1839 mac->ledctl_mode1 = mac->ledctl_default; 1840 mac->ledctl_mode2 = mac->ledctl_default; 1841 1842 for (i = 0; i < 4; i++) { 1843 temp = (data >> (i << 2)) & led_mask; 1844 switch (temp) { 1845 case ID_LED_ON1_DEF2: 1846 case ID_LED_ON1_ON2: 1847 case ID_LED_ON1_OFF2: 1848 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1849 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1850 break; 1851 case ID_LED_OFF1_DEF2: 1852 case ID_LED_OFF1_ON2: 1853 case ID_LED_OFF1_OFF2: 1854 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1855 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1856 break; 1857 default: 1858 /* Do nothing */ 1859 break; 1860 } 1861 switch (temp) { 1862 case ID_LED_DEF1_ON2: 1863 case ID_LED_ON1_ON2: 1864 case ID_LED_OFF1_ON2: 1865 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1866 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1867 break; 1868 case ID_LED_DEF1_OFF2: 1869 case ID_LED_ON1_OFF2: 1870 case ID_LED_OFF1_OFF2: 1871 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1872 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1873 break; 1874 default: 1875 /* Do nothing */ 1876 break; 1877 } 1878 } 1879 1880 out: 1881 return (ret_val); 1882 } 1883 1884 /* 1885 * e1000_setup_led_generic - Configures SW controllable LED 1886 * @hw: pointer to the HW structure 1887 * 1888 * This prepares the SW controllable LED for use and saves the current state 1889 * of the LED so it can be later restored. 1890 */ 1891 s32 1892 e1000_setup_led_generic(struct e1000_hw *hw) 1893 { 1894 u32 ledctl; 1895 s32 ret_val = E1000_SUCCESS; 1896 1897 DEBUGFUNC("e1000_setup_led_generic"); 1898 1899 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1900 ret_val = -E1000_ERR_CONFIG; 1901 goto out; 1902 } 1903 1904 if (hw->phy.media_type == e1000_media_type_fiber) { 1905 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1906 hw->mac.ledctl_default = ledctl; 1907 /* Turn off LED0 */ 1908 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1909 E1000_LEDCTL_LED0_BLINK | 1910 E1000_LEDCTL_LED0_MODE_MASK); 1911 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1912 E1000_LEDCTL_LED0_MODE_SHIFT); 1913 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1914 } else if (hw->phy.media_type == e1000_media_type_copper) { 1915 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1916 } 1917 1918 out: 1919 return (ret_val); 1920 } 1921 1922 /* 1923 * e1000_cleanup_led_generic - Set LED config to default operation 1924 * @hw: pointer to the HW structure 1925 * 1926 * Remove the current LED configuration and set the LED configuration 1927 * to the default value, saved from the EEPROM. 1928 */ 1929 s32 1930 e1000_cleanup_led_generic(struct e1000_hw *hw) 1931 { 1932 s32 ret_val = E1000_SUCCESS; 1933 1934 DEBUGFUNC("e1000_cleanup_led_generic"); 1935 1936 if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) { 1937 ret_val = -E1000_ERR_CONFIG; 1938 goto out; 1939 } 1940 1941 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1942 1943 out: 1944 return (ret_val); 1945 } 1946 1947 /* 1948 * e1000_blink_led_generic - Blink LED 1949 * @hw: pointer to the HW structure 1950 * 1951 * Blink the LEDs which are set to be on. 1952 */ 1953 s32 1954 e1000_blink_led_generic(struct e1000_hw *hw) 1955 { 1956 u32 ledctl_blink = 0; 1957 u32 i; 1958 1959 DEBUGFUNC("e1000_blink_led_generic"); 1960 1961 if (hw->phy.media_type == e1000_media_type_fiber) { 1962 /* always blink LED0 for PCI-E fiber */ 1963 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1964 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1965 } else { 1966 /* 1967 * set the blink bit for each LED that's "on" (0x0E) 1968 * in ledctl_mode2 1969 */ 1970 ledctl_blink = hw->mac.ledctl_mode2; 1971 for (i = 0; i < 4; i++) 1972 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1973 E1000_LEDCTL_MODE_LED_ON) 1974 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1975 (i * 8)); 1976 } 1977 1978 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1979 1980 return (E1000_SUCCESS); 1981 } 1982 1983 /* 1984 * e1000_led_on_generic - Turn LED on 1985 * @hw: pointer to the HW structure 1986 * 1987 * Turn LED on. 1988 */ 1989 s32 1990 e1000_led_on_generic(struct e1000_hw *hw) 1991 { 1992 u32 ctrl; 1993 1994 DEBUGFUNC("e1000_led_on_generic"); 1995 1996 switch (hw->phy.media_type) { 1997 case e1000_media_type_fiber: 1998 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1999 ctrl &= ~E1000_CTRL_SWDPIN0; 2000 ctrl |= E1000_CTRL_SWDPIO0; 2001 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2002 break; 2003 case e1000_media_type_copper: 2004 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2005 break; 2006 default: 2007 break; 2008 } 2009 2010 return (E1000_SUCCESS); 2011 } 2012 2013 /* 2014 * e1000_led_off_generic - Turn LED off 2015 * @hw: pointer to the HW structure 2016 * 2017 * Turn LED off. 2018 */ 2019 s32 2020 e1000_led_off_generic(struct e1000_hw *hw) 2021 { 2022 u32 ctrl; 2023 2024 DEBUGFUNC("e1000_led_off_generic"); 2025 2026 switch (hw->phy.media_type) { 2027 case e1000_media_type_fiber: 2028 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2029 ctrl |= E1000_CTRL_SWDPIN0; 2030 ctrl |= E1000_CTRL_SWDPIO0; 2031 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2032 break; 2033 case e1000_media_type_copper: 2034 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2035 break; 2036 default: 2037 break; 2038 } 2039 2040 return (E1000_SUCCESS); 2041 } 2042 2043 /* 2044 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2045 * @hw: pointer to the HW structure 2046 * @no_snoop: bitmap of snoop events 2047 * 2048 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2049 */ 2050 void 2051 e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2052 { 2053 u32 gcr; 2054 2055 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2056 2057 if (hw->bus.type != e1000_bus_type_pci_express) 2058 return; 2059 2060 if (no_snoop) { 2061 gcr = E1000_READ_REG(hw, E1000_GCR); 2062 gcr &= ~(PCIE_NO_SNOOP_ALL); 2063 gcr |= no_snoop; 2064 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2065 } 2066 } 2067 2068 /* 2069 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2070 * @hw: pointer to the HW structure 2071 * 2072 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 2073 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2074 * the master requests to be disabled. 2075 * 2076 * Disables PCI-Express master access and verifies there are no pending 2077 * requests. 2078 */ 2079 s32 2080 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2081 { 2082 u32 ctrl; 2083 s32 timeout = MASTER_DISABLE_TIMEOUT; 2084 s32 ret_val = E1000_SUCCESS; 2085 2086 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2087 2088 if (hw->bus.type != e1000_bus_type_pci_express) 2089 goto out; 2090 2091 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2092 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2093 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2094 2095 while (timeout) { 2096 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2097 E1000_STATUS_GIO_MASTER_ENABLE)) 2098 break; 2099 usec_delay(100); 2100 timeout--; 2101 } 2102 2103 if (!timeout) { 2104 DEBUGOUT("Master requests are pending.\n"); 2105 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2106 goto out; 2107 } 2108 2109 out: 2110 return (ret_val); 2111 } 2112 2113 /* 2114 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2115 * @hw: pointer to the HW structure 2116 * 2117 * Reset the Adaptive Interframe Spacing throttle to default values. 2118 */ 2119 void 2120 e1000_reset_adaptive_generic(struct e1000_hw *hw) 2121 { 2122 struct e1000_mac_info *mac = &hw->mac; 2123 2124 DEBUGFUNC("e1000_reset_adaptive_generic"); 2125 2126 if (!mac->adaptive_ifs) { 2127 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2128 return; 2129 } 2130 2131 mac->current_ifs_val = 0; 2132 mac->ifs_min_val = IFS_MIN; 2133 mac->ifs_max_val = IFS_MAX; 2134 mac->ifs_step_size = IFS_STEP; 2135 mac->ifs_ratio = IFS_RATIO; 2136 2137 mac->in_ifs_mode = false; 2138 E1000_WRITE_REG(hw, E1000_AIT, 0); 2139 } 2140 2141 /* 2142 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2143 * @hw: pointer to the HW structure 2144 * 2145 * Update the Adaptive Interframe Spacing Throttle value based on the 2146 * time between transmitted packets and time between collisions. 2147 */ 2148 void 2149 e1000_update_adaptive_generic(struct e1000_hw *hw) 2150 { 2151 struct e1000_mac_info *mac = &hw->mac; 2152 2153 DEBUGFUNC("e1000_update_adaptive_generic"); 2154 2155 if (!mac->adaptive_ifs) { 2156 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2157 return; 2158 } 2159 2160 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2161 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2162 mac->in_ifs_mode = true; 2163 if (mac->current_ifs_val < mac->ifs_max_val) { 2164 if (!mac->current_ifs_val) 2165 mac->current_ifs_val = mac->ifs_min_val; 2166 else 2167 mac->current_ifs_val += 2168 mac->ifs_step_size; 2169 E1000_WRITE_REG(hw, E1000_AIT, 2170 mac->current_ifs_val); 2171 } 2172 } 2173 } else { 2174 if (mac->in_ifs_mode && 2175 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2176 mac->current_ifs_val = 0; 2177 mac->in_ifs_mode = false; 2178 E1000_WRITE_REG(hw, E1000_AIT, 0); 2179 } 2180 } 2181 } 2182 2183 /* 2184 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2185 * @hw: pointer to the HW structure 2186 * 2187 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2188 * set, which is forced to MDI mode only. 2189 */ 2190 static s32 2191 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2192 { 2193 s32 ret_val = E1000_SUCCESS; 2194 2195 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2196 2197 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2198 DEBUGOUT("Invalid MDI setting detected\n"); 2199 hw->phy.mdix = 1; 2200 ret_val = -E1000_ERR_CONFIG; 2201 goto out; 2202 } 2203 2204 out: 2205 return (ret_val); 2206 } 2207
Indexes created Wed Feb 10 09:32:22 UTC 2010
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