1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 /* 27 * IntelVersion: 1.439 v3-1-10-1_2009-9-18_Release14-6 28 */ 29 #ifndef _E1000_HW_H_ 30 #define _E1000_HW_H_ 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include "e1000_osdep.h" 37 #include "e1000_regs.h" 38 #include "e1000_defines.h" 39 40 struct e1000_hw; 41 42 #define E1000_DEV_ID_82542 0x1000 43 #define E1000_DEV_ID_82543GC_FIBER 0x1001 44 #define E1000_DEV_ID_82543GC_COPPER 0x1004 45 #define E1000_DEV_ID_82544EI_COPPER 0x1008 46 #define E1000_DEV_ID_82544EI_FIBER 0x1009 47 #define E1000_DEV_ID_82544GC_COPPER 0x100C 48 #define E1000_DEV_ID_82544GC_LOM 0x100D 49 #define E1000_DEV_ID_82540EM 0x100E 50 #define E1000_DEV_ID_82540EM_LOM 0x1015 51 #define E1000_DEV_ID_82540EP_LOM 0x1016 52 #define E1000_DEV_ID_82540EP 0x1017 53 #define E1000_DEV_ID_82540EP_LP 0x101E 54 #define E1000_DEV_ID_82545EM_COPPER 0x100F 55 #define E1000_DEV_ID_82545EM_FIBER 0x1011 56 #define E1000_DEV_ID_82545GM_COPPER 0x1026 57 #define E1000_DEV_ID_82545GM_FIBER 0x1027 58 #define E1000_DEV_ID_82545GM_SERDES 0x1028 59 #define E1000_DEV_ID_82546EB_COPPER 0x1010 60 #define E1000_DEV_ID_82546EB_FIBER 0x1012 61 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 62 #define E1000_DEV_ID_82546GB_COPPER 0x1079 63 #define E1000_DEV_ID_82546GB_FIBER 0x107A 64 #define E1000_DEV_ID_82546GB_SERDES 0x107B 65 #define E1000_DEV_ID_82546GB_PCIE 0x108A 66 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 67 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 68 #define E1000_DEV_ID_82541EI 0x1013 69 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 70 #define E1000_DEV_ID_82541ER_LOM 0x1014 71 #define E1000_DEV_ID_82541ER 0x1078 72 #define E1000_DEV_ID_82541GI 0x1076 73 #define E1000_DEV_ID_82541GI_LF 0x107C 74 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 75 #define E1000_DEV_ID_82547EI 0x1019 76 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 77 #define E1000_DEV_ID_82547GI 0x1075 78 #define E1000_DEV_ID_82571EB_COPPER 0x105E 79 #define E1000_DEV_ID_82571EB_FIBER 0x105F 80 #define E1000_DEV_ID_82571EB_SERDES 0x1060 81 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 82 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 83 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 84 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 85 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 86 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 87 #define E1000_DEV_ID_82572EI_COPPER 0x107D 88 #define E1000_DEV_ID_82572EI_FIBER 0x107E 89 #define E1000_DEV_ID_82572EI_SERDES 0x107F 90 #define E1000_DEV_ID_82572EI 0x10B9 91 #define E1000_DEV_ID_82573E 0x108B 92 #define E1000_DEV_ID_82573E_IAMT 0x108C 93 #define E1000_DEV_ID_82573L 0x109A 94 #define E1000_DEV_ID_82574L 0x10D3 95 #define E1000_DEV_ID_82574LA 0x10F6 96 #define E1000_DEV_ID_82583V 0x150C 97 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 98 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 99 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 101 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 102 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 103 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 104 #define E1000_DEV_ID_ICH8_IFE 0x104C 105 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 106 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 107 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 108 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 109 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 110 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 111 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 112 #define E1000_DEV_ID_ICH9_BM 0x10E5 113 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 114 #define E1000_DEV_ID_ICH9_IFE 0x10C0 115 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 116 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 117 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 118 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 119 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 120 #define E1000_DEV_ID_ICH10_HANKSVILLE 0xF0FE 121 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 122 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 123 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 124 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 125 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 126 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 127 128 #define E1000_REVISION_0 0 129 #define E1000_REVISION_1 1 130 #define E1000_REVISION_2 2 131 #define E1000_REVISION_3 3 132 #define E1000_REVISION_4 4 133 134 #define E1000_FUNC_0 0 135 #define E1000_FUNC_1 1 136 137 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 138 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 139 140 /* Maximum size of the MTA register table in all supported adapters */ 141 #define MAX_MTA_REG 128 142 143 enum e1000_mac_type { 144 e1000_undefined = 0, 145 e1000_82542, 146 e1000_82543, 147 e1000_82544, 148 e1000_82540, 149 e1000_82545, 150 e1000_82545_rev_3, 151 e1000_82546, 152 e1000_82546_rev_3, 153 e1000_82541, 154 e1000_82541_rev_2, 155 e1000_82547, 156 e1000_82547_rev_2, 157 e1000_82571, 158 e1000_82572, 159 e1000_82573, 160 e1000_82574, 161 e1000_82583, 162 e1000_80003es2lan, 163 e1000_ich8lan, 164 e1000_ich9lan, 165 e1000_ich10lan, 166 e1000_pchlan, 167 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 168 }; 169 170 enum e1000_media_type { 171 e1000_media_type_unknown = 0, 172 e1000_media_type_copper = 1, 173 e1000_media_type_fiber = 2, 174 e1000_media_type_internal_serdes = 3, 175 e1000_num_media_types 176 }; 177 178 enum e1000_nvm_type { 179 e1000_nvm_unknown = 0, 180 e1000_nvm_none, 181 e1000_nvm_eeprom_spi, 182 e1000_nvm_eeprom_microwire, 183 e1000_nvm_flash_hw, 184 e1000_nvm_flash_sw 185 }; 186 187 enum e1000_nvm_override { 188 e1000_nvm_override_none = 0, 189 e1000_nvm_override_spi_small, 190 e1000_nvm_override_spi_large, 191 e1000_nvm_override_microwire_small, 192 e1000_nvm_override_microwire_large 193 }; 194 195 enum e1000_phy_type { 196 e1000_phy_unknown = 0, 197 e1000_phy_none, 198 e1000_phy_m88, 199 e1000_phy_igp, 200 e1000_phy_igp_2, 201 e1000_phy_gg82563, 202 e1000_phy_igp_3, 203 e1000_phy_ife, 204 e1000_phy_bm, 205 e1000_phy_82578, 206 e1000_phy_82577, 207 }; 208 209 enum e1000_bus_type { 210 e1000_bus_type_unknown = 0, 211 e1000_bus_type_pci, 212 e1000_bus_type_pcix, 213 e1000_bus_type_pci_express, 214 e1000_bus_type_reserved 215 }; 216 217 enum e1000_bus_speed { 218 e1000_bus_speed_unknown = 0, 219 e1000_bus_speed_33, 220 e1000_bus_speed_66, 221 e1000_bus_speed_100, 222 e1000_bus_speed_120, 223 e1000_bus_speed_133, 224 e1000_bus_speed_2500, 225 e1000_bus_speed_5000, 226 e1000_bus_speed_reserved 227 }; 228 229 enum e1000_bus_width { 230 e1000_bus_width_unknown = 0, 231 e1000_bus_width_pcie_x1, 232 e1000_bus_width_pcie_x2, 233 e1000_bus_width_pcie_x4 = 4, 234 e1000_bus_width_pcie_x8 = 8, 235 e1000_bus_width_32, 236 e1000_bus_width_64, 237 e1000_bus_width_reserved 238 }; 239 240 enum e1000_1000t_rx_status { 241 e1000_1000t_rx_status_not_ok = 0, 242 e1000_1000t_rx_status_ok, 243 e1000_1000t_rx_status_undefined = 0xFF 244 }; 245 246 enum e1000_rev_polarity { 247 e1000_rev_polarity_normal = 0, 248 e1000_rev_polarity_reversed, 249 e1000_rev_polarity_undefined = 0xFF 250 }; 251 252 enum e1000_fc_mode { 253 e1000_fc_none = 0, 254 e1000_fc_rx_pause, 255 e1000_fc_tx_pause, 256 e1000_fc_full, 257 e1000_fc_default = 0xFF 258 }; 259 260 enum e1000_ffe_config { 261 e1000_ffe_config_enabled = 0, 262 e1000_ffe_config_active, 263 e1000_ffe_config_blocked 264 }; 265 266 enum e1000_dsp_config { 267 e1000_dsp_config_disabled = 0, 268 e1000_dsp_config_enabled, 269 e1000_dsp_config_activated, 270 e1000_dsp_config_undefined = 0xFF 271 }; 272 273 enum e1000_ms_type { 274 e1000_ms_hw_default = 0, 275 e1000_ms_force_master, 276 e1000_ms_force_slave, 277 e1000_ms_auto 278 }; 279 280 enum e1000_smart_speed { 281 e1000_smart_speed_default = 0, 282 e1000_smart_speed_on, 283 e1000_smart_speed_off 284 }; 285 286 enum e1000_serdes_link_state { 287 e1000_serdes_link_down = 0, 288 e1000_serdes_link_autoneg_progress, 289 e1000_serdes_link_autoneg_complete, 290 e1000_serdes_link_forced_up 291 }; 292 293 /* Receive Descriptor */ 294 struct e1000_rx_desc { 295 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 296 __le16 length; /* Length of data DMAed into data buffer */ 297 __le16 csum; /* Packet checksum */ 298 u8 status; /* Descriptor status */ 299 u8 errors; /* Descriptor Errors */ 300 __le16 special; 301 }; 302 303 /* Receive Descriptor - Extended */ 304 union e1000_rx_desc_extended { 305 struct { 306 __le64 buffer_addr; 307 __le64 reserved; 308 } read; 309 struct { 310 struct { 311 __le32 mrq; /* Multiple Rx Queues */ 312 union { 313 __le32 rss; /* RSS Hash */ 314 struct { 315 __le16 ip_id; /* IP id */ 316 __le16 csum; /* Packet Checksum */ 317 } csum_ip; 318 } hi_dword; 319 } lower; 320 struct { 321 __le32 status_error; /* ext status/error */ 322 __le16 length; 323 __le16 vlan; /* VLAN tag */ 324 } upper; 325 } wb; /* writeback */ 326 }; 327 328 #define MAX_PS_BUFFERS 4 329 /* Receive Descriptor - Packet Split */ 330 union e1000_rx_desc_packet_split { 331 struct { 332 /* one buffer for protocol header(s), three data buffers */ 333 __le64 buffer_addr[MAX_PS_BUFFERS]; 334 } read; 335 struct { 336 struct { 337 __le32 mrq; /* Multiple Rx Queues */ 338 union { 339 __le32 rss; /* RSS Hash */ 340 struct { 341 __le16 ip_id; /* IP id */ 342 __le16 csum; /* Packet Checksum */ 343 } csum_ip; 344 } hi_dword; 345 } lower; 346 struct { 347 __le32 status_error; /* ext status/error */ 348 __le16 length0; /* length of buffer 0 */ 349 __le16 vlan; /* VLAN tag */ 350 } middle; 351 struct { 352 __le16 header_status; 353 __le16 length[3]; /* length of buffers 1-3 */ 354 } upper; 355 __le64 reserved; 356 } wb; /* writeback */ 357 }; 358 359 /* Transmit Descriptor */ 360 struct e1000_tx_desc { 361 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 362 union { 363 __le32 data; 364 struct { 365 __le16 length; /* Data buffer length */ 366 u8 cso; /* Checksum offset */ 367 u8 cmd; /* Descriptor control */ 368 } flags; 369 } lower; 370 union { 371 __le32 data; 372 struct { 373 u8 status; /* Descriptor status */ 374 u8 css; /* Checksum start */ 375 __le16 special; 376 } fields; 377 } upper; 378 }; 379 380 /* Offload Context Descriptor */ 381 struct e1000_context_desc { 382 union { 383 __le32 ip_config; 384 struct { 385 u8 ipcss; /* IP checksum start */ 386 u8 ipcso; /* IP checksum offset */ 387 __le16 ipcse; /* IP checksum end */ 388 } ip_fields; 389 } lower_setup; 390 union { 391 __le32 tcp_config; 392 struct { 393 u8 tucss; /* TCP checksum start */ 394 u8 tucso; /* TCP checksum offset */ 395 __le16 tucse; /* TCP checksum end */ 396 } tcp_fields; 397 } upper_setup; 398 __le32 cmd_and_length; 399 union { 400 __le32 data; 401 struct { 402 u8 status; /* Descriptor status */ 403 u8 hdr_len; /* Header length */ 404 __le16 mss; /* Maximum segment size */ 405 } fields; 406 } tcp_seg_setup; 407 }; 408 409 /* Offload data descriptor */ 410 struct e1000_data_desc { 411 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 412 union { 413 __le32 data; 414 struct { 415 __le16 length; /* Data buffer length */ 416 u8 typ_len_ext; 417 u8 cmd; 418 } flags; 419 } lower; 420 union { 421 __le32 data; 422 struct { 423 u8 status; /* Descriptor status */ 424 u8 popts; /* Packet Options */ 425 __le16 special; 426 } fields; 427 } upper; 428 }; 429 430 /* Statistics counters collected by the MAC */ 431 struct e1000_hw_stats { 432 u64 crcerrs; 433 u64 algnerrc; 434 u64 symerrs; 435 u64 rxerrc; 436 u64 mpc; 437 u64 scc; 438 u64 ecol; 439 u64 mcc; 440 u64 latecol; 441 u64 colc; 442 u64 dc; 443 u64 tncrs; 444 u64 sec; 445 u64 cexterr; 446 u64 rlec; 447 u64 xonrxc; 448 u64 xontxc; 449 u64 xoffrxc; 450 u64 xofftxc; 451 u64 fcruc; 452 u64 prc64; 453 u64 prc127; 454 u64 prc255; 455 u64 prc511; 456 u64 prc1023; 457 u64 prc1522; 458 u64 gprc; 459 u64 bprc; 460 u64 mprc; 461 u64 gptc; 462 u64 gorc; 463 u64 gotc; 464 u64 rnbc; 465 u64 ruc; 466 u64 rfc; 467 u64 roc; 468 u64 rjc; 469 u64 mgprc; 470 u64 mgpdc; 471 u64 mgptc; 472 u64 tor; 473 u64 tot; 474 u64 tpr; 475 u64 tpt; 476 u64 ptc64; 477 u64 ptc127; 478 u64 ptc255; 479 u64 ptc511; 480 u64 ptc1023; 481 u64 ptc1522; 482 u64 mptc; 483 u64 bptc; 484 u64 tsctc; 485 u64 tsctfc; 486 u64 iac; 487 u64 icrxptc; 488 u64 icrxatc; 489 u64 ictxptc; 490 u64 ictxatc; 491 u64 ictxqec; 492 u64 ictxqmtc; 493 u64 icrxdmtc; 494 u64 icrxoc; 495 u64 cbtmpc; 496 u64 htdpmc; 497 u64 cbrdpc; 498 u64 cbrmpc; 499 u64 rpthc; 500 u64 hgptc; 501 u64 htcbdpc; 502 u64 hgorc; 503 u64 hgotc; 504 u64 lenerrs; 505 u64 scvpc; 506 u64 hrmpc; 507 u64 doosync; 508 }; 509 510 struct e1000_phy_stats { 511 u32 idle_errors; 512 u32 receive_errors; 513 }; 514 515 struct e1000_host_mng_dhcp_cookie { 516 u32 signature; 517 u8 status; 518 u8 reserved0; 519 u16 vlan_id; 520 u32 reserved1; 521 u16 reserved2; 522 u8 reserved3; 523 u8 checksum; 524 }; 525 526 /* Host Interface "Rev 1" */ 527 struct e1000_host_command_header { 528 u8 command_id; 529 u8 command_length; 530 u8 command_options; 531 u8 checksum; 532 }; 533 534 #define E1000_HI_MAX_DATA_LENGTH 252 535 struct e1000_host_command_info { 536 struct e1000_host_command_header command_header; 537 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 538 }; 539 540 /* Host Interface "Rev 2" */ 541 struct e1000_host_mng_command_header { 542 u8 command_id; 543 u8 checksum; 544 u16 reserved1; 545 u16 reserved2; 546 u16 command_length; 547 }; 548 549 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 550 struct e1000_host_mng_command_info { 551 struct e1000_host_mng_command_header command_header; 552 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 553 }; 554 555 #include "e1000_mac.h" 556 #include "e1000_phy.h" 557 #include "e1000_nvm.h" 558 #include "e1000_manage.h" 559 560 struct e1000_mac_operations { 561 /* Function pointers for the MAC. */ 562 s32 (*init_params)(struct e1000_hw *); 563 s32 (*id_led_init)(struct e1000_hw *); 564 s32 (*blink_led)(struct e1000_hw *); 565 s32 (*check_for_link)(struct e1000_hw *); 566 bool (*check_mng_mode)(struct e1000_hw *hw); 567 s32 (*cleanup_led)(struct e1000_hw *); 568 void (*clear_hw_cntrs)(struct e1000_hw *); 569 void (*clear_vfta)(struct e1000_hw *); 570 s32 (*get_bus_info)(struct e1000_hw *); 571 void (*set_lan_id)(struct e1000_hw *); 572 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 573 s32 (*led_on)(struct e1000_hw *); 574 s32 (*led_off)(struct e1000_hw *); 575 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 576 s32 (*reset_hw)(struct e1000_hw *); 577 s32 (*init_hw)(struct e1000_hw *); 578 s32 (*setup_link)(struct e1000_hw *); 579 s32 (*setup_physical_interface)(struct e1000_hw *); 580 s32 (*setup_led)(struct e1000_hw *); 581 void (*write_vfta)(struct e1000_hw *, u32, u32); 582 void (*mta_set)(struct e1000_hw *, u32); 583 void (*config_collision_dist)(struct e1000_hw *); 584 void (*rar_set)(struct e1000_hw *, u8 *, u32); 585 s32 (*read_mac_addr)(struct e1000_hw *); 586 s32 (*validate_mdi_setting)(struct e1000_hw *); 587 s32 (*mng_host_if_write)(struct e1000_hw *, u8 *, u16, u16, u8 *); 588 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 589 struct e1000_host_mng_command_header *); 590 s32 (*mng_enable_host_if)(struct e1000_hw *); 591 s32 (*wait_autoneg)(struct e1000_hw *); 592 }; 593 594 struct e1000_phy_operations { 595 s32 (*init_params)(struct e1000_hw *); 596 s32 (*acquire)(struct e1000_hw *); 597 s32 (*cfg_on_link_up)(struct e1000_hw *); 598 s32 (*check_polarity)(struct e1000_hw *); 599 s32 (*check_reset_block)(struct e1000_hw *); 600 s32 (*commit)(struct e1000_hw *); 601 s32 (*force_speed_duplex)(struct e1000_hw *); 602 s32 (*get_cfg_done)(struct e1000_hw *hw); 603 s32 (*get_cable_length)(struct e1000_hw *); 604 s32 (*get_info)(struct e1000_hw *); 605 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 606 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 607 void (*release)(struct e1000_hw *); 608 s32 (*reset)(struct e1000_hw *); 609 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 610 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 611 s32 (*write_reg)(struct e1000_hw *, u32, u16); 612 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 613 void (*power_up)(struct e1000_hw *); 614 void (*power_down)(struct e1000_hw *); 615 }; 616 617 struct e1000_nvm_operations { 618 s32 (*init_params)(struct e1000_hw *); 619 s32 (*acquire)(struct e1000_hw *); 620 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 621 void (*release)(struct e1000_hw *); 622 void (*reload)(struct e1000_hw *); 623 s32 (*update)(struct e1000_hw *); 624 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 625 s32 (*validate)(struct e1000_hw *); 626 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 627 }; 628 629 struct e1000_mac_info { 630 struct e1000_mac_operations ops; 631 u8 addr[6]; 632 u8 perm_addr[6]; 633 634 enum e1000_mac_type type; 635 636 u32 collision_delta; 637 u32 ledctl_default; 638 u32 ledctl_mode1; 639 u32 ledctl_mode2; 640 u32 mc_filter_type; 641 u32 tx_packet_delta; 642 u32 txcw; 643 644 u16 current_ifs_val; 645 u16 ifs_max_val; 646 u16 ifs_min_val; 647 u16 ifs_ratio; 648 u16 ifs_step_size; 649 u16 mta_reg_count; 650 u32 mta_shadow[MAX_MTA_REG]; 651 u16 rar_entry_count; 652 653 u8 forced_speed_duplex; 654 655 bool adaptive_ifs; 656 bool arc_subsystem_valid; 657 bool asf_firmware_present; 658 bool autoneg; 659 bool autoneg_failed; 660 bool get_link_status; 661 bool in_ifs_mode; 662 bool report_tx_early; 663 enum e1000_serdes_link_state serdes_link_state; 664 bool serdes_has_link; 665 bool tx_pkt_filtering; 666 }; 667 668 struct e1000_phy_info { 669 struct e1000_phy_operations ops; 670 enum e1000_phy_type type; 671 672 enum e1000_1000t_rx_status local_rx; 673 enum e1000_1000t_rx_status remote_rx; 674 enum e1000_ms_type ms_type; 675 enum e1000_ms_type original_ms_type; 676 enum e1000_rev_polarity cable_polarity; 677 enum e1000_smart_speed smart_speed; 678 679 u32 addr; 680 u32 id; 681 u32 reset_delay_us; /* in usec */ 682 u32 revision; 683 684 enum e1000_media_type media_type; 685 686 u16 autoneg_advertised; 687 u16 autoneg_mask; 688 u16 cable_length; 689 u16 max_cable_length; 690 u16 min_cable_length; 691 692 u8 mdix; 693 694 bool disable_polarity_correction; 695 bool is_mdix; 696 bool polarity_correction; 697 bool reset_disable; 698 bool speed_downgraded; 699 bool autoneg_wait_to_complete; 700 }; 701 702 struct e1000_nvm_info { 703 struct e1000_nvm_operations ops; 704 enum e1000_nvm_type type; 705 enum e1000_nvm_override override; 706 707 u32 flash_bank_size; 708 u32 flash_base_addr; 709 710 u16 word_size; 711 u16 delay_usec; 712 u16 address_bits; 713 u16 opcode_bits; 714 u16 page_size; 715 }; 716 717 struct e1000_bus_info { 718 enum e1000_bus_type type; 719 enum e1000_bus_speed speed; 720 enum e1000_bus_width width; 721 722 u16 func; 723 u16 pci_cmd_word; 724 }; 725 726 struct e1000_fc_info { 727 u32 high_water; /* Flow control high-water mark */ 728 u32 low_water; /* Flow control low-water mark */ 729 u16 pause_time; /* Flow control pause timer */ 730 bool send_xon; /* Flow control send XON */ 731 bool strict_ieee; /* Strict IEEE mode */ 732 enum e1000_fc_mode current_mode; /* FC mode in effect */ 733 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 734 }; 735 736 struct e1000_dev_spec_82541 { 737 enum e1000_dsp_config dsp_config; 738 enum e1000_ffe_config ffe_config; 739 u32 tx_fifo_head; 740 u32 tx_fifo_start; 741 u32 tx_fifo_size; 742 u16 dsp_reset_counter; 743 u16 spd_default; 744 bool phy_init_script; 745 bool ttl_workaround; 746 }; 747 748 struct e1000_dev_spec_82542 { 749 bool dma_fairness; 750 }; 751 752 struct e1000_dev_spec_82543 { 753 u32 tbi_compatibility; 754 bool dma_fairness; 755 bool init_phy_disabled; 756 }; 757 758 struct e1000_dev_spec_82571 { 759 bool laa_is_present; 760 u32 smb_counter; 761 }; 762 763 struct e1000_dev_spec_80003es2lan { 764 bool mdic_wa_enable; 765 }; 766 767 struct e1000_shadow_ram { 768 u16 value; 769 bool modified; 770 }; 771 772 #define E1000_SHADOW_RAM_WORDS 2048 773 774 struct e1000_dev_spec_ich8lan { 775 bool kmrn_lock_loss_workaround_enabled; 776 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 777 E1000_MUTEX nvm_mutex; 778 E1000_MUTEX swflag_mutex; 779 bool nvm_k1_enabled; 780 bool nvm_lcd_config_enabled; 781 }; 782 783 struct e1000_hw { 784 void *back; 785 786 u8 *hw_addr; 787 u8 *flash_address; 788 unsigned long io_base; 789 790 struct e1000_mac_info mac; 791 struct e1000_fc_info fc; 792 struct e1000_phy_info phy; 793 struct e1000_nvm_info nvm; 794 struct e1000_bus_info bus; 795 struct e1000_host_mng_dhcp_cookie mng_cookie; 796 797 union { 798 struct e1000_dev_spec_82541 _82541; 799 struct e1000_dev_spec_82542 _82542; 800 struct e1000_dev_spec_82543 _82543; 801 struct e1000_dev_spec_82571 _82571; 802 struct e1000_dev_spec_80003es2lan _80003es2lan; 803 struct e1000_dev_spec_ich8lan ich8lan; 804 } dev_spec; 805 806 u16 device_id; 807 u16 subsystem_vendor_id; 808 u16 subsystem_device_id; 809 u16 vendor_id; 810 811 u8 revision_id; 812 }; 813 814 #include "e1000_82541.h" 815 #include "e1000_82543.h" 816 #include "e1000_82571.h" 817 #include "e1000_80003es2lan.h" 818 #include "e1000_ich8lan.h" 819 820 /* These functions must be implemented by drivers */ 821 void e1000_pci_clear_mwi(struct e1000_hw *hw); 822 void e1000_pci_set_mwi(struct e1000_hw *hw); 823 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 824 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 825 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 826 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 827 828 #ifdef __cplusplus 829 } 830 #endif 831 832 #endif /* _E1000_HW_H_ */ 833
Indexes created Wed Feb 10 08:45:31 UTC 2010
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