1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 /* 27 * IntelVersion: 1.113 v3-1-10-1_2009-9-18_Release14-6 28 */ 29 30 /* 31 * 82571EB Gigabit Ethernet Controller 32 * 82571EB Gigabit Ethernet Controller (Copper) 33 * 82571EB Gigabit Ethernet Controller (Fiber) 34 * 82571EB Dual Port Gigabit Mezzanine Adapter 35 * 82571EB Quad Port Gigabit Mezzanine Adapter 36 * 82571PT Gigabit PT Quad Port Server ExpressModule 37 * 82572EI Gigabit Ethernet Controller (Copper) 38 * 82572EI Gigabit Ethernet Controller (Fiber) 39 * 82572EI Gigabit Ethernet Controller 40 * 82573V Gigabit Ethernet Controller (Copper) 41 * 82573E Gigabit Ethernet Controller (Copper) 42 * 82573L Gigabit Ethernet Controller 43 * 82574L Gigabit Network Connection 44 * 82583V Gigabit Network Connection 45 */ 46 47 #include "e1000_api.h" 48 49 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 50 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 51 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 52 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 53 static void e1000_release_nvm_82571(struct e1000_hw *hw); 54 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 55 u16 words, u16 *data); 56 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 57 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 58 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 59 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 60 bool active); 61 static s32 e1000_reset_hw_82571(struct e1000_hw *hw); 62 static s32 e1000_init_hw_82571(struct e1000_hw *hw); 63 static void e1000_clear_vfta_82571(struct e1000_hw *hw); 64 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 65 static s32 e1000_led_on_82574(struct e1000_hw *hw); 66 static s32 e1000_setup_link_82571(struct e1000_hw *hw); 67 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 68 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 69 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 70 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 71 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 72 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 73 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 74 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 75 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 76 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 77 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 78 u16 words, u16 *data); 79 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 80 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 81 82 /* 83 * e1000_init_phy_params_82571 - Init PHY func ptrs. 84 * @hw: pointer to the HW structure 85 */ 86 static s32 87 e1000_init_phy_params_82571(struct e1000_hw *hw) 88 { 89 struct e1000_phy_info *phy = &hw->phy; 90 s32 ret_val = E1000_SUCCESS; 91 92 DEBUGFUNC("e1000_init_phy_params_82571"); 93 94 if (hw->phy.media_type != e1000_media_type_copper) { 95 phy->type = e1000_phy_none; 96 goto out; 97 } 98 99 phy->addr = 1; 100 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 101 phy->reset_delay_us = 100; 102 103 phy->ops.acquire = e1000_get_hw_semaphore_82571; 104 phy->ops.check_polarity = e1000_check_polarity_igp; 105 phy->ops.check_reset_block = e1000_check_reset_block_generic; 106 phy->ops.release = e1000_put_hw_semaphore_82571; 107 phy->ops.reset = e1000_phy_hw_reset_generic; 108 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 109 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 110 phy->ops.power_up = e1000_power_up_phy_copper; 111 phy->ops.power_down = e1000_power_down_phy_copper_82571; 112 113 switch (hw->mac.type) { 114 case e1000_82571: 115 case e1000_82572: 116 phy->type = e1000_phy_igp_2; 117 phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 118 phy->ops.get_info = e1000_get_phy_info_igp; 119 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 120 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 121 phy->ops.read_reg = e1000_read_phy_reg_igp; 122 phy->ops.write_reg = e1000_write_phy_reg_igp; 123 124 /* This uses above function pointers */ 125 ret_val = e1000_get_phy_id_82571(hw); 126 127 /* Verify PHY ID */ 128 if (phy->id != IGP01E1000_I_PHY_ID) { 129 ret_val = -E1000_ERR_PHY; 130 goto out; 131 } 132 break; 133 case e1000_82573: 134 phy->type = e1000_phy_m88; 135 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 136 phy->ops.get_info = e1000_get_phy_info_m88; 137 phy->ops.commit = e1000_phy_sw_reset_generic; 138 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 139 phy->ops.get_cable_length = e1000_get_cable_length_m88; 140 phy->ops.read_reg = e1000_read_phy_reg_m88; 141 phy->ops.write_reg = e1000_write_phy_reg_m88; 142 143 /* This uses above function pointers */ 144 ret_val = e1000_get_phy_id_82571(hw); 145 146 /* Verify PHY ID */ 147 if (phy->id != M88E1111_I_PHY_ID) { 148 ret_val = -E1000_ERR_PHY; 149 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 150 goto out; 151 } 152 break; 153 case e1000_82574: 154 case e1000_82583: 155 phy->type = e1000_phy_bm; 156 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 157 phy->ops.get_info = e1000_get_phy_info_m88; 158 phy->ops.commit = e1000_phy_sw_reset_generic; 159 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 160 phy->ops.get_cable_length = e1000_get_cable_length_m88; 161 phy->ops.read_reg = e1000_read_phy_reg_bm2; 162 phy->ops.write_reg = e1000_write_phy_reg_bm2; 163 164 /* This uses above function pointers */ 165 ret_val = e1000_get_phy_id_82571(hw); 166 /* Verify PHY ID */ 167 if (phy->id != BME1000_E_PHY_ID_R2) { 168 ret_val = -E1000_ERR_PHY; 169 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 170 goto out; 171 } 172 break; 173 default: 174 ret_val = -E1000_ERR_PHY; 175 goto out; 176 } 177 178 out: 179 return (ret_val); 180 } 181 182 /* 183 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 184 * @hw: pointer to the HW structure 185 */ 186 static s32 187 e1000_init_nvm_params_82571(struct e1000_hw *hw) 188 { 189 struct e1000_nvm_info *nvm = &hw->nvm; 190 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 191 u16 size; 192 193 DEBUGFUNC("e1000_init_nvm_params_82571"); 194 195 nvm->opcode_bits = 8; 196 nvm->delay_usec = 1; 197 switch (nvm->override) { 198 case e1000_nvm_override_spi_large: 199 nvm->page_size = 32; 200 nvm->address_bits = 16; 201 break; 202 case e1000_nvm_override_spi_small: 203 nvm->page_size = 8; 204 nvm->address_bits = 8; 205 break; 206 default: 207 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 208 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 209 break; 210 } 211 212 switch (hw->mac.type) { 213 case e1000_82573: 214 case e1000_82574: 215 case e1000_82583: 216 if (((eecd >> 15) & 0x3) == 0x3) { 217 nvm->type = e1000_nvm_flash_hw; 218 nvm->word_size = 2048; 219 /* 220 * Autonomous Flash update bit must be cleared due 221 * to Flash update issue. 222 */ 223 eecd &= ~E1000_EECD_AUPDEN; 224 E1000_WRITE_REG(hw, E1000_EECD, eecd); 225 break; 226 } 227 /* Fall Through */ 228 default: 229 nvm->type = e1000_nvm_eeprom_spi; 230 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 231 E1000_EECD_SIZE_EX_SHIFT); 232 /* 233 * Added to a constant, "size" becomes the left-shift value 234 * for setting word_size. 235 */ 236 size += NVM_WORD_SIZE_BASE_SHIFT; 237 238 /* EEPROM access above 16k is unsupported */ 239 if (size > 14) 240 size = 14; 241 nvm->word_size = 1 << size; 242 break; 243 } 244 245 /* Function Pointers */ 246 nvm->ops.acquire = e1000_acquire_nvm_82571; 247 nvm->ops.read = e1000_read_nvm_eerd; 248 nvm->ops.release = e1000_release_nvm_82571; 249 nvm->ops.update = e1000_update_nvm_checksum_82571; 250 nvm->ops.validate = e1000_validate_nvm_checksum_82571; 251 nvm->ops.valid_led_default = e1000_valid_led_default_82571; 252 nvm->ops.write = e1000_write_nvm_82571; 253 254 return (E1000_SUCCESS); 255 } 256 257 /* 258 * e1000_init_mac_params_82571 - Init MAC func ptrs. 259 * @hw: pointer to the HW structure 260 */ 261 static s32 262 e1000_init_mac_params_82571(struct e1000_hw *hw) 263 { 264 struct e1000_mac_info *mac = &hw->mac; 265 s32 ret_val = E1000_SUCCESS; 266 u32 swsm = 0; 267 u32 swsm2 = 0; 268 bool force_clear_smbi = false; 269 270 DEBUGFUNC("e1000_init_mac_params_82571"); 271 272 /* Set media type */ 273 switch (hw->device_id) { 274 case E1000_DEV_ID_82571EB_FIBER: 275 case E1000_DEV_ID_82572EI_FIBER: 276 case E1000_DEV_ID_82571EB_QUAD_FIBER: 277 hw->phy.media_type = e1000_media_type_fiber; 278 break; 279 case E1000_DEV_ID_82571EB_SERDES: 280 case E1000_DEV_ID_82571EB_SERDES_DUAL: 281 case E1000_DEV_ID_82571EB_SERDES_QUAD: 282 case E1000_DEV_ID_82572EI_SERDES: 283 hw->phy.media_type = e1000_media_type_internal_serdes; 284 break; 285 default: 286 hw->phy.media_type = e1000_media_type_copper; 287 break; 288 } 289 290 /* Set mta register count */ 291 mac->mta_reg_count = 128; 292 /* Set rar entry count */ 293 mac->rar_entry_count = E1000_RAR_ENTRIES; 294 /* Set if part includes ASF firmware */ 295 mac->asf_firmware_present = true; 296 /* Set if manageability features are enabled. */ 297 mac->arc_subsystem_valid = 298 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 299 ? true : false; 300 301 /* Function pointers */ 302 303 /* bus type/speed/width */ 304 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 305 /* function id */ 306 switch (hw->mac.type) { 307 case e1000_82573: 308 case e1000_82574: 309 case e1000_82583: 310 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 311 break; 312 default: 313 break; 314 } 315 /* reset */ 316 mac->ops.reset_hw = e1000_reset_hw_82571; 317 /* hw initialization */ 318 mac->ops.init_hw = e1000_init_hw_82571; 319 /* link setup */ 320 mac->ops.setup_link = e1000_setup_link_82571; 321 /* physical interface link setup */ 322 mac->ops.setup_physical_interface = 323 (hw->phy.media_type == e1000_media_type_copper) 324 ? e1000_setup_copper_link_82571 325 : e1000_setup_fiber_serdes_link_82571; 326 /* check for link */ 327 switch (hw->phy.media_type) { 328 case e1000_media_type_copper: 329 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 330 break; 331 case e1000_media_type_fiber: 332 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 333 break; 334 case e1000_media_type_internal_serdes: 335 mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 336 break; 337 default: 338 ret_val = -E1000_ERR_CONFIG; 339 goto out; 340 } 341 /* check management mode */ 342 switch (hw->mac.type) { 343 case e1000_82574: 344 case e1000_82583: 345 mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 346 break; 347 default: 348 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 349 break; 350 } 351 /* multicast address update */ 352 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 353 /* writing VFTA */ 354 mac->ops.write_vfta = e1000_write_vfta_generic; 355 /* clearing VFTA */ 356 mac->ops.clear_vfta = e1000_clear_vfta_82571; 357 /* setting MTA */ 358 mac->ops.mta_set = e1000_mta_set_generic; 359 /* read mac address */ 360 mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 361 /* ID LED init */ 362 mac->ops.id_led_init = e1000_id_led_init_generic; 363 /* blink LED */ 364 mac->ops.blink_led = e1000_blink_led_generic; 365 /* setup LED */ 366 mac->ops.setup_led = e1000_setup_led_generic; 367 /* cleanup LED */ 368 mac->ops.cleanup_led = e1000_cleanup_led_generic; 369 /* turn on/off LED */ 370 switch (hw->mac.type) { 371 case e1000_82574: 372 case e1000_82583: 373 mac->ops.led_on = e1000_led_on_82574; 374 break; 375 default: 376 mac->ops.led_on = e1000_led_on_generic; 377 break; 378 } 379 mac->ops.led_off = e1000_led_off_generic; 380 /* clear hardware counters */ 381 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 382 /* link info */ 383 mac->ops.get_link_up_info = 384 (hw->phy.media_type == e1000_media_type_copper) 385 ? e1000_get_speed_and_duplex_copper_generic 386 : e1000_get_speed_and_duplex_fiber_serdes_generic; 387 388 /* 389 * Ensure that the inter-port SWSM.SMBI lock bit is clear before 390 * first NVM or PHY acess. This should be done for single-port 391 * devices, and for one port only on dual-port devices so that 392 * for those devices we can still use the SMBI lock to synchronize 393 * inter-port accesses to the PHY & NVM. 394 */ 395 switch (hw->mac.type) { 396 case e1000_82571: 397 case e1000_82572: 398 swsm2 = E1000_READ_REG(hw, E1000_SWSM2); 399 400 if (!(swsm2 & E1000_SWSM2_LOCK)) { 401 /* Only do this for the first interface on this card */ 402 E1000_WRITE_REG(hw, E1000_SWSM2, 403 swsm2 | E1000_SWSM2_LOCK); 404 force_clear_smbi = true; 405 } else 406 force_clear_smbi = false; 407 break; 408 default: 409 force_clear_smbi = true; 410 break; 411 } 412 413 if (force_clear_smbi) { 414 /* Make sure SWSM.SMBI is clear */ 415 swsm = E1000_READ_REG(hw, E1000_SWSM); 416 if (swsm & E1000_SWSM_SMBI) { 417 /* EMPTY */ 418 /* 419 * This bit should not be set on a first interface, and 420 * indicates that the bootagent or EFI code has 421 * improperly left this bit enabled 422 */ 423 DEBUGOUT("Please update your 82571 Bootagent\n"); 424 } 425 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); 426 } 427 428 /* 429 * Initialze device specific counter of SMBI acquisition 430 * timeouts. 431 */ 432 hw->dev_spec._82571.smb_counter = 0; 433 434 out: 435 return (ret_val); 436 } 437 438 /* 439 * e1000_init_function_pointers_82571 - Init func ptrs. 440 * @hw: pointer to the HW structure 441 * 442 * Called to initialize all function pointers and parameters. 443 */ 444 void 445 e1000_init_function_pointers_82571(struct e1000_hw *hw) 446 { 447 DEBUGFUNC("e1000_init_function_pointers_82571"); 448 449 hw->mac.ops.init_params = e1000_init_mac_params_82571; 450 hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 451 hw->phy.ops.init_params = e1000_init_phy_params_82571; 452 } 453 454 /* 455 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 456 * @hw: pointer to the HW structure 457 * 458 * Reads the PHY registers and stores the PHY ID and possibly the PHY 459 * revision in the hardware structure. 460 */ 461 static s32 462 e1000_get_phy_id_82571(struct e1000_hw *hw) 463 { 464 struct e1000_phy_info *phy = &hw->phy; 465 s32 ret_val = E1000_SUCCESS; 466 u16 phy_id = 0; 467 468 DEBUGFUNC("e1000_get_phy_id_82571"); 469 470 switch (hw->mac.type) { 471 case e1000_82571: 472 case e1000_82572: 473 /* 474 * The 82571 firmware may still be configuring the PHY. In 475 * this case, we cannot access the PHY until the configuration 476 * is done. So we explicitly set the PHY ID. 477 */ 478 phy->id = IGP01E1000_I_PHY_ID; 479 break; 480 case e1000_82573: 481 ret_val = e1000_get_phy_id(hw); 482 break; 483 case e1000_82574: 484 case e1000_82583: 485 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 486 if (ret_val) 487 goto out; 488 489 phy->id = (u32)(phy_id << 16); 490 usec_delay(20); 491 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 492 if (ret_val) 493 goto out; 494 495 phy->id |= (u32)(phy_id); 496 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 497 break; 498 default: 499 ret_val = -E1000_ERR_PHY; 500 break; 501 } 502 503 out: 504 return (ret_val); 505 } 506 507 /* 508 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 509 * @hw: pointer to the HW structure 510 * 511 * Acquire the HW semaphore to access the PHY or NVM 512 */ 513 s32 514 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 515 { 516 u32 swsm; 517 s32 ret_val = E1000_SUCCESS; 518 s32 sw_timeout = hw->nvm.word_size + 1; 519 s32 fw_timeout = hw->nvm.word_size + 1; 520 s32 i = 0; 521 522 DEBUGFUNC("e1000_get_hw_semaphore_82571"); 523 524 /* 525 * If we have timedout 3 times on trying to acquire 526 * the inter-port SMBI semaphore, there is old code 527 * operating on the other port, and it is not 528 * releasing SMBI. Modify the number of times that 529 * we try for the semaphore to interwork with this 530 * older code. 531 */ 532 if (hw->dev_spec._82571.smb_counter > 2) 533 sw_timeout = 1; 534 535 /* Get the SW semaphore */ 536 while (i < sw_timeout) { 537 swsm = E1000_READ_REG(hw, E1000_SWSM); 538 if (!(swsm & E1000_SWSM_SMBI)) 539 break; 540 541 usec_delay(50); 542 i++; 543 } 544 545 if (i == sw_timeout) { 546 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 547 hw->dev_spec._82571.smb_counter++; 548 } 549 /* Get the FW semaphore. */ 550 for (i = 0; i < fw_timeout; i++) { 551 swsm = E1000_READ_REG(hw, E1000_SWSM); 552 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 553 554 /* Semaphore acquired if bit latched */ 555 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 556 break; 557 558 usec_delay(50); 559 } 560 561 if (i == fw_timeout) { 562 /* Release semaphores */ 563 e1000_put_hw_semaphore_82571(hw); 564 DEBUGOUT("Driver can't access the NVM\n"); 565 ret_val = -E1000_ERR_NVM; 566 goto out; 567 } 568 569 out: 570 return (ret_val); 571 } 572 573 /* 574 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 575 * @hw: pointer to the HW structure 576 * 577 * Release hardware semaphore used to access the PHY or NVM 578 */ 579 void 580 e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 581 { 582 u32 swsm; 583 584 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 585 586 swsm = E1000_READ_REG(hw, E1000_SWSM); 587 588 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 589 590 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 591 } 592 593 /* 594 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 595 * @hw: pointer to the HW structure 596 * 597 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 598 * Then for non-82573 hardware, set the EEPROM access request bit and wait 599 * for EEPROM access grant bit. If the access grant bit is not set, release 600 * hardware semaphore. 601 */ 602 static s32 603 e1000_acquire_nvm_82571(struct e1000_hw *hw) 604 { 605 s32 ret_val; 606 607 DEBUGFUNC("e1000_acquire_nvm_82571"); 608 609 ret_val = e1000_get_hw_semaphore_82571(hw); 610 if (ret_val) 611 goto out; 612 613 switch (hw->mac.type) { 614 case e1000_82573: 615 case e1000_82574: 616 case e1000_82583: 617 break; 618 default: 619 ret_val = e1000_acquire_nvm_generic(hw); 620 break; 621 } 622 623 if (ret_val) 624 e1000_put_hw_semaphore_82571(hw); 625 626 out: 627 return (ret_val); 628 } 629 630 /* 631 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 632 * @hw: pointer to the HW structure 633 * 634 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 635 */ 636 static void 637 e1000_release_nvm_82571(struct e1000_hw *hw) 638 { 639 DEBUGFUNC("e1000_release_nvm_82571"); 640 641 e1000_release_nvm_generic(hw); 642 e1000_put_hw_semaphore_82571(hw); 643 } 644 645 /* 646 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 647 * @hw: pointer to the HW structure 648 * @offset: offset within the EEPROM to be written to 649 * @words: number of words to write 650 * @data: 16 bit word(s) to be written to the EEPROM 651 * 652 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 653 * 654 * If e1000_update_nvm_checksum is not called after this function, the 655 * EEPROM will most likely contain an invalid checksum. 656 */ 657 static s32 658 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 659 u16 *data) 660 { 661 s32 ret_val = E1000_SUCCESS; 662 663 DEBUGFUNC("e1000_write_nvm_82571"); 664 665 switch (hw->mac.type) { 666 case e1000_82573: 667 case e1000_82574: 668 case e1000_82583: 669 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 670 break; 671 case e1000_82571: 672 case e1000_82572: 673 ret_val = e1000_write_nvm_spi(hw, offset, words, data); 674 break; 675 default: 676 ret_val = -E1000_ERR_NVM; 677 break; 678 } 679 680 return (ret_val); 681 } 682 683 /* 684 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 685 * @hw: pointer to the HW structure 686 * 687 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 688 * up to the checksum. Then calculates the EEPROM checksum and writes the 689 * value to the EEPROM. 690 */ 691 static s32 692 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 693 { 694 u32 eecd; 695 s32 ret_val; 696 u16 i; 697 698 DEBUGFUNC("e1000_update_nvm_checksum_82571"); 699 700 ret_val = e1000_update_nvm_checksum_generic(hw); 701 if (ret_val) 702 goto out; 703 704 /* 705 * If our nvm is an EEPROM, then we're done otherwise, commit the 706 * checksum to the flash NVM. 707 */ 708 if (hw->nvm.type != e1000_nvm_flash_hw) 709 goto out; 710 711 /* Check for pending operations. */ 712 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 713 msec_delay(1); 714 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 715 break; 716 } 717 718 if (i == E1000_FLASH_UPDATES) { 719 ret_val = -E1000_ERR_NVM; 720 goto out; 721 } 722 723 /* Reset the firmware if using STM opcode. */ 724 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 725 /* 726 * The enabling of and the actual reset must be done in two 727 * write cycles. 728 */ 729 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 730 E1000_WRITE_FLUSH(hw); 731 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 732 } 733 734 /* Commit the write to flash */ 735 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 736 E1000_WRITE_REG(hw, E1000_EECD, eecd); 737 738 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 739 msec_delay(1); 740 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 741 break; 742 } 743 744 if (i == E1000_FLASH_UPDATES) { 745 ret_val = -E1000_ERR_NVM; 746 goto out; 747 } 748 749 out: 750 return (ret_val); 751 } 752 753 /* 754 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 755 * @hw: pointer to the HW structure 756 * 757 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 758 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 759 */ 760 static s32 761 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 762 { 763 DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 764 765 if (hw->nvm.type == e1000_nvm_flash_hw) 766 (void) e1000_fix_nvm_checksum_82571(hw); 767 768 return (e1000_validate_nvm_checksum_generic(hw)); 769 } 770 771 /* 772 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 773 * @hw: pointer to the HW structure 774 * @offset: offset within the EEPROM to be written to 775 * @words: number of words to write 776 * @data: 16 bit word(s) to be written to the EEPROM 777 * 778 * After checking for invalid values, poll the EEPROM to ensure the previous 779 * command has completed before trying to write the next word. After write 780 * poll for completion. 781 * 782 * If e1000_update_nvm_checksum is not called after this function, the 783 * EEPROM will most likely contain an invalid checksum. 784 */ 785 static s32 786 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 787 u16 words, u16 *data) 788 { 789 struct e1000_nvm_info *nvm = &hw->nvm; 790 u32 i, eewr = 0; 791 s32 ret_val = 0; 792 793 DEBUGFUNC("e1000_write_nvm_eewr_82571"); 794 795 /* 796 * A check for invalid values: offset too large, too many words, and 797 * not enough words. 798 */ 799 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 800 (words == 0)) { 801 DEBUGOUT("nvm parameter(s) out of bounds\n"); 802 ret_val = -E1000_ERR_NVM; 803 goto out; 804 } 805 806 for (i = 0; i < words; i++) { 807 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 808 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) | 809 E1000_NVM_RW_REG_START; 810 811 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 812 if (ret_val) 813 break; 814 815 E1000_WRITE_REG(hw, E1000_EEWR, eewr); 816 817 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 818 if (ret_val) 819 break; 820 } 821 822 out: 823 return (ret_val); 824 } 825 826 /* 827 * e1000_get_cfg_done_82571 - Poll for configuration done 828 * @hw: pointer to the HW structure 829 * 830 * Reads the management control register for the config done bit to be set. 831 */ 832 static s32 833 e1000_get_cfg_done_82571(struct e1000_hw *hw) 834 { 835 s32 timeout = PHY_CFG_TIMEOUT; 836 s32 ret_val = E1000_SUCCESS; 837 838 DEBUGFUNC("e1000_get_cfg_done_82571"); 839 840 while (timeout) { 841 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & 842 E1000_NVM_CFG_DONE_PORT_0) 843 break; 844 msec_delay(1); 845 timeout--; 846 } 847 if (!timeout) { 848 DEBUGOUT("MNG configuration cycle has not completed.\n"); 849 goto out; 850 } 851 852 out: 853 return (ret_val); 854 } 855 856 /* 857 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 858 * @hw: pointer to the HW structure 859 * @active: true to enable LPLU, false to disable 860 * 861 * Sets the LPLU D0 state according to the active flag. When activating LPLU 862 * this function also disables smart speed and vice versa. LPLU will not be 863 * activated unless the device autonegotiation advertisement meets standards 864 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 865 * pointer entry point only called by PHY setup routines. 866 */ 867 static s32 868 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 869 { 870 struct e1000_phy_info *phy = &hw->phy; 871 s32 ret_val = E1000_SUCCESS; 872 u16 data; 873 874 DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 875 876 if (!(phy->ops.read_reg)) 877 goto out; 878 879 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 880 if (ret_val) 881 goto out; 882 883 if (active) { 884 data |= IGP02E1000_PM_D0_LPLU; 885 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 886 data); 887 if (ret_val) 888 goto out; 889 890 /* When LPLU is enabled, we should disable SmartSpeed */ 891 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 892 &data); 893 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 894 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 895 data); 896 if (ret_val) 897 goto out; 898 } else { 899 data &= ~IGP02E1000_PM_D0_LPLU; 900 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 901 data); 902 /* 903 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 904 * during Dx states where the power conservation is most 905 * important. During driver activity we should enable 906 * SmartSpeed, so performance is maintained. 907 */ 908 if (phy->smart_speed == e1000_smart_speed_on) { 909 ret_val = phy->ops.read_reg(hw, 910 IGP01E1000_PHY_PORT_CONFIG, 911 &data); 912 if (ret_val) 913 goto out; 914 915 data |= IGP01E1000_PSCFR_SMART_SPEED; 916 ret_val = phy->ops.write_reg(hw, 917 IGP01E1000_PHY_PORT_CONFIG, 918 data); 919 if (ret_val) 920 goto out; 921 } else if (phy->smart_speed == e1000_smart_speed_off) { 922 ret_val = phy->ops.read_reg(hw, 923 IGP01E1000_PHY_PORT_CONFIG, 924 &data); 925 if (ret_val) 926 goto out; 927 928 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 929 ret_val = phy->ops.write_reg(hw, 930 IGP01E1000_PHY_PORT_CONFIG, 931 data); 932 if (ret_val) 933 goto out; 934 } 935 } 936 937 out: 938 return (ret_val); 939 } 940 941 /* 942 * e1000_reset_hw_82571 - Reset hardware 943 * @hw: pointer to the HW structure 944 * 945 * This resets the hardware into a known state. 946 */ 947 static s32 948 e1000_reset_hw_82571(struct e1000_hw *hw) 949 { 950 u32 ctrl, extcnf_ctrl, ctrl_ext; 951 s32 ret_val; 952 u16 i = 0; 953 954 DEBUGFUNC("e1000_reset_hw_82571"); 955 956 /* 957 * Prevent the PCI-E bus from sticking if there is no TLP connection 958 * on the last TLP read/write transaction when MAC is reset. 959 */ 960 ret_val = e1000_disable_pcie_master_generic(hw); 961 if (ret_val) { 962 /* EMPTY */ 963 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 964 } 965 966 DEBUGOUT("Masking off all interrupts\n"); 967 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 968 969 E1000_WRITE_REG(hw, E1000_RCTL, 0); 970 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 971 E1000_WRITE_FLUSH(hw); 972 973 msec_delay(10); 974 975 /* 976 * Must acquire the MDIO ownership before MAC reset. Ownership 977 * defaults to firmware after a reset. 978 */ 979 switch (hw->mac.type) { 980 case e1000_82573: 981 case e1000_82574: 982 case e1000_82583: 983 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 984 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 985 986 do { 987 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 988 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 989 990 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 991 break; 992 993 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 994 995 msec_delay(2); 996 i++; 997 } while (i < MDIO_OWNERSHIP_TIMEOUT); 998 break; 999 default: 1000 break; 1001 } 1002 1003 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1004 1005 DEBUGOUT("Issuing a global reset to MAC\n"); 1006 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1007 1008 if (hw->nvm.type == e1000_nvm_flash_hw) { 1009 usec_delay(10); 1010 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1011 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1012 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1013 E1000_WRITE_FLUSH(hw); 1014 } 1015 1016 ret_val = e1000_get_auto_rd_done_generic(hw); 1017 if (ret_val) 1018 /* We don't want to continue accessing MAC registers. */ 1019 goto out; 1020 1021 /* 1022 * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 1023 * Need to wait for Phy configuration completion before accessing 1024 * NVM and Phy. 1025 */ 1026 switch (hw->mac.type) { 1027 case e1000_82573: 1028 case e1000_82574: 1029 case e1000_82583: 1030 msec_delay(25); 1031 break; 1032 default: 1033 break; 1034 } 1035 1036 /* Clear any pending interrupt events. */ 1037 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1038 (void) E1000_READ_REG(hw, E1000_ICR); 1039 1040 /* Install any alternate MAC address into RAR0 */ 1041 ret_val = e1000_check_alt_mac_addr_generic(hw); 1042 if (ret_val) 1043 goto out; 1044 1045 e1000_set_laa_state_82571(hw, true); 1046 1047 /* Reinitialize the 82571 serdes link state machine */ 1048 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1049 hw->mac.serdes_link_state = e1000_serdes_link_down; 1050 1051 out: 1052 return (ret_val); 1053 } 1054 1055 /* 1056 * e1000_init_hw_82571 - Initialize hardware 1057 * @hw: pointer to the HW structure 1058 * 1059 * This inits the hardware readying it for operation. 1060 */ 1061 static s32 1062 e1000_init_hw_82571(struct e1000_hw *hw) 1063 { 1064 struct e1000_mac_info *mac = &hw->mac; 1065 u32 reg_data; 1066 s32 ret_val; 1067 u16 i, rar_count = mac->rar_entry_count; 1068 1069 DEBUGFUNC("e1000_init_hw_82571"); 1070 1071 e1000_initialize_hw_bits_82571(hw); 1072 1073 /* Initialize identification LED */ 1074 ret_val = mac->ops.id_led_init(hw); 1075 if (ret_val) { 1076 /* EMPTY */ 1077 DEBUGOUT("Error initializing identification LED\n"); 1078 /* This is not fatal and we should not stop init due to this */ 1079 } 1080 1081 /* Disabling VLAN filtering */ 1082 DEBUGOUT("Initializing the IEEE VLAN\n"); 1083 mac->ops.clear_vfta(hw); 1084 1085 /* Setup the receive address. */ 1086 /* 1087 * If, however, a locally administered address was assigned to the 1088 * 82571, we must reserve a RAR for it to work around an issue where 1089 * resetting one port will reload the MAC on the other port. 1090 */ 1091 if (e1000_get_laa_state_82571(hw)) 1092 rar_count--; 1093 e1000_init_rx_addrs_generic(hw, rar_count); 1094 1095 /* Zero out the Multicast HASH table */ 1096 DEBUGOUT("Zeroing the MTA\n"); 1097 for (i = 0; i < mac->mta_reg_count; i++) 1098 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1099 1100 /* Setup link and flow control */ 1101 ret_val = mac->ops.setup_link(hw); 1102 1103 /* Set the transmit descriptor write-back policy */ 1104 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1105 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1106 E1000_TXDCTL_FULL_TX_DESC_WB | 1107 E1000_TXDCTL_COUNT_DESC; 1108 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 1109 1110 /* ...for both queues. */ 1111 switch (mac->type) { 1112 case e1000_82573: 1113 case e1000_82574: 1114 case e1000_82583: 1115 (void) e1000_enable_tx_pkt_filtering_generic(hw); 1116 reg_data = E1000_READ_REG(hw, E1000_GCR); 1117 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1118 E1000_WRITE_REG(hw, E1000_GCR, reg_data); 1119 break; 1120 default: 1121 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1122 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1123 E1000_TXDCTL_FULL_TX_DESC_WB | 1124 E1000_TXDCTL_COUNT_DESC; 1125 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 1126 break; 1127 } 1128 1129 /* 1130 * Clear all of the statistics registers (clear on read). It is 1131 * important that we do this after we have tried to establish link 1132 * because the symbol error count will increment wildly if there 1133 * is no link. 1134 */ 1135 e1000_clear_hw_cntrs_82571(hw); 1136 1137 return (ret_val); 1138 } 1139 1140 /* 1141 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1142 * @hw: pointer to the HW structure 1143 * 1144 * Initializes required hardware-dependent bits needed for normal operation. 1145 */ 1146 static void 1147 e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1148 { 1149 u32 reg; 1150 1151 DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1152 1153 /* Transmit Descriptor Control 0 */ 1154 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1155 reg |= (1 << 22); 1156 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1157 1158 /* Transmit Descriptor Control 1 */ 1159 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1160 reg |= (1 << 22); 1161 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1162 1163 /* Transmit Arbitration Control 0 */ 1164 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1165 reg &= ~(0xF << 27); /* 30:27 */ 1166 switch (hw->mac.type) { 1167 case e1000_82571: 1168 case e1000_82572: 1169 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1170 break; 1171 default: 1172 break; 1173 } 1174 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1175 1176 /* Transmit Arbitration Control 1 */ 1177 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1178 switch (hw->mac.type) { 1179 case e1000_82571: 1180 case e1000_82572: 1181 reg &= ~((1 << 29) | (1 << 30)); 1182 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1183 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1184 reg &= ~(1 << 28); 1185 else 1186 reg |= (1 << 28); 1187 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1188 break; 1189 default: 1190 break; 1191 } 1192 1193 /* Device Control */ 1194 switch (hw->mac.type) { 1195 case e1000_82573: 1196 case e1000_82574: 1197 case e1000_82583: 1198 reg = E1000_READ_REG(hw, E1000_CTRL); 1199 reg &= ~(1 << 29); 1200 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1201 break; 1202 default: 1203 break; 1204 } 1205 1206 /* Extended Device Control */ 1207 switch (hw->mac.type) { 1208 case e1000_82573: 1209 case e1000_82574: 1210 case e1000_82583: 1211 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1212 reg &= ~(1 << 23); 1213 reg |= (1 << 22); 1214 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1215 break; 1216 default: 1217 break; 1218 } 1219 1220 if (hw->mac.type == e1000_82571) { 1221 reg = E1000_READ_REG(hw, E1000_PBA_ECC); 1222 reg |= E1000_PBA_ECC_CORR_EN; 1223 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); 1224 } 1225 1226 /* 1227 * Workaround for hardware errata. 1228 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1229 */ 1230 if ((hw->mac.type == e1000_82571) || 1231 (hw->mac.type == e1000_82572)) { 1232 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1233 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1234 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1235 } 1236 1237 /* PCI-Ex Control Registers */ 1238 switch (hw->mac.type) { 1239 case e1000_82574: 1240 case e1000_82583: 1241 reg = E1000_READ_REG(hw, E1000_GCR); 1242 reg |= (1 << 22); 1243 E1000_WRITE_REG(hw, E1000_GCR, reg); 1244 /* 1245 * Workaround for hardware errata. 1246 * apply workaround for hardware errata documented in errata 1247 * docs Fixes issue where some error prone or unreliable PCIe 1248 * completions are occurring, particularly with ASPM enabled. 1249 * Without fix, issue can cause tx timeouts. 1250 */ 1251 reg = E1000_READ_REG(hw, E1000_GCR2); 1252 reg |= 1; 1253 E1000_WRITE_REG(hw, E1000_GCR2, reg); 1254 break; 1255 default: 1256 break; 1257 } 1258 } 1259 1260 /* 1261 * e1000_clear_vfta_82571 - Clear VLAN filter table 1262 * @hw: pointer to the HW structure 1263 * 1264 * Clears the register array which contains the VLAN filter table by 1265 * setting all the values to 0. 1266 */ 1267 static void 1268 e1000_clear_vfta_82571(struct e1000_hw *hw) 1269 { 1270 u32 offset; 1271 u32 vfta_value = 0; 1272 u32 vfta_offset = 0; 1273 u32 vfta_bit_in_reg = 0; 1274 1275 DEBUGFUNC("e1000_clear_vfta_82571"); 1276 1277 switch (hw->mac.type) { 1278 case e1000_82573: 1279 case e1000_82574: 1280 case e1000_82583: 1281 if (hw->mng_cookie.vlan_id != 0) { 1282 /* 1283 * The VFTA is a 4096b bit-field, each identifying 1284 * a single VLAN ID. The following operations 1285 * determine which 32b entry (i.e. offset) into the 1286 * array we want to set the VLAN ID (i.e. bit) of 1287 * the manageability unit. 1288 */ 1289 vfta_offset = (hw->mng_cookie.vlan_id >> 1290 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 1291 1292 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1293 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1294 } 1295 1296 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; 1297 offset ++) { 1298 /* 1299 * If the offset we want to clear is the same offset of 1300 * the manageability VLAN ID, then clear all bits except 1301 * that of the manageability unit 1302 */ 1303 vfta_value = (offset == vfta_offset) ? 1304 vfta_bit_in_reg : 0; 1305 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 1306 vfta_value); 1307 E1000_WRITE_FLUSH(hw); 1308 } 1309 break; 1310 default: 1311 break; 1312 } 1313 } 1314 1315 /* 1316 * e1000_check_mng_mode_82574 - Check manageability is enabled 1317 * @hw: pointer to the HW structure 1318 * 1319 * Reads the NVM Initialization Control Word 2 and returns true 1320 * (>0) if any manageability is enabled, else false (0). 1321 */ 1322 static bool 1323 e1000_check_mng_mode_82574(struct e1000_hw *hw) 1324 { 1325 u16 data; 1326 1327 DEBUGFUNC("e1000_check_mng_mode_82574"); 1328 1329 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1330 return ((data & E1000_NVM_INIT_CTRL2_MNGM) != 0); 1331 } 1332 1333 /* 1334 * e1000_led_on_82574 - Turn LED on 1335 * @hw: pointer to the HW structure 1336 * 1337 * Turn LED on. 1338 */ 1339 static s32 1340 e1000_led_on_82574(struct e1000_hw *hw) 1341 { 1342 u32 ctrl; 1343 u32 i; 1344 1345 DEBUGFUNC("e1000_led_on_82574"); 1346 1347 ctrl = hw->mac.ledctl_mode2; 1348 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { 1349 /* 1350 * If no link, then turn LED on by setting the invert bit 1351 * for each LED that's "on" (0x0E) in ledctl_mode2. 1352 */ 1353 for (i = 0; i < 4; i++) 1354 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1355 E1000_LEDCTL_MODE_LED_ON) 1356 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1357 } 1358 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl); 1359 1360 return (E1000_SUCCESS); 1361 } 1362 1363 /* 1364 * e1000_setup_link_82571 - Setup flow control and link settings 1365 * @hw: pointer to the HW structure 1366 * 1367 * Determines which flow control settings to use, then configures flow 1368 * control. Calls the appropriate media-specific link configuration 1369 * function. Assuming the adapter has a valid link partner, a valid link 1370 * should be established. Assumes the hardware has previously been reset 1371 * and the transmitter and receiver are not enabled. 1372 */ 1373 static s32 1374 e1000_setup_link_82571(struct e1000_hw *hw) 1375 { 1376 DEBUGFUNC("e1000_setup_link_82571"); 1377 1378 /* 1379 * 82573 does not have a word in the NVM to determine the default flow 1380 * control setting, so we explicitly set it to full. 1381 */ 1382 switch (hw->mac.type) { 1383 case e1000_82573: 1384 case e1000_82574: 1385 case e1000_82583: 1386 if (hw->fc.requested_mode == e1000_fc_default) 1387 hw->fc.requested_mode = e1000_fc_full; 1388 break; 1389 default: 1390 break; 1391 } 1392 return (e1000_setup_link_generic(hw)); 1393 } 1394 1395 /* 1396 * e1000_setup_copper_link_82571 - Configure copper link settings 1397 * @hw: pointer to the HW structure 1398 * 1399 * Configures the link for auto-neg or forced speed and duplex. Then we check 1400 * for link, once link is established calls to configure collision distance 1401 * and flow control are called. 1402 */ 1403 static s32 1404 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1405 { 1406 u32 ctrl; 1407 s32 ret_val; 1408 1409 DEBUGFUNC("e1000_setup_copper_link_82571"); 1410 1411 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1412 ctrl |= E1000_CTRL_SLU; 1413 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1414 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1415 1416 switch (hw->phy.type) { 1417 case e1000_phy_m88: 1418 case e1000_phy_bm: 1419 ret_val = e1000_copper_link_setup_m88(hw); 1420 break; 1421 case e1000_phy_igp_2: 1422 ret_val = e1000_copper_link_setup_igp(hw); 1423 break; 1424 default: 1425 ret_val = -E1000_ERR_PHY; 1426 break; 1427 } 1428 1429 if (ret_val) 1430 goto out; 1431 1432 ret_val = e1000_setup_copper_link_generic(hw); 1433 1434 out: 1435 return (ret_val); 1436 } 1437 1438 /* 1439 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1440 * @hw: pointer to the HW structure 1441 * 1442 * Configures collision distance and flow control for fiber and serdes links. 1443 * Upon successful setup, poll for link. 1444 */ 1445 static s32 1446 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1447 { 1448 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1449 1450 switch (hw->mac.type) { 1451 case e1000_82571: 1452 case e1000_82572: 1453 /* 1454 * If SerDes loopback mode is entered, there is no form of 1455 * reset to take the adapter out of that mode. So we have to 1456 * explicitly take the adapter out of loopback mode. This 1457 * prevents drivers from twiddling their thumbs if another 1458 * tool failed to take it out of loopback mode. 1459 */ 1460 E1000_WRITE_REG(hw, E1000_SCTL, 1461 E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1462 break; 1463 default: 1464 break; 1465 } 1466 1467 return (e1000_setup_fiber_serdes_link_generic(hw)); 1468 } 1469 1470 /* 1471 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1472 * @hw: pointer to the HW structure 1473 * 1474 * Reports the link state as up or down. 1475 * 1476 * If autonegotiation is supported by the link partner, the link state is 1477 * determined by the result of autongotiation. This is the most likely case. 1478 * If autonegotiation is not supported by the link partner, and the link 1479 * has a valid signal, force the link up. 1480 * 1481 * The link state is represented internally here by 4 states: 1482 * 1483 * 1) down 1484 * 2) autoneg_progress 1485 * 3) autoneg_complete (the link sucessfully autonegotiated) 1486 * 4) forced_up (the link has been forced up, it did not autonegotiate) 1487 */ 1488 s32 1489 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1490 { 1491 struct e1000_mac_info *mac = &hw->mac; 1492 u32 rxcw; 1493 u32 ctrl; 1494 u32 status; 1495 s32 ret_val = E1000_SUCCESS; 1496 1497 DEBUGFUNC("e1000_check_for_serdes_link_82571"); 1498 1499 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1500 status = E1000_READ_REG(hw, E1000_STATUS); 1501 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1502 1503 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1504 1505 /* Receiver is synchronized with no invalid bits. */ 1506 switch (mac->serdes_link_state) { 1507 case e1000_serdes_link_autoneg_complete: 1508 if (!(status & E1000_STATUS_LU)) { 1509 /* 1510 * We have lost link, retry autoneg before 1511 * reporting link failure 1512 */ 1513 mac->serdes_link_state = 1514 e1000_serdes_link_autoneg_progress; 1515 mac->serdes_has_link = false; 1516 DEBUGOUT("AN_UP -> AN_PROG\n"); 1517 } 1518 break; 1519 1520 case e1000_serdes_link_forced_up: 1521 /* 1522 * If we are receiving /C/ ordered sets, re-enable 1523 * auto-negotiation in the TXCW register and disable 1524 * forced link in the Device Control register in an 1525 * attempt to auto-negotiate with our link partner. 1526 */ 1527 if (rxcw & E1000_RXCW_C) { 1528 /* Enable autoneg, and unforce link up */ 1529 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1530 E1000_WRITE_REG(hw, E1000_CTRL, 1531 (ctrl & ~E1000_CTRL_SLU)); 1532 mac->serdes_link_state = 1533 e1000_serdes_link_autoneg_progress; 1534 mac->serdes_has_link = false; 1535 DEBUGOUT("FORCED_UP -> AN_PROG\n"); 1536 } 1537 break; 1538 1539 case e1000_serdes_link_autoneg_progress: 1540 if (rxcw & E1000_RXCW_C) { 1541 /* 1542 * We received /C/ ordered sets, meaning the 1543 * link partner has autonegotiated, and we can 1544 * trust the Link Up (LU) status bit 1545 */ 1546 if (status & E1000_STATUS_LU) { 1547 mac->serdes_link_state = 1548 e1000_serdes_link_autoneg_complete; 1549 DEBUGOUT("AN_PROG -> AN_UP\n"); 1550 mac->serdes_has_link = true; 1551 } else { 1552 /* Autoneg completed, but failed */ 1553 mac->serdes_link_state = 1554 e1000_serdes_link_down; 1555 DEBUGOUT("AN_PROG -> DOWN\n"); 1556 } 1557 } else { 1558 /* 1559 * The link partner did not autoneg. 1560 * Force link up and full duplex, and change 1561 * state to forced. 1562 */ 1563 E1000_WRITE_REG(hw, E1000_TXCW, 1564 (mac->txcw & ~E1000_TXCW_ANE)); 1565 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1566 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1567 1568 /* Configure Flow Control after link up. */ 1569 ret_val = 1570 e1000_config_fc_after_link_up_generic(hw); 1571 if (ret_val) { 1572 DEBUGOUT("Error config flow control\n"); 1573 break; 1574 } 1575 mac->serdes_link_state = 1576 e1000_serdes_link_forced_up; 1577 mac->serdes_has_link = true; 1578 DEBUGOUT("AN_PROG -> FORCED_UP\n"); 1579 } 1580 break; 1581 1582 case e1000_serdes_link_down: 1583 default: 1584 /* 1585 * The link was down but the receiver has now gained 1586 * valid sync, so lets see if we can bring the link 1587 * up. 1588 */ 1589 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1590 E1000_WRITE_REG(hw, E1000_CTRL, 1591 (ctrl & ~E1000_CTRL_SLU)); 1592 mac->serdes_link_state = 1593 e1000_serdes_link_autoneg_progress; 1594 DEBUGOUT("DOWN -> AN_PROG\n"); 1595 break; 1596 } 1597 } else { 1598 if (!(rxcw & E1000_RXCW_SYNCH)) { 1599 mac->serdes_has_link = false; 1600 mac->serdes_link_state = e1000_serdes_link_down; 1601 DEBUGOUT("ANYSTATE -> DOWN\n"); 1602 } else { 1603 /* 1604 * We have sync, and can tolerate one 1605 * invalid (IV) codeword before declaring 1606 * link down, so reread to look again 1607 */ 1608 usec_delay(10); 1609 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1610 if (rxcw & E1000_RXCW_IV) { 1611 mac->serdes_link_state = e1000_serdes_link_down; 1612 mac->serdes_has_link = false; 1613 DEBUGOUT("ANYSTATE -> DOWN\n"); 1614 } 1615 } 1616 } 1617 1618 return (ret_val); 1619 } 1620 1621 /* 1622 * e1000_valid_led_default_82571 - Verify a valid default LED config 1623 * @hw: pointer to the HW structure 1624 * @data: pointer to the NVM (EEPROM) 1625 * 1626 * Read the EEPROM for the current default LED configuration. If the 1627 * LED configuration is not valid, set to a valid LED configuration. 1628 */ 1629 static s32 1630 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 * data) 1631 { 1632 s32 ret_val; 1633 1634 DEBUGFUNC("e1000_valid_led_default_82571"); 1635 1636 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1637 if (ret_val) { 1638 DEBUGOUT("NVM Read Error\n"); 1639 goto out; 1640 } 1641 1642 switch (hw->mac.type) { 1643 case e1000_82573: 1644 case e1000_82574: 1645 case e1000_82583: 1646 if (*data == ID_LED_RESERVED_F746) 1647 *data = ID_LED_DEFAULT_82573; 1648 break; 1649 default: 1650 if (*data == ID_LED_RESERVED_0000 || 1651 *data == ID_LED_RESERVED_FFFF) 1652 *data = ID_LED_DEFAULT; 1653 break; 1654 } 1655 1656 out: 1657 return (ret_val); 1658 } 1659 1660 /* 1661 * e1000_get_laa_state_82571 - Get locally administered address state 1662 * @hw: pointer to the HW structure 1663 * 1664 * Retrieve and return the current locally administered address state. 1665 */ 1666 bool 1667 e1000_get_laa_state_82571(struct e1000_hw *hw) 1668 { 1669 DEBUGFUNC("e1000_get_laa_state_82571"); 1670 1671 if (hw->mac.type != e1000_82571) 1672 return (false); 1673 1674 return (hw->dev_spec._82571.laa_is_present); 1675 } 1676 1677 /* 1678 * e1000_set_laa_state_82571 - Set locally administered address state 1679 * @hw: pointer to the HW structure 1680 * @state: enable/disable locally administered address 1681 * 1682 * Enable/Disable the current locally administered address state. 1683 */ 1684 void 1685 e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1686 { 1687 DEBUGFUNC("e1000_set_laa_state_82571"); 1688 1689 if (hw->mac.type != e1000_82571) 1690 return; 1691 1692 hw->dev_spec._82571.laa_is_present = state; 1693 1694 /* If workaround is activated... */ 1695 if (state) { 1696 /* 1697 * Hold a copy of the LAA in RAR[14] This is done so that 1698 * between the time RAR[0] gets clobbered and the time it gets 1699 * fixed, the actual LAA is in one of the RARs and no incoming 1700 * packets directed to this port are dropped. Eventually the 1701 * LAA will be in RAR[0] and RAR[14]. 1702 */ 1703 e1000_rar_set_generic(hw, hw->mac.addr, 1704 hw->mac.rar_entry_count - 1); 1705 } 1706 } 1707 1708 /* 1709 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1710 * @hw: pointer to the HW structure 1711 * 1712 * Verifies that the EEPROM has completed the update. After updating the 1713 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1714 * the checksum fix is not implemented, we need to set the bit and update 1715 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1716 * we need to return bad checksum. 1717 */ 1718 static s32 1719 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1720 { 1721 struct e1000_nvm_info *nvm = &hw->nvm; 1722 s32 ret_val = E1000_SUCCESS; 1723 u16 data; 1724 1725 DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1726 1727 if (nvm->type != e1000_nvm_flash_hw) 1728 goto out; 1729 1730 /* 1731 * Check bit 4 of word 10h. If it is 0, firmware is done updating 1732 * 10h-12h. Checksum may need to be fixed. 1733 */ 1734 ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1735 if (ret_val) 1736 goto out; 1737 1738 if (!(data & 0x10)) { 1739 /* 1740 * Read 0x23 and check bit 15. This bit is a 1 when the 1741 * checksum has already been fixed. If the checksum is still 1742 * wrong and this bit is a 1, we need to return bad checksum. 1743 * Otherwise, we need to set this bit to a 1 and update the 1744 * checksum. 1745 */ 1746 ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1747 if (ret_val) 1748 goto out; 1749 1750 if (!(data & 0x8000)) { 1751 data |= 0x8000; 1752 ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1753 if (ret_val) 1754 goto out; 1755 ret_val = nvm->ops.update(hw); 1756 } 1757 } 1758 1759 out: 1760 return (ret_val); 1761 } 1762 1763 /* 1764 * e1000_read_mac_addr_82571 - Read device MAC address 1765 * @hw: pointer to the HW structure 1766 */ 1767 static s32 1768 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1769 { 1770 s32 ret_val = E1000_SUCCESS; 1771 1772 DEBUGFUNC("e1000_read_mac_addr_82571"); 1773 1774 /* 1775 * If there's an alternate MAC address place it in RAR0 1776 * so that it will override the Si installed default perm 1777 * address. 1778 */ 1779 ret_val = e1000_check_alt_mac_addr_generic(hw); 1780 if (ret_val) 1781 goto out; 1782 1783 ret_val = e1000_read_mac_addr_generic(hw); 1784 1785 out: 1786 return (ret_val); 1787 } 1788 1789 /* 1790 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1791 * @hw: pointer to the HW structure 1792 * 1793 * In the case of a PHY power down to save power, or to turn off link during a 1794 * driver unload, or wake on lan is not enabled, remove the link. 1795 */ 1796 static void 1797 e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1798 { 1799 struct e1000_phy_info *phy = &hw->phy; 1800 struct e1000_mac_info *mac = &hw->mac; 1801 1802 if (!(phy->ops.check_reset_block)) 1803 return; 1804 1805 /* If the management interface is not enabled, then power down */ 1806 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1807 e1000_power_down_phy_copper(hw); 1808 } 1809 1810 /* 1811 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1812 * @hw: pointer to the HW structure 1813 * 1814 * Clears the hardware counters by reading the counter registers. 1815 */ 1816 static void 1817 e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1818 { 1819 DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1820 1821 e1000_clear_hw_cntrs_base_generic(hw); 1822 1823 (void) E1000_READ_REG(hw, E1000_PRC64); 1824 (void) E1000_READ_REG(hw, E1000_PRC127); 1825 (void) E1000_READ_REG(hw, E1000_PRC255); 1826 (void) E1000_READ_REG(hw, E1000_PRC511); 1827 (void) E1000_READ_REG(hw, E1000_PRC1023); 1828 (void) E1000_READ_REG(hw, E1000_PRC1522); 1829 (void) E1000_READ_REG(hw, E1000_PTC64); 1830 (void) E1000_READ_REG(hw, E1000_PTC127); 1831 (void) E1000_READ_REG(hw, E1000_PTC255); 1832 (void) E1000_READ_REG(hw, E1000_PTC511); 1833 (void) E1000_READ_REG(hw, E1000_PTC1023); 1834 (void) E1000_READ_REG(hw, E1000_PTC1522); 1835 1836 (void) E1000_READ_REG(hw, E1000_ALGNERRC); 1837 (void) E1000_READ_REG(hw, E1000_RXERRC); 1838 (void) E1000_READ_REG(hw, E1000_TNCRS); 1839 (void) E1000_READ_REG(hw, E1000_CEXTERR); 1840 (void) E1000_READ_REG(hw, E1000_TSCTC); 1841 (void) E1000_READ_REG(hw, E1000_TSCTFC); 1842 1843 (void) E1000_READ_REG(hw, E1000_MGTPRC); 1844 (void) E1000_READ_REG(hw, E1000_MGTPDC); 1845 (void) E1000_READ_REG(hw, E1000_MGTPTC); 1846 1847 (void) E1000_READ_REG(hw, E1000_IAC); 1848 (void) E1000_READ_REG(hw, E1000_ICRXOC); 1849 1850 (void) E1000_READ_REG(hw, E1000_ICRXPTC); 1851 (void) E1000_READ_REG(hw, E1000_ICRXATC); 1852 (void) E1000_READ_REG(hw, E1000_ICTXPTC); 1853 (void) E1000_READ_REG(hw, E1000_ICTXATC); 1854 (void) E1000_READ_REG(hw, E1000_ICTXQEC); 1855 (void) E1000_READ_REG(hw, E1000_ICTXQMTC); 1856 (void) E1000_READ_REG(hw, E1000_ICRXDMTC); 1857 } 1858
Indexes created Wed Feb 10 04:24:43 UTC 2010
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