1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 /* 27 * IntelVersion: 1.68 v3-1-10-1_2009-9-18_Release14-6 28 */ 29 30 /* 31 * 82541EI Gigabit Ethernet Controller 32 * 82541ER Gigabit Ethernet Controller 33 * 82541GI Gigabit Ethernet Controller 34 * 82541PI Gigabit Ethernet Controller 35 * 82547EI Gigabit Ethernet Controller 36 * 82547GI Gigabit Ethernet Controller 37 */ 38 39 #include "e1000_api.h" 40 41 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw); 42 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); 43 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw); 44 static s32 e1000_reset_hw_82541(struct e1000_hw *hw); 45 static s32 e1000_init_hw_82541(struct e1000_hw *hw); 46 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 47 u16 *duplex); 48 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); 49 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); 50 static s32 e1000_check_for_link_82541(struct e1000_hw *hw); 51 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); 52 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, 53 bool active); 54 static s32 e1000_setup_led_82541(struct e1000_hw *hw); 55 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw); 56 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); 57 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 58 bool link_up); 59 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw); 60 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw); 61 62 static const u16 e1000_igp_cable_length_table[] = 63 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 64 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 65 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 66 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 67 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 68 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 69 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 70 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 71 72 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ 73 (sizeof (e1000_igp_cable_length_table) / \ 74 sizeof (e1000_igp_cable_length_table[0])) 75 76 /* 77 * e1000_init_phy_params_82541 - Init PHY func ptrs. 78 * @hw: pointer to the HW structure 79 */ 80 static s32 81 e1000_init_phy_params_82541(struct e1000_hw *hw) 82 { 83 struct e1000_phy_info *phy = &hw->phy; 84 s32 ret_val = E1000_SUCCESS; 85 86 DEBUGFUNC("e1000_init_phy_params_82541"); 87 88 phy->addr = 1; 89 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 90 phy->reset_delay_us = 10000; 91 phy->type = e1000_phy_igp; 92 93 /* Function Pointers */ 94 phy->ops.check_polarity = e1000_check_polarity_igp; 95 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 96 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541; 97 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 98 phy->ops.get_info = e1000_get_phy_info_igp; 99 phy->ops.read_reg = e1000_read_phy_reg_igp; 100 phy->ops.reset = e1000_phy_hw_reset_82541; 101 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541; 102 phy->ops.write_reg = e1000_write_phy_reg_igp; 103 phy->ops.power_up = e1000_power_up_phy_copper; 104 phy->ops.power_down = e1000_power_down_phy_copper_82541; 105 106 ret_val = e1000_get_phy_id(hw); 107 if (ret_val) 108 goto out; 109 110 /* Verify phy id */ 111 if (phy->id != IGP01E1000_I_PHY_ID) { 112 ret_val = -E1000_ERR_PHY; 113 goto out; 114 } 115 116 out: 117 return (ret_val); 118 } 119 120 /* 121 * e1000_init_nvm_params_82541 - Init NVM func ptrs. 122 * @hw: pointer to the HW structure 123 */ 124 static s32 125 e1000_init_nvm_params_82541(struct e1000_hw *hw) 126 { 127 struct e1000_nvm_info *nvm = &hw->nvm; 128 s32 ret_val = E1000_SUCCESS; 129 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 130 u16 size; 131 132 DEBUGFUNC("e1000_init_nvm_params_82541"); 133 134 switch (nvm->override) { 135 case e1000_nvm_override_spi_large: 136 nvm->type = e1000_nvm_eeprom_spi; 137 eecd |= E1000_EECD_ADDR_BITS; 138 break; 139 case e1000_nvm_override_spi_small: 140 nvm->type = e1000_nvm_eeprom_spi; 141 eecd &= ~E1000_EECD_ADDR_BITS; 142 break; 143 case e1000_nvm_override_microwire_large: 144 nvm->type = e1000_nvm_eeprom_microwire; 145 eecd |= E1000_EECD_SIZE; 146 break; 147 case e1000_nvm_override_microwire_small: 148 nvm->type = e1000_nvm_eeprom_microwire; 149 eecd &= ~E1000_EECD_SIZE; 150 break; 151 default: 152 nvm->type = eecd & E1000_EECD_TYPE 153 ? e1000_nvm_eeprom_spi 154 : e1000_nvm_eeprom_microwire; 155 break; 156 } 157 158 if (nvm->type == e1000_nvm_eeprom_spi) { 159 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 160 ? 16 : 8; 161 nvm->delay_usec = 1; 162 nvm->opcode_bits = 8; 163 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) 164 ? 32 : 8; 165 166 /* Function Pointers */ 167 nvm->ops.acquire = e1000_acquire_nvm_generic; 168 nvm->ops.read = e1000_read_nvm_spi; 169 nvm->ops.release = e1000_release_nvm_generic; 170 nvm->ops.update = e1000_update_nvm_checksum_generic; 171 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 172 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 173 nvm->ops.write = e1000_write_nvm_spi; 174 175 /* 176 * nvm->word_size must be discovered after the pointers 177 * are set so we can verify the size from the nvm image 178 * itself. Temporarily set it to a dummy value so the 179 * read will work. 180 */ 181 nvm->word_size = 64; 182 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size); 183 if (ret_val) 184 goto out; 185 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; 186 /* 187 * if size != 0, it can be added to a constant and become 188 * the left-shift value to set the word_size. Otherwise, 189 * word_size stays at 64. 190 */ 191 if (size) { 192 size += NVM_WORD_SIZE_BASE_SHIFT_82541; 193 nvm->word_size = 1 << size; 194 } 195 } else { 196 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 197 ? 8 : 6; 198 nvm->delay_usec = 50; 199 nvm->opcode_bits = 3; 200 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) 201 ? 256 : 64; 202 203 /* Function Pointers */ 204 nvm->ops.acquire = e1000_acquire_nvm_generic; 205 nvm->ops.read = e1000_read_nvm_microwire; 206 nvm->ops.release = e1000_release_nvm_generic; 207 nvm->ops.update = e1000_update_nvm_checksum_generic; 208 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 209 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 210 nvm->ops.write = e1000_write_nvm_microwire; 211 } 212 213 out: 214 return (ret_val); 215 } 216 217 /* 218 * e1000_init_mac_params_82541 - Init MAC func ptrs. 219 * @hw: pointer to the HW structure 220 */ 221 static s32 222 e1000_init_mac_params_82541(struct e1000_hw *hw) 223 { 224 struct e1000_mac_info *mac = &hw->mac; 225 226 DEBUGFUNC("e1000_init_mac_params_82541"); 227 228 /* Set media type */ 229 hw->phy.media_type = e1000_media_type_copper; 230 /* Set mta register count */ 231 mac->mta_reg_count = 128; 232 /* Set rar entry count */ 233 mac->rar_entry_count = E1000_RAR_ENTRIES; 234 /* Set if part includes ASF firmware */ 235 mac->asf_firmware_present = true; 236 237 /* Function Pointers */ 238 239 /* bus type/speed/width */ 240 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 241 /* function id */ 242 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 243 /* reset */ 244 mac->ops.reset_hw = e1000_reset_hw_82541; 245 /* hw initialization */ 246 mac->ops.init_hw = e1000_init_hw_82541; 247 /* link setup */ 248 mac->ops.setup_link = e1000_setup_link_generic; 249 /* physical interface link setup */ 250 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541; 251 /* check for link */ 252 mac->ops.check_for_link = e1000_check_for_link_82541; 253 /* link info */ 254 mac->ops.get_link_up_info = e1000_get_link_up_info_82541; 255 /* multicast address update */ 256 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 257 /* writing VFTA */ 258 mac->ops.write_vfta = e1000_write_vfta_generic; 259 /* clearing VFTA */ 260 mac->ops.clear_vfta = e1000_clear_vfta_generic; 261 /* setting MTA */ 262 mac->ops.mta_set = e1000_mta_set_generic; 263 /* ID LED init */ 264 mac->ops.id_led_init = e1000_id_led_init_generic; 265 /* setup LED */ 266 mac->ops.setup_led = e1000_setup_led_82541; 267 /* cleanup LED */ 268 mac->ops.cleanup_led = e1000_cleanup_led_82541; 269 /* turn on/off LED */ 270 mac->ops.led_on = e1000_led_on_generic; 271 mac->ops.led_off = e1000_led_off_generic; 272 /* clear hardware counters */ 273 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541; 274 275 return (E1000_SUCCESS); 276 } 277 278 /* 279 * e1000_init_function_pointers_82541 - Init func ptrs. 280 * @hw: pointer to the HW structure 281 * 282 * Called to initialize all function pointers and parameters. 283 */ 284 void 285 e1000_init_function_pointers_82541(struct e1000_hw *hw) 286 { 287 DEBUGFUNC("e1000_init_function_pointers_82541"); 288 289 hw->mac.ops.init_params = e1000_init_mac_params_82541; 290 hw->nvm.ops.init_params = e1000_init_nvm_params_82541; 291 hw->phy.ops.init_params = e1000_init_phy_params_82541; 292 } 293 294 /* 295 * e1000_reset_hw_82541 - Reset hardware 296 * @hw: pointer to the HW structure 297 * 298 * This resets the hardware into a known state. 299 */ 300 static s32 301 e1000_reset_hw_82541(struct e1000_hw *hw) 302 { 303 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 304 u32 ledctl, ctrl, manc; 305 306 DEBUGFUNC("e1000_reset_hw_82541"); 307 308 DEBUGOUT("Masking off all interrupts\n"); 309 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 310 311 E1000_WRITE_REG(hw, E1000_RCTL, 0); 312 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 313 E1000_WRITE_FLUSH(hw); 314 315 dev_spec->tx_fifo_head = 0; 316 317 /* 318 * Delay to allow any outstanding PCI transactions to complete 319 * before resetting the device. 320 */ 321 msec_delay(10); 322 323 ctrl = E1000_READ_REG(hw, E1000_CTRL); 324 325 /* Must reset the Phy before resetting the MAC */ 326 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 327 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); 328 msec_delay(5); 329 } 330 331 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); 332 switch (hw->mac.type) { 333 case e1000_82541: 334 case e1000_82541_rev_2: 335 /* 336 * These controllers can't ack the 64-bit write when 337 * issuing the reset, so we use IO-mapping as a 338 * workaround to issue the reset. 339 */ 340 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 341 break; 342 default: 343 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 344 break; 345 } 346 347 /* Wait for NVM reload */ 348 msec_delay(20); 349 350 /* Disable HW ARPs on ASF enabled adapters */ 351 manc = E1000_READ_REG(hw, E1000_MANC); 352 manc &= ~E1000_MANC_ARP_EN; 353 E1000_WRITE_REG(hw, E1000_MANC, manc); 354 355 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 356 (void) e1000_phy_init_script_82541(hw); 357 358 /* Configure activity LED after Phy reset */ 359 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 360 ledctl &= IGP_ACTIVITY_LED_MASK; 361 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 362 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 363 } 364 365 /* Once again, mask the interrupts */ 366 DEBUGOUT("Masking off all interrupts\n"); 367 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 368 369 /* Clear any pending interrupt events. */ 370 (void) E1000_READ_REG(hw, E1000_ICR); 371 372 return (E1000_SUCCESS); 373 } 374 375 /* 376 * e1000_init_hw_82541 - Initialize hardware 377 * @hw: pointer to the HW structure 378 * 379 * This inits the hardware readying it for operation. 380 */ 381 static s32 382 e1000_init_hw_82541(struct e1000_hw *hw) 383 { 384 struct e1000_mac_info *mac = &hw->mac; 385 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 386 u32 pba; 387 u32 i, txdctl; 388 s32 ret_val; 389 390 DEBUGFUNC("e1000_init_hw_82541"); 391 392 /* Initialize identification LED */ 393 ret_val = mac->ops.id_led_init(hw); 394 if (ret_val) { 395 /* EMPTY */ 396 DEBUGOUT("Error initializing identification LED\n"); 397 /* This is not fatal and we should not stop init due to this */ 398 } 399 400 /* Storing the Speed Power Down value for later use */ 401 ret_val = hw->phy.ops.read_reg(hw, 402 IGP01E1000_GMII_FIFO, 403 &dev_spec->spd_default); 404 if (ret_val) 405 goto out; 406 407 pba = E1000_READ_REG(hw, E1000_PBA); 408 dev_spec->tx_fifo_start = (pba & 0x0000FFFF) * E1000_FIFO_MULTIPLIER; 409 dev_spec->tx_fifo_size = (pba & 0xFFFF0000) >> 6; 410 411 /* Disabling VLAN filtering */ 412 DEBUGOUT("Initializing the IEEE VLAN\n"); 413 mac->ops.clear_vfta(hw); 414 415 /* Setup the receive address. */ 416 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 417 418 /* Zero out the Multicast HASH table */ 419 DEBUGOUT("Zeroing the MTA\n"); 420 for (i = 0; i < mac->mta_reg_count; i++) { 421 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 422 /* 423 * Avoid back to back register writes by adding the register 424 * read (flush). This is to protect against some strange 425 * bridge configurations that may issue Memory Write Block 426 * (MWB) to our register space. 427 */ 428 E1000_WRITE_FLUSH(hw); 429 } 430 431 /* Setup link and flow control */ 432 ret_val = mac->ops.setup_link(hw); 433 434 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 435 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 436 E1000_TXDCTL_FULL_TX_DESC_WB; 437 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 438 439 /* 440 * Clear all of the statistics registers (clear on read). It is 441 * important that we do this after we have tried to establish link 442 * because the symbol error count will increment wildly if there 443 * is no link. 444 */ 445 e1000_clear_hw_cntrs_82541(hw); 446 447 out: 448 return (ret_val); 449 } 450 451 /* 452 * e1000_get_link_up_info_82541 - Report speed and duplex 453 * @hw: pointer to the HW structure 454 * @speed: pointer to speed buffer 455 * @duplex: pointer to duplex buffer 456 * 457 * Retrieve the current speed and duplex configuration. 458 */ 459 static s32 460 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, u16 *duplex) 461 { 462 struct e1000_phy_info *phy = &hw->phy; 463 s32 ret_val; 464 u16 data; 465 466 DEBUGFUNC("e1000_get_link_up_info_82541"); 467 468 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 469 if (ret_val) 470 goto out; 471 472 if (!phy->speed_downgraded) 473 goto out; 474 475 /* 476 * IGP01 PHY may advertise full duplex operation after speed 477 * downgrade even if it is operating at half duplex. 478 * Here we set the duplex settings to match the duplex in the 479 * link partner's capabilities. 480 */ 481 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data); 482 if (ret_val) 483 goto out; 484 485 if (!(data & NWAY_ER_LP_NWAY_CAPS)) { 486 *duplex = HALF_DUPLEX; 487 } else { 488 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data); 489 if (ret_val) 490 goto out; 491 492 if (*speed == SPEED_100) { 493 if (!(data & NWAY_LPAR_100TX_FD_CAPS)) 494 *duplex = HALF_DUPLEX; 495 } else if (*speed == SPEED_10) { 496 if (!(data & NWAY_LPAR_10T_FD_CAPS)) 497 *duplex = HALF_DUPLEX; 498 } 499 } 500 501 out: 502 return (ret_val); 503 } 504 505 /* 506 * e1000_phy_hw_reset_82541 - PHY hardware reset 507 * @hw: pointer to the HW structure 508 * 509 * Verify the reset block is not blocking us from resetting. Acquire 510 * semaphore (if necessary) and read/set/write the device control reset 511 * bit in the PHY. Wait the appropriate delay time for the device to 512 * reset and release the semaphore (if necessary). 513 */ 514 static s32 515 e1000_phy_hw_reset_82541(struct e1000_hw *hw) 516 { 517 s32 ret_val; 518 u32 ledctl; 519 520 DEBUGFUNC("e1000_phy_hw_reset_82541"); 521 522 ret_val = e1000_phy_hw_reset_generic(hw); 523 if (ret_val) 524 goto out; 525 526 (void) e1000_phy_init_script_82541(hw); 527 528 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 529 /* Configure activity LED after PHY reset */ 530 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 531 ledctl &= IGP_ACTIVITY_LED_MASK; 532 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 533 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 534 } 535 536 out: 537 return (ret_val); 538 } 539 540 /* 541 * e1000_setup_copper_link_82541 - Configure copper link settings 542 * @hw: pointer to the HW structure 543 * 544 * Calls the appropriate function to configure the link for auto-neg or forced 545 * speed and duplex. Then we check for link, once link is established calls 546 * to configure collision distance and flow control are called. If link is 547 * not established, we return -E1000_ERR_PHY (-2). 548 */ 549 static s32 550 e1000_setup_copper_link_82541(struct e1000_hw *hw) 551 { 552 struct e1000_phy_info *phy = &hw->phy; 553 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 554 s32 ret_val; 555 u32 ctrl, ledctl; 556 557 DEBUGFUNC("e1000_setup_copper_link_82541"); 558 559 ctrl = E1000_READ_REG(hw, E1000_CTRL); 560 ctrl |= E1000_CTRL_SLU; 561 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 562 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 563 564 hw->phy.reset_disable = false; 565 566 /* Earlier revs of the IGP phy require us to force MDI. */ 567 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { 568 dev_spec->dsp_config = e1000_dsp_config_disabled; 569 phy->mdix = 1; 570 } else { 571 dev_spec->dsp_config = e1000_dsp_config_enabled; 572 } 573 574 ret_val = e1000_copper_link_setup_igp(hw); 575 if (ret_val) 576 goto out; 577 578 if (hw->mac.autoneg) { 579 if (dev_spec->ffe_config == e1000_ffe_config_active) 580 dev_spec->ffe_config = e1000_ffe_config_enabled; 581 } 582 583 /* Configure activity LED after Phy reset */ 584 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 585 ledctl &= IGP_ACTIVITY_LED_MASK; 586 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 587 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 588 589 ret_val = e1000_setup_copper_link_generic(hw); 590 591 out: 592 return (ret_val); 593 } 594 595 /* 596 * e1000_check_for_link_82541 - Check/Store link connection 597 * @hw: pointer to the HW structure 598 * 599 * This checks the link condition of the adapter and stores the 600 * results in the hw->mac structure. 601 */ 602 static s32 603 e1000_check_for_link_82541(struct e1000_hw *hw) 604 { 605 struct e1000_mac_info *mac = &hw->mac; 606 s32 ret_val; 607 bool link; 608 609 DEBUGFUNC("e1000_check_for_link_82541"); 610 611 /* 612 * We only want to go out to the PHY registers to see if Auto-Neg 613 * has completed and/or if our link status has changed. The 614 * get_link_status flag is set upon receiving a Link Status 615 * Change or Rx Sequence Error interrupt. 616 */ 617 if (!mac->get_link_status) { 618 ret_val = E1000_SUCCESS; 619 goto out; 620 } 621 622 /* 623 * First we want to see if the MII Status Register reports 624 * link. If so, then we want to get the current speed/duplex 625 * of the PHY. 626 */ 627 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 628 if (ret_val) 629 goto out; 630 631 if (!link) { 632 ret_val = e1000_config_dsp_after_link_change_82541(hw, false); 633 goto out; /* No link detected */ 634 } 635 636 mac->get_link_status = false; 637 638 /* 639 * Check if there was DownShift, must be checked 640 * immediately after link-up 641 */ 642 (void) e1000_check_downshift_generic(hw); 643 644 /* 645 * If we are forcing speed/duplex, then we simply return since 646 * we have already determined whether we have link or not. 647 */ 648 if (!mac->autoneg) { 649 ret_val = -E1000_ERR_CONFIG; 650 goto out; 651 } 652 653 ret_val = e1000_config_dsp_after_link_change_82541(hw, true); 654 655 /* 656 * Auto-Neg is enabled. Auto Speed Detection takes care 657 * of MAC speed/duplex configuration. So we only need to 658 * configure Collision Distance in the MAC. 659 */ 660 e1000_config_collision_dist_generic(hw); 661 662 /* 663 * Configure Flow Control now that Auto-Neg has completed. 664 * First, we need to restore the desired flow control 665 * settings because we may have had to re-autoneg with a 666 * different link partner. 667 */ 668 ret_val = e1000_config_fc_after_link_up_generic(hw); 669 if (ret_val) { 670 /* EMPTY */ 671 DEBUGOUT("Error configuring flow control\n"); 672 } 673 674 out: 675 return (ret_val); 676 } 677 678 /* 679 * e1000_config_dsp_after_link_change_82541 - Config DSP after link 680 * @hw: pointer to the HW structure 681 * @link_up: boolean flag for link up status 682 * 683 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS 684 * at any other case. 685 * 686 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 687 * gigabit link is achieved to improve link quality. 688 */ 689 static s32 690 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 691 bool link_up) 692 { 693 struct e1000_phy_info *phy = &hw->phy; 694 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 695 s32 ret_val; 696 u32 idle_errs = 0; 697 u16 phy_data, phy_saved_data, speed, duplex, i; 698 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 699 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 700 {IGP01E1000_PHY_AGC_PARAM_A, 701 IGP01E1000_PHY_AGC_PARAM_B, 702 IGP01E1000_PHY_AGC_PARAM_C, 703 IGP01E1000_PHY_AGC_PARAM_D}; 704 705 DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); 706 707 if (link_up) { 708 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 709 if (ret_val) { 710 DEBUGOUT("Error getting link speed and duplex\n"); 711 goto out; 712 } 713 714 if (speed != SPEED_1000) { 715 ret_val = E1000_SUCCESS; 716 goto out; 717 } 718 719 ret_val = phy->ops.get_cable_length(hw); 720 if (ret_val) 721 goto out; 722 723 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && 724 phy->min_cable_length >= 50) { 725 726 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 727 ret_val = phy->ops.read_reg(hw, 728 dsp_reg_array[i], 729 &phy_data); 730 if (ret_val) 731 goto out; 732 733 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 734 735 ret_val = phy->ops.write_reg(hw, 736 dsp_reg_array[i], 737 phy_data); 738 if (ret_val) 739 goto out; 740 } 741 dev_spec->dsp_config = e1000_dsp_config_activated; 742 } 743 744 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || 745 (phy->min_cable_length >= 50)) { 746 ret_val = E1000_SUCCESS; 747 goto out; 748 } 749 750 /* clear previous idle error counts */ 751 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 752 if (ret_val) 753 goto out; 754 755 for (i = 0; i < ffe_idle_err_timeout; i++) { 756 usec_delay(1000); 757 ret_val = phy->ops.read_reg(hw, 758 PHY_1000T_STATUS, 759 &phy_data); 760 if (ret_val) 761 goto out; 762 763 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 764 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 765 dev_spec->ffe_config = e1000_ffe_config_active; 766 767 ret_val = phy->ops.write_reg(hw, 768 IGP01E1000_PHY_DSP_FFE, 769 IGP01E1000_PHY_DSP_FFE_CM_CP); 770 if (ret_val) 771 goto out; 772 break; 773 } 774 775 if (idle_errs) 776 ffe_idle_err_timeout = 777 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 778 } 779 } else { 780 if (dev_spec->dsp_config == e1000_dsp_config_activated) { 781 /* 782 * Save off the current value of register 0x2F5B 783 * to be restored at the end of the routines. 784 */ 785 ret_val = phy->ops.read_reg(hw, 786 0x2F5B, 787 &phy_saved_data); 788 if (ret_val) 789 goto out; 790 791 /* Disable the PHY transmitter */ 792 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 793 if (ret_val) 794 goto out; 795 796 msec_delay_irq(20); 797 798 ret_val = phy->ops.write_reg(hw, 799 0x0000, 800 IGP01E1000_IEEE_FORCE_GIG); 801 if (ret_val) 802 goto out; 803 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 804 ret_val = phy->ops.read_reg(hw, 805 dsp_reg_array[i], 806 &phy_data); 807 if (ret_val) 808 goto out; 809 810 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 811 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 812 813 ret_val = phy->ops.write_reg(hw, 814 dsp_reg_array[i], 815 phy_data); 816 if (ret_val) 817 goto out; 818 } 819 820 ret_val = phy->ops.write_reg(hw, 821 0x0000, 822 IGP01E1000_IEEE_RESTART_AUTONEG); 823 if (ret_val) 824 goto out; 825 826 msec_delay_irq(20); 827 828 /* Now enable the transmitter */ 829 ret_val = phy->ops.write_reg(hw, 830 0x2F5B, 831 phy_saved_data); 832 if (ret_val) 833 goto out; 834 835 dev_spec->dsp_config = e1000_dsp_config_enabled; 836 } 837 838 if (dev_spec->ffe_config != e1000_ffe_config_active) { 839 ret_val = E1000_SUCCESS; 840 goto out; 841 } 842 843 /* 844 * Save off the current value of register 0x2F5B 845 * to be restored at the end of the routines. 846 */ 847 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data); 848 if (ret_val) 849 goto out; 850 851 /* Disable the PHY transmitter */ 852 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 853 if (ret_val) 854 goto out; 855 856 msec_delay_irq(20); 857 858 ret_val = phy->ops.write_reg(hw, 859 0x0000, 860 IGP01E1000_IEEE_FORCE_GIG); 861 if (ret_val) 862 goto out; 863 864 ret_val = phy->ops.write_reg(hw, 865 IGP01E1000_PHY_DSP_FFE, 866 IGP01E1000_PHY_DSP_FFE_DEFAULT); 867 if (ret_val) 868 goto out; 869 870 ret_val = phy->ops.write_reg(hw, 871 0x0000, 872 IGP01E1000_IEEE_RESTART_AUTONEG); 873 if (ret_val) 874 goto out; 875 876 msec_delay_irq(20); 877 878 /* Now enable the transmitter */ 879 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data); 880 881 if (ret_val) 882 goto out; 883 884 dev_spec->ffe_config = e1000_ffe_config_enabled; 885 } 886 887 out: 888 return (ret_val); 889 } 890 891 /* 892 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY 893 * @hw: pointer to the HW structure 894 * 895 * The automatic gain control (agc) normalizes the amplitude of the 896 * received signal, adjusting for the attenuation produced by the 897 * cable. By reading the AGC registers, which represent the 898 * combination of coarse and fine gain value, the value can be put 899 * into a lookup table to obtain the approximate cable length 900 * for each channel. 901 */ 902 static s32 903 e1000_get_cable_length_igp_82541(struct e1000_hw *hw) 904 { 905 struct e1000_phy_info *phy = &hw->phy; 906 s32 ret_val = E1000_SUCCESS; 907 u16 i, data; 908 u16 cur_agc_value, agc_value = 0; 909 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 910 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 911 {IGP01E1000_PHY_AGC_A, 912 IGP01E1000_PHY_AGC_B, 913 IGP01E1000_PHY_AGC_C, 914 IGP01E1000_PHY_AGC_D}; 915 916 DEBUGFUNC("e1000_get_cable_length_igp_82541"); 917 918 /* Read the AGC registers for all channels */ 919 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 920 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data); 921 if (ret_val) 922 goto out; 923 924 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; 925 926 /* Bounds checking */ 927 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 928 (cur_agc_value == 0)) { 929 ret_val = -E1000_ERR_PHY; 930 goto out; 931 } 932 933 agc_value += cur_agc_value; 934 935 if (min_agc_value > cur_agc_value) 936 min_agc_value = cur_agc_value; 937 } 938 939 /* Remove the minimal AGC result for length < 50m */ 940 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { 941 agc_value -= min_agc_value; 942 /* Average the three remaining channels for the length. */ 943 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 944 } else { 945 /* Average the channels for the length. */ 946 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 947 } 948 949 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > 950 IGP01E1000_AGC_RANGE) 951 ? (e1000_igp_cable_length_table[agc_value] - 952 IGP01E1000_AGC_RANGE) 953 : 0; 954 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + 955 IGP01E1000_AGC_RANGE; 956 957 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 958 959 out: 960 return (ret_val); 961 } 962 963 /* 964 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 965 * @hw: pointer to the HW structure 966 * @active: boolean used to enable/disable lplu 967 * 968 * Success returns 0, Failure returns 1 969 * 970 * The low power link up (lplu) state is set to the power management level D3 971 * and SmartSpeed is disabled when active is true, else clear lplu for D3 972 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 973 * is used during Dx states where the power conservation is most important. 974 * During driver activity, SmartSpeed should be enabled so performance is 975 * maintained. 976 */ 977 static s32 978 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active) 979 { 980 struct e1000_phy_info *phy = &hw->phy; 981 s32 ret_val; 982 u16 data; 983 984 DEBUGFUNC("e1000_set_d3_lplu_state_82541"); 985 986 switch (hw->mac.type) { 987 case e1000_82541_rev_2: 988 case e1000_82547_rev_2: 989 break; 990 default: 991 ret_val = e1000_set_d3_lplu_state_generic(hw, active); 992 goto out; 993 } 994 995 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data); 996 if (ret_val) 997 goto out; 998 999 if (!active) { 1000 data &= ~IGP01E1000_GMII_FLEX_SPD; 1001 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 1002 if (ret_val) 1003 goto out; 1004 1005 /* 1006 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1007 * during Dx states where the power conservation is most 1008 * important. During driver activity we should enable 1009 * SmartSpeed, so performance is maintained. 1010 */ 1011 if (phy->smart_speed == e1000_smart_speed_on) { 1012 ret_val = phy->ops.read_reg(hw, 1013 IGP01E1000_PHY_PORT_CONFIG, 1014 &data); 1015 if (ret_val) 1016 goto out; 1017 1018 data |= IGP01E1000_PSCFR_SMART_SPEED; 1019 ret_val = phy->ops.write_reg(hw, 1020 IGP01E1000_PHY_PORT_CONFIG, 1021 data); 1022 if (ret_val) 1023 goto out; 1024 } else if (phy->smart_speed == e1000_smart_speed_off) { 1025 ret_val = phy->ops.read_reg(hw, 1026 IGP01E1000_PHY_PORT_CONFIG, 1027 &data); 1028 if (ret_val) 1029 goto out; 1030 1031 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1032 ret_val = phy->ops.write_reg(hw, 1033 IGP01E1000_PHY_PORT_CONFIG, 1034 data); 1035 if (ret_val) 1036 goto out; 1037 } 1038 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1039 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1040 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1041 data |= IGP01E1000_GMII_FLEX_SPD; 1042 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 1043 if (ret_val) 1044 goto out; 1045 1046 /* When LPLU is enabled, we should disable SmartSpeed */ 1047 ret_val = phy->ops.read_reg(hw, 1048 IGP01E1000_PHY_PORT_CONFIG, 1049 &data); 1050 if (ret_val) 1051 goto out; 1052 1053 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1054 ret_val = phy->ops.write_reg(hw, 1055 IGP01E1000_PHY_PORT_CONFIG, 1056 data); 1057 } 1058 1059 out: 1060 return (ret_val); 1061 } 1062 1063 /* 1064 * e1000_setup_led_82541 - Configures SW controllable LED 1065 * @hw: pointer to the HW structure 1066 * 1067 * This prepares the SW controllable LED for use and saves the current state 1068 * of the LED so it can be later restored. 1069 */ 1070 static s32 1071 e1000_setup_led_82541(struct e1000_hw *hw) 1072 { 1073 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1074 s32 ret_val; 1075 1076 DEBUGFUNC("e1000_setup_led_82541"); 1077 1078 ret_val = hw->phy.ops.read_reg(hw, 1079 IGP01E1000_GMII_FIFO, 1080 &dev_spec->spd_default); 1081 if (ret_val) 1082 goto out; 1083 1084 ret_val = hw->phy.ops.write_reg(hw, 1085 IGP01E1000_GMII_FIFO, 1086 (u16)(dev_spec->spd_default & 1087 ~IGP01E1000_GMII_SPD)); 1088 if (ret_val) 1089 goto out; 1090 1091 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1092 1093 out: 1094 return (ret_val); 1095 } 1096 1097 /* 1098 * e1000_cleanup_led_82541 - Set LED config to default operation 1099 * @hw: pointer to the HW structure 1100 * 1101 * Remove the current LED configuration and set the LED configuration 1102 * to the default value, saved from the EEPROM. 1103 */ 1104 static s32 1105 e1000_cleanup_led_82541(struct e1000_hw *hw) 1106 { 1107 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1108 s32 ret_val; 1109 1110 DEBUGFUNC("e1000_cleanup_led_82541"); 1111 1112 ret_val = hw->phy.ops.write_reg(hw, 1113 IGP01E1000_GMII_FIFO, 1114 dev_spec->spd_default); 1115 if (ret_val) 1116 goto out; 1117 1118 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1119 1120 out: 1121 return (ret_val); 1122 } 1123 1124 /* 1125 * e1000_phy_init_script_82541 - Initialize GbE PHY 1126 * @hw: pointer to the HW structure 1127 * 1128 * Initializes the IGP PHY. 1129 */ 1130 static s32 1131 e1000_phy_init_script_82541(struct e1000_hw *hw) 1132 { 1133 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1134 u32 ret_val; 1135 u16 phy_saved_data; 1136 1137 DEBUGFUNC("e1000_phy_init_script_82541"); 1138 1139 if (!dev_spec->phy_init_script) { 1140 ret_val = E1000_SUCCESS; 1141 goto out; 1142 } 1143 1144 /* Delay after phy reset to enable NVM configuration to load */ 1145 msec_delay(20); 1146 1147 /* 1148 * Save off the current value of register 0x2F5B to be restored at 1149 * the end of this routine. 1150 */ 1151 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data); 1152 1153 /* Disabled the PHY transmitter */ 1154 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003); 1155 1156 msec_delay(20); 1157 1158 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 1159 1160 msec_delay(5); 1161 1162 switch (hw->mac.type) { 1163 case e1000_82541: 1164 case e1000_82547: 1165 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001); 1166 1167 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21); 1168 1169 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018); 1170 1171 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600); 1172 1173 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014); 1174 1175 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C); 1176 1177 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003); 1178 1179 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F); 1180 1181 hw->phy.ops.write_reg(hw, 0x2010, 0x0008); 1182 break; 1183 case e1000_82541_rev_2: 1184 case e1000_82547_rev_2: 1185 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099); 1186 break; 1187 default: 1188 break; 1189 } 1190 1191 hw->phy.ops.write_reg(hw, 0x0000, 0x3300); 1192 1193 msec_delay(20); 1194 1195 /* Now enable the transmitter */ 1196 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data); 1197 1198 if (hw->mac.type == e1000_82547) { 1199 u16 fused, fine, coarse; 1200 1201 /* Move to analog registers page */ 1202 hw->phy.ops.read_reg(hw, 1203 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 1204 &fused); 1205 1206 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 1207 hw->phy.ops.read_reg(hw, 1208 IGP01E1000_ANALOG_FUSE_STATUS, 1209 &fused); 1210 1211 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 1212 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 1213 1214 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 1215 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 1216 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 1217 } else if (coarse == 1218 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 1219 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 1220 1221 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 1222 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 1223 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 1224 1225 hw->phy.ops.write_reg(hw, 1226 IGP01E1000_ANALOG_FUSE_CONTROL, 1227 fused); 1228 hw->phy.ops.write_reg(hw, 1229 IGP01E1000_ANALOG_FUSE_BYPASS, 1230 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 1231 } 1232 } 1233 1234 out: 1235 return (ret_val); 1236 } 1237 1238 /* 1239 * e1000_init_script_state_82541 - Enable/Disable PHY init script 1240 * @hw: pointer to the HW structure 1241 * @state: boolean value used to enable/disable PHY init script 1242 * 1243 * Allows the driver to enable/disable the PHY init script, if the PHY is an 1244 * IGP PHY. 1245 */ 1246 void 1247 e1000_init_script_state_82541(struct e1000_hw *hw, bool state) 1248 { 1249 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1250 1251 DEBUGFUNC("e1000_init_script_state_82541"); 1252 1253 if (hw->phy.type != e1000_phy_igp) { 1254 DEBUGOUT("Initialization script not necessary.\n"); 1255 return; 1256 } 1257 1258 dev_spec->phy_init_script = state; 1259 } 1260 1261 /* 1262 * e1000_fifo_workaround_82547 - Workaround for Tx fifo failure 1263 * @hw: pointer to the HW structure 1264 * @length: length of next outgoing frame 1265 * 1266 * Returns: E1000_ERR_FIFO_WRAP if the next packet cannot be transmitted yet 1267 * E1000_SUCCESS if the next packet can be transmitted 1268 * 1269 * Workaround for the 82547 Tx fifo failure. 1270 */ 1271 s32 1272 e1000_fifo_workaround_82547(struct e1000_hw *hw, u16 length) 1273 { 1274 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1275 u32 tctl; 1276 s32 ret_val = E1000_SUCCESS; 1277 u16 fifo_pkt_len; 1278 1279 DEBUGFUNC("e1000_fifo_workaround_82547"); 1280 1281 if (hw->mac.type != e1000_82547) 1282 goto out; 1283 1284 /* 1285 * Get the length as seen by the FIFO of the next real 1286 * packet to be transmitted. 1287 */ 1288 fifo_pkt_len = E1000_ROUNDUP(length + E1000_FIFO_HDR_SIZE, 1289 E1000_FIFO_GRANULARITY); 1290 1291 if (fifo_pkt_len <= (E1000_FIFO_PAD_82547 + E1000_FIFO_HDR_SIZE)) 1292 goto out; 1293 1294 if ((dev_spec->tx_fifo_head + fifo_pkt_len) < 1295 (dev_spec->tx_fifo_size + E1000_FIFO_PAD_82547)) 1296 goto out; 1297 1298 if (E1000_READ_REG(hw, E1000_TDT(0)) != 1299 E1000_READ_REG(hw, E1000_TDH(0))) { 1300 ret_val = -E1000_ERR_FIFO_WRAP; 1301 goto out; 1302 } 1303 1304 if (E1000_READ_REG(hw, E1000_TDFT) != E1000_READ_REG(hw, E1000_TDFH)) { 1305 ret_val = -E1000_ERR_FIFO_WRAP; 1306 goto out; 1307 } 1308 1309 if (E1000_READ_REG(hw, E1000_TDFTS) != 1310 E1000_READ_REG(hw, E1000_TDFHS)) { 1311 ret_val = -E1000_ERR_FIFO_WRAP; 1312 goto out; 1313 } 1314 1315 /* Disable the tx unit to avoid further pointer movement */ 1316 tctl = E1000_READ_REG(hw, E1000_TCTL); 1317 E1000_WRITE_REG(hw, E1000_TCTL, tctl & ~E1000_TCTL_EN); 1318 1319 /* Reset the fifo pointers. */ 1320 E1000_WRITE_REG(hw, E1000_TDFT, dev_spec->tx_fifo_start); 1321 E1000_WRITE_REG(hw, E1000_TDFH, dev_spec->tx_fifo_start); 1322 E1000_WRITE_REG(hw, E1000_TDFTS, dev_spec->tx_fifo_start); 1323 E1000_WRITE_REG(hw, E1000_TDFHS, dev_spec->tx_fifo_start); 1324 1325 /* Re-enabling tx unit */ 1326 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1327 E1000_WRITE_FLUSH(hw); 1328 1329 dev_spec->tx_fifo_head = 0; 1330 1331 out: 1332 return (ret_val); 1333 } 1334 1335 /* 1336 * e1000_update_tx_fifo_head - Update Tx fifo head pointer 1337 * @hw: pointer to the HW structure 1338 * @length: length of next outgoing frame 1339 * 1340 * Updates the SW calculated Tx FIFO head pointer. 1341 */ 1342 void 1343 e1000_update_tx_fifo_head_82547(struct e1000_hw *hw, u32 length) 1344 { 1345 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1346 1347 DEBUGFUNC("e1000_update_tx_fifo_head_82547"); 1348 1349 if (hw->mac.type != e1000_82547) 1350 return; 1351 1352 dev_spec->tx_fifo_head += E1000_ROUNDUP(length + E1000_FIFO_HDR_SIZE, 1353 E1000_FIFO_GRANULARITY); 1354 1355 if (dev_spec->tx_fifo_head > dev_spec->tx_fifo_size) 1356 dev_spec->tx_fifo_head -= dev_spec->tx_fifo_size; 1357 } 1358 1359 /* 1360 * e1000_set_ttl_workaround_state_82541 - Enable/Disables TTL workaround 1361 * @hw: pointer to the HW structure 1362 * @state: boolean to enable/disable TTL workaround 1363 * 1364 * For 82541 or 82547 only silicon, allows the driver to enable/disable the 1365 * TTL workaround. 1366 */ 1367 void 1368 e1000_set_ttl_workaround_state_82541(struct e1000_hw *hw, bool state) 1369 { 1370 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1371 1372 DEBUGFUNC("e1000_set_ttl_workaround_state_82541"); 1373 1374 if ((hw->mac.type != e1000_82541) && (hw->mac.type != e1000_82547)) 1375 return; 1376 1377 dev_spec->ttl_workaround = state; 1378 } 1379 1380 /* 1381 * e1000_ttl_workaround_enabled_82541 - Returns current TTL workaround status 1382 * @hw: pointer to the HW structure 1383 * 1384 * Returns the current status of the TTL workaround, as to whether the 1385 * workaround is enabled or disabled. 1386 */ 1387 bool 1388 e1000_ttl_workaround_enabled_82541(struct e1000_hw *hw) 1389 { 1390 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1391 bool state = false; 1392 1393 DEBUGFUNC("e1000_ttl_workaround_enabled_82541"); 1394 1395 if ((hw->mac.type != e1000_82541) && (hw->mac.type != e1000_82547)) 1396 goto out; 1397 1398 state = dev_spec->ttl_workaround; 1399 1400 out: 1401 return (state); 1402 } 1403 1404 /* 1405 * e1000_igp_ttl_workaround_82547 - Workaround for long TTL on 100HD hubs 1406 * @hw: pointer to the HW structure 1407 * 1408 * Returns: E1000_ERR_PHY if fail to read/write the PHY 1409 * E1000_SUCCESS in any other case 1410 * 1411 * This function, specific to 82547 hardware only, needs to be called every 1412 * second. It checks if a parallel detect fault has occurred. If a fault 1413 * occurred, disable/enable the DSP reset mechanism up to 5 times (once per 1414 * second). If link is established, stop the workaround and ensure the DSP 1415 * reset is enabled. 1416 */ 1417 s32 1418 e1000_igp_ttl_workaround_82547(struct e1000_hw *hw) 1419 { 1420 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1421 s32 ret_val = E1000_SUCCESS; 1422 u16 phy_data = 0; 1423 u16 dsp_value = DSP_RESET_ENABLE; 1424 bool link; 1425 1426 DEBUGFUNC("e1000_igp_ttl_workaround_82547"); 1427 1428 /* The workaround needed only for B-0 silicon HW */ 1429 if ((hw->mac.type != e1000_82541) && (hw->mac.type != e1000_82547)) 1430 goto out; 1431 1432 if (!(e1000_ttl_workaround_enabled_82541(hw))) 1433 goto out; 1434 1435 /* Check for link first */ 1436 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1437 if (ret_val) 1438 goto out; 1439 1440 if (link) { 1441 /* 1442 * If link is established during the workaround, 1443 * the DSP mechanism must be enabled. 1444 */ 1445 if (dev_spec->dsp_reset_counter) { 1446 dev_spec->dsp_reset_counter = 0; 1447 dsp_value = DSP_RESET_ENABLE; 1448 } else { 1449 ret_val = E1000_SUCCESS; 1450 goto out; 1451 } 1452 } else { 1453 if (dev_spec->dsp_reset_counter == 0) { 1454 /* 1455 * Workaround not activated, 1456 * check if it needs activation 1457 */ 1458 ret_val = hw->phy.ops.read_reg(hw, 1459 PHY_AUTONEG_EXP, 1460 &phy_data); 1461 if (ret_val) 1462 goto out; 1463 /* 1464 * Activate the workaround if there was a 1465 * parallel detect fault 1466 */ 1467 if (phy_data & NWAY_ER_PAR_DETECT_FAULT) { 1468 dev_spec->dsp_reset_counter++; 1469 } else { 1470 ret_val = E1000_SUCCESS; 1471 goto out; 1472 } 1473 } 1474 1475 /* After 5 times, stop the workaround */ 1476 if (dev_spec->dsp_reset_counter > E1000_MAX_DSP_RESETS) { 1477 dev_spec->dsp_reset_counter = 0; 1478 dsp_value = DSP_RESET_ENABLE; 1479 } else { 1480 if (dev_spec->dsp_reset_counter) { 1481 dsp_value = (dev_spec->dsp_reset_counter & 1) 1482 ? DSP_RESET_DISABLE 1483 : DSP_RESET_ENABLE; 1484 dev_spec->dsp_reset_counter++; 1485 } 1486 } 1487 } 1488 1489 ret_val = 1490 hw->phy.ops.write_reg(hw, IGP01E1000_PHY_DSP_RESET, dsp_value); 1491 1492 out: 1493 return (ret_val); 1494 } 1495 1496 /* 1497 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down 1498 * @hw: pointer to the HW structure 1499 * 1500 * In the case of a PHY power down to save power, or to turn off link during a 1501 * driver unload, or wake on lan is not enabled, remove the link. 1502 */ 1503 static void 1504 e1000_power_down_phy_copper_82541(struct e1000_hw *hw) 1505 { 1506 /* If the management interface is not enabled, then power down */ 1507 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 1508 e1000_power_down_phy_copper(hw); 1509 } 1510 1511 /* 1512 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters 1513 * @hw: pointer to the HW structure 1514 * 1515 * Clears the hardware counters by reading the counter registers. 1516 */ 1517 static void 1518 e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) 1519 { 1520 DEBUGFUNC("e1000_clear_hw_cntrs_82541"); 1521 1522 e1000_clear_hw_cntrs_base_generic(hw); 1523 1524 (void) E1000_READ_REG(hw, E1000_PRC64); 1525 (void) E1000_READ_REG(hw, E1000_PRC127); 1526 (void) E1000_READ_REG(hw, E1000_PRC255); 1527 (void) E1000_READ_REG(hw, E1000_PRC511); 1528 (void) E1000_READ_REG(hw, E1000_PRC1023); 1529 (void) E1000_READ_REG(hw, E1000_PRC1522); 1530 (void) E1000_READ_REG(hw, E1000_PTC64); 1531 (void) E1000_READ_REG(hw, E1000_PTC127); 1532 (void) E1000_READ_REG(hw, E1000_PTC255); 1533 (void) E1000_READ_REG(hw, E1000_PTC511); 1534 (void) E1000_READ_REG(hw, E1000_PTC1023); 1535 (void) E1000_READ_REG(hw, E1000_PTC1522); 1536 1537 (void) E1000_READ_REG(hw, E1000_ALGNERRC); 1538 (void) E1000_READ_REG(hw, E1000_RXERRC); 1539 (void) E1000_READ_REG(hw, E1000_TNCRS); 1540 (void) E1000_READ_REG(hw, E1000_CEXTERR); 1541 (void) E1000_READ_REG(hw, E1000_TSCTC); 1542 (void) E1000_READ_REG(hw, E1000_TSCTFC); 1543 1544 (void) E1000_READ_REG(hw, E1000_MGTPRC); 1545 (void) E1000_READ_REG(hw, E1000_MGTPDC); 1546 (void) E1000_READ_REG(hw, E1000_MGTPTC); 1547 } 1548
Indexes created Wed Feb 10 08:04:22 UTC 2010
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