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      1 /*
      2  * This file is provided under a CDDLv1 license.  When using or
      3  * redistributing this file, you may do so under this license.
      4  * In redistributing this file this license must be included
      5  * and no other modification of this header file is permitted.
      6  *
      7  * CDDL LICENSE SUMMARY
      8  *
      9  * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
     10  *
     11  * The contents of this file are subject to the terms of Version
     12  * 1.0 of the Common Development and Distribution License (the "License").
     13  *
     14  * You should have received a copy of the License with this software.
     15  * You can obtain a copy of the License at
     16  *	http://www.opensolaris.org/os/licensing.
     17  * See the License for the specific language governing permissions
     18  * and limitations under the License.
     19  */
     20 
     21 /*
     22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
     23  * Use is subject to license terms of the CDDLv1.
     24  */
     25 
     26 /*
     27  * IntelVersion: 1.10 v3-1-10-1_2009-9-18_Release14-6
     28  */
     29 #ifndef _E1000_80003ES2LAN_H_
     30 #define	_E1000_80003ES2LAN_H_
     31 
     32 #ifdef __cplusplus
     33 extern "C" {
     34 #endif
     35 
     36 #define	E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	0x00
     37 #define	E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	0x02
     38 #define	E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	0x10
     39 #define	E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	0x1F
     40 
     41 #define	E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	0x0008
     42 #define	E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	0x0800
     43 #define	E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	0x0010
     44 
     45 #define	E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
     46 #define	E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	0x0000
     47 #define	E1000_KMRNCTRLSTA_OPMODE_E_IDLE		0x2000
     48 
     49 #define	E1000_KMRNCTRLSTA_OPMODE_MASK		0x000C
     50 #define	E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO	0x0004
     51 
     52 /* Gigabit Carry Extend Padding */
     53 #define	E1000_TCTL_EXT_GCEX_MASK	0x000FFC00
     54 
     55 #define	DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	0x00010000
     56 
     57 #define	DEFAULT_TIPG_IPGT_1000_80003ES2LAN	0x8
     58 #define	DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	0x9
     59 
     60 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
     61 #define	GG82563_PSCR_POLARITY_REVERSAL_DISABLE	0x0002 /* 1=Reversal Disabled */
     62 #define	GG82563_PSCR_CROSSOVER_MODE_MASK	0x0060
     63 #define	GG82563_PSCR_CROSSOVER_MODE_MDI		0x0000 /* 00=Manual MDI */
     64 #define	GG82563_PSCR_CROSSOVER_MODE_MDIX	0x0020 /* 01=Manual MDIX */
     65 #define	GG82563_PSCR_CROSSOVER_MODE_AUTO	0x0060 /* 11=Auto crossover */
     66 
     67 /* PHY Specific Control Register 2 (Page 0, Register 26) */
     68 #define	GG82563_PSCR2_REVERSE_AUTO_NEG		0x2000
     69 						/* 1=Reverse Auto-Negotiation */
     70 
     71 /* MAC Specific Control Register (Page 2, Register 21) */
     72 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
     73 #define	GG82563_MSCR_TX_CLK_MASK		0x0007
     74 #define	GG82563_MSCR_TX_CLK_10MBPS_2_5		0x0004
     75 #define	GG82563_MSCR_TX_CLK_100MBPS_25		0x0005
     76 #define	GG82563_MSCR_TX_CLK_1000MBPS_2_5	0x0006
     77 #define	GG82563_MSCR_TX_CLK_1000MBPS_25		0x0007
     78 
     79 #define	GG82563_MSCR_ASSERT_CRS_ON_TX		0x0010	/* 1=Assert */
     80 
     81 /* DSP Distance Register (Page 5, Register 26) */
     82 /*
     83  * 0 = <50M
     84  * 1 = 50-80M
     85  * 2 = 80-100M
     86  * 3 = 110-140M
     87  * 4 = >140M
     88  */
     89 #define	GG82563_DSPD_CABLE_LENGTH		0x0007
     90 
     91 /* Kumeran Mode Control Register (Page 193, Register 16) */
     92 #define	GG82563_KMCR_PASS_FALSE_CARRIER		0x0800
     93 
     94 /* Max number of times Kumeran read/write should be validated */
     95 #define	GG82563_MAX_KMRN_RETRY			0x5
     96 
     97 /* Power Management Control Register (Page 193, Register 20) */
     98 #define	GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	0x0001
     99 					/* 1=Enable SERDES Electrical Idle */
    100 
    101 /* In-Band Control Register (Page 194, Register 18) */
    102 #define	GG82563_ICR_DIS_PADDING			0x0010	/* Disable Padding */
    103 
    104 #ifdef __cplusplus
    105 }
    106 #endif
    107 
    108 #endif	/* _E1000_80003ES2LAN_H_ */
    109