1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #pragma dictionary "SUN4V" 30 31 /* 32 * Define FITrates for different types of errors. For the ultrSPARC-T2plus 33 * interconnect, they are all defined to provide relative likelihood as 34 * actual FITrates are unavailable. We define them here in case more 35 * accurate values become available in future. 36 */ 37 #define CPU_CHIP_FIT 400 38 #define FPGA_FIT 400 39 #define FIRMWARE_HYPERVISOR_FIT 400 40 #define FIRMWARE_VBSC_FIT 400 41 #define INTERCONNECT_OPU_FIT 400 42 #define INTERCONNECT_LFU_F_FIT 400 43 #define INTERCONNECT_LFU_U_FIT 400 44 #define INTERCONNECT_LFU_C_FIT 400 45 #define INTERCONNECT_GPD_FIT 400 46 #define INTERCONNECT_ASU_FIT 400 47 48 /* 49 * Define propogation delays for the ereports. 50 * 51 * For immediate processing, we specify a very short delay, which seems to 52 * work better than 0. For ereports that are to be ignored, we delay longer, 53 * 1 second. 54 */ 55 #define IGNORE_DELAY 1s 56 #define IMMEDIATE_DELAY 5ms 57 #define SERD_DELAY 1ms 58 #define RETRAIN_DELAY 5s 59 60 61 /* 62 * Test for primary or secondary ereports 63 */ 64 #define IS_PRIMARY (payloadprop("primary")) 65 #define IS_SECONDARY (! payloadprop("primary")) 66 67 68 /* 69 * Tests to determine what CHIP is associated with an ereport 70 */ 71 #define MATCH_CPUID(n) (payloadprop("cpu-nodeid") == n) 72 73 74 /* 75 * SERD values used by the LFU subsystem 76 */ 77 #define LFU_CRC_SERD_N 22 78 #define LFU_CRC_SERD_T 30 min 79 80 81 /* 82 * ASRU and FRU definitions used by this diagnosis engine. 83 */ 84 asru motherboard; 85 asru interconnect; 86 asru chip; 87 fru motherboard; 88 fru cpuboard; 89 90 91 /* 92 * Define the errors that propogate to a CHIP fault. 93 */ 94 event error.cpu.ultraSPARC-T2plus.opu.protocol@chip; 95 event error.cpu.ultraSPARC-T2plus.lfu-c.chip@chip; 96 event error.cpu.ultraSPARC-T2plus.lfu-f.chip@chip; 97 event error.cpu.ultraSPARC-T2plus.lfu-u.chip@chip; 98 event error.cpu.ultraSPARC-T2plus.gpd-u.chip@chip; 99 event error.cpu.ultraSPARC-T2plus.gpd-c.chip@chip; 100 event error.cpu.ultraSPARC-T2plus.asu.protocol@chip; 101 102 event fault.cpu.ultraSPARC-T2plus.chip@chip 103 FITrate=CPU_CHIP_FIT, ASRU=chip, FRU=cpuboard; 104 105 prop fault.cpu.ultraSPARC-T2plus.chip@chip -> 106 error.cpu.ultraSPARC-T2plus.opu.protocol@chip, 107 error.cpu.ultraSPARC-T2plus.lfu-c.chip@chip, 108 error.cpu.ultraSPARC-T2plus.lfu-f.chip@chip, 109 error.cpu.ultraSPARC-T2plus.lfu-u.chip@chip, 110 error.cpu.ultraSPARC-T2plus.gpd-u.chip@chip, 111 error.cpu.ultraSPARC-T2plus.gpd-c.chip@chip, 112 error.cpu.ultraSPARC-T2plus.asu.protocol@chip; 113 114 115 /* 116 * OPU Subsystem 117 */ 118 event ereport.asic.zambezi.opu.ods-ctrl-parity@interconnect 119 {within (IMMEDIATE_DELAY)}; 120 event ereport.asic.zambezi.opu.ods-data-coherent-read@interconnect 121 {within (IMMEDIATE_DELAY)}; 122 event ereport.asic.zambezi.opu.ods-data-coherent-writeback@interconnect 123 {within (IMMEDIATE_DELAY)}; 124 event ereport.asic.zambezi.opu.ods-data-destid@interconnect 125 {within (IMMEDIATE_DELAY)}; 126 event ereport.asic.zambezi.opu.ods-data-parity@interconnect 127 {within (IMMEDIATE_DELAY)}; 128 event ereport.asic.zambezi.opu.oqs-request-bad-nc-type@interconnect 129 {within (IMMEDIATE_DELAY)}; 130 event ereport.asic.zambezi.opu.oqs-request-bad-read-type@interconnect 131 {within (IMMEDIATE_DELAY)}; 132 event ereport.asic.zambezi.opu.oqs-request-bad-writeback-type@interconnect 133 {within (IMMEDIATE_DELAY)}; 134 event ereport.asic.zambezi.opu.oqs-request-duplicate@interconnect 135 {within (IMMEDIATE_DELAY)}; 136 event ereport.asic.zambezi.opu.ors-response-bad-nc-type@interconnect 137 {within (IMMEDIATE_DELAY)}; 138 event ereport.asic.zambezi.opu.ors-response-bad-read-type@interconnect 139 {within (IMMEDIATE_DELAY)}; 140 event ereport.asic.zambezi.opu.ors-response-bad-writeback-type@interconnect 141 {within (IMMEDIATE_DELAY)}; 142 event ereport.asic.zambezi.opu.ors-response-duplicate@interconnect 143 {within (IMMEDIATE_DELAY)}; 144 event ereport.asic.zambezi.opu.ors-response-inconsistent@interconnect 145 {within (IMMEDIATE_DELAY)}; 146 event ereport.asic.zambezi.opu.ors-response-unexpected@interconnect 147 {within (IMMEDIATE_DELAY)}; 148 event ereport.asic.zambezi.opu.ors-timeout-read@interconnect 149 {within (IMMEDIATE_DELAY)}; 150 event ereport.asic.zambezi.opu.ors-timeout-writeback@interconnect 151 {within (IMMEDIATE_DELAY)}; 152 153 154 /* 155 * Declare the intermediate errors that will be generated by the ereports 156 * in this subsystem. These errors will, in turn, propogate to the 157 * appropriate fault. 158 */ 159 event error.asic.ultraSPARC-T2plus.interconnect.opu-u@interconnect; 160 event error.asic.ultraSPARC-T2plus.interconnect.opu-c@interconnect; 161 162 163 /* 164 * This fault is diagnosed for uncorrectible OPU errors 165 */ 166 event fault.asic.ultraSPARC-T2plus.interconnect.opu-u@interconnect 167 FITrate=INTERCONNECT_OPU_FIT, ASRU=interconnect, FRU=motherboard; 168 169 prop error.asic.ultraSPARC-T2plus.interconnect.opu-u@interconnect -> 170 ereport.asic.zambezi.opu.ods-ctrl-parity@interconnect; 171 172 prop fault.asic.ultraSPARC-T2plus.interconnect.opu-u@interconnect -> 173 error.asic.ultraSPARC-T2plus.interconnect.opu-u@interconnect; 174 175 176 /* 177 * This fault is diagnosed for correctible OPU errors. 178 */ 179 event fault.asic.ultraSPARC-T2plus.interconnect.opu-c@interconnect 180 FITrate=INTERCONNECT_OPU_FIT, ASRU=interconnect, FRU=motherboard; 181 182 prop error.asic.ultraSPARC-T2plus.interconnect.opu-c@interconnect -> 183 ereport.asic.zambezi.opu.ods-data-parity@interconnect; 184 185 prop fault.asic.ultraSPARC-T2plus.interconnect.opu-c@interconnect -> 186 error.asic.ultraSPARC-T2plus.interconnect.opu-c@interconnect; 187 188 189 /* 190 * All of the following ereports are associated with a CHIP. Propogate 191 * them to the appropriate error for diagnosis to a CHIP fault, above. 192 */ 193 prop error.cpu.ultraSPARC-T2plus.opu.protocol@chip[chip_num] (0) -> 194 ereport.asic.zambezi.opu.ods-data-destid@interconnect 195 {MATCH_CPUID(chip_num)}, 196 ereport.asic.zambezi.opu.ods-data-coherent-read@interconnect 197 {MATCH_CPUID(chip_num)}, 198 ereport.asic.zambezi.opu.ods-data-coherent-writeback@interconnect 199 {MATCH_CPUID(chip_num)}, 200 ereport.asic.zambezi.opu.oqs-request-bad-read-type@interconnect 201 {MATCH_CPUID(chip_num)}, 202 ereport.asic.zambezi.opu.oqs-request-bad-writeback-type@interconnect 203 {MATCH_CPUID(chip_num)}, 204 ereport.asic.zambezi.opu.oqs-request-bad-nc-type@interconnect 205 {MATCH_CPUID(chip_num)}, 206 ereport.asic.zambezi.opu.oqs-request-duplicate@interconnect 207 {MATCH_CPUID(chip_num)}, 208 ereport.asic.zambezi.opu.ors-response-unexpected@interconnect 209 {MATCH_CPUID(chip_num)}, 210 ereport.asic.zambezi.opu.ors-response-duplicate@interconnect 211 {MATCH_CPUID(chip_num)}, 212 ereport.asic.zambezi.opu.ors-response-inconsistent@interconnect 213 {MATCH_CPUID(chip_num)}, 214 ereport.asic.zambezi.opu.ors-response-bad-read-type@interconnect 215 {MATCH_CPUID(chip_num)}, 216 ereport.asic.zambezi.opu.ors-response-bad-writeback-type@interconnect 217 {MATCH_CPUID(chip_num)}, 218 ereport.asic.zambezi.opu.ors-response-bad-nc-type@interconnect 219 {MATCH_CPUID(chip_num)}, 220 ereport.asic.zambezi.opu.ors-timeout-read@interconnect 221 {MATCH_CPUID(chip_num)}, 222 ereport.asic.zambezi.opu.ors-timeout-writeback@interconnect 223 {MATCH_CPUID(chip_num)}; 224 225 226 227 /* 228 * LFU Subsystem 229 */ 230 event ereport.asic.zambezi.lfu.crc-error@interconnect 231 {within (SERD_DELAY)}; 232 event ereport.asic.zambezi.lfu.data-invalid-or-unmapped@interconnect 233 {within (IMMEDIATE_DELAY)}; 234 event ereport.asic.zambezi.lfu.electric-idle@interconnect 235 {within (RETRAIN_DELAY)}; 236 event ereport.asic.zambezi.lfu.irq-overflow@interconnect 237 {within (IMMEDIATE_DELAY)}; 238 event ereport.asic.zambezi.lfu.irq-parity@interconnect 239 {within (IMMEDIATE_DELAY)}; 240 event ereport.asic.zambezi.lfu.irq-underflow@interconnect 241 {within (IMMEDIATE_DELAY)}; 242 event ereport.asic.zambezi.lfu.lane-failure-slf@interconnect 243 {within (IMMEDIATE_DELAY)}; 244 event ereport.asic.zambezi.lfu.lane-failure-mlf@interconnect 245 {within (IMMEDIATE_DELAY)}; 246 event ereport.asic.zambezi.lfu.link-down-retrain@interconnect 247 {within (RETRAIN_DELAY)}; 248 event ereport.asic.zambezi.lfu.link-down-retrain-failed@interconnect 249 {within (IMMEDIATE_DELAY)}; 250 event ereport.asic.zambezi.lfu.link-down-second-replay@interconnect 251 {within (SERD_DELAY)}; 252 event ereport.asic.zambezi.lfu.link-training-l05@interconnect 253 {within (IMMEDIATE_DELAY)}; 254 event ereport.asic.zambezi.lfu.link-training-config@interconnect 255 {within (IMMEDIATE_DELAY)}; 256 event ereport.asic.zambezi.lfu.link-training-state@interconnect 257 {within (IMMEDIATE_DELAY)}; 258 event ereport.asic.zambezi.lfu.link-training-testing@interconnect 259 {within (IMMEDIATE_DELAY)}; 260 event ereport.asic.zambezi.lfu.replay-lcf-rcvd-error@interconnect 261 {within (RETRAIN_DELAY)}; 262 event ereport.asic.zambezi.lfu.replay-lcf-sent-error@interconnect 263 {within (RETRAIN_DELAY)}; 264 event ereport.asic.zambezi.lfu.replay-parity@interconnect 265 {within (IMMEDIATE_DELAY)}; 266 event ereport.asic.zambezi.lfu.reply-invalid-or-unmapped@interconnect 267 {within (IMMEDIATE_DELAY)}; 268 event ereport.asic.zambezi.lfu.reply-tid-release-set@interconnect 269 {within (IMMEDIATE_DELAY)}; 270 event ereport.asic.zambezi.lfu.retrain-error-disabled@interconnect 271 {within (RETRAIN_DELAY)}; 272 event ereport.asic.zambezi.lfu.retrain-error-resume-timeout@interconnect 273 {within (RETRAIN_DELAY)}; 274 event ereport.asic.zambezi.lfu.retrain-error-second-crc@interconnect 275 {within (RETRAIN_DELAY)}; 276 event ereport.asic.zambezi.lfu.retrain-failed-disabled@interconnect 277 {within (IMMEDIATE_DELAY)}; 278 event ereport.asic.zambezi.lfu.retrain-failed-resume-timeout@interconnect 279 {within (IMMEDIATE_DELAY)}; 280 event ereport.asic.zambezi.lfu.retrain-failed-second-crc@interconnect 281 {within (IMMEDIATE_DELAY)}; 282 283 /* 284 * Declare the intermediate errors that will be generated by the ereports 285 * in this subsystem. These errors will, in turn, propogate to the 286 * appropriate fault. 287 */ 288 event error.asic.ultraSPARC-T2plus.interconnect.lfu-c@interconnect; 289 event error.asic.ultraSPARC-T2plus.interconnect.lfu-f@interconnect; 290 event error.asic.ultraSPARC-T2plus.interconnect.lfu-u@interconnect; 291 event error.asic.ultraSPARC-T2plus.interconnect.lfu.ignore@interconnect; 292 293 294 /* 295 * Declare the upsets that may be diagnosed for the LFU subsystem 296 */ 297 event upset.asic.ultraSPARC-T2plus.interconnect.lfu.ignore@interconnect; 298 299 300 /* 301 * Declare the faults that may be generated for the LFU subsystem. 302 */ 303 event fault.asic.ultraSPARC-T2plus.interconnect.lfu-c@interconnect 304 FITrate=INTERCONNECT_LFU_C_FIT, ASRU=interconnect, FRU=motherboard; 305 306 event fault.asic.ultraSPARC-T2plus.interconnect.lfu-f@interconnect 307 FITrate=INTERCONNECT_LFU_F_FIT, ASRU=interconnect, FRU=motherboard; 308 309 event fault.asic.ultraSPARC-T2plus.interconnect.lfu-u@interconnect 310 FITrate=INTERCONNECT_LFU_U_FIT, ASRU=interconnect, FRU=motherboard; 311 312 /* 313 * Define how the intermediate errors propogate to faults for the LFU 314 * subsystem. 315 */ 316 prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.ignore@interconnect -> 317 error.asic.ultraSPARC-T2plus.interconnect.lfu.ignore@interconnect; 318 319 prop fault.asic.ultraSPARC-T2plus.interconnect.lfu-c@interconnect -> 320 error.asic.ultraSPARC-T2plus.interconnect.lfu-c@interconnect; 321 322 prop fault.asic.ultraSPARC-T2plus.interconnect.lfu-f@interconnect -> 323 error.asic.ultraSPARC-T2plus.interconnect.lfu-f@interconnect; 324 325 prop fault.asic.ultraSPARC-T2plus.interconnect.lfu-u@interconnect -> 326 error.asic.ultraSPARC-T2plus.interconnect.lfu-u@interconnect; 327 328 329 /* 330 * We want to count CRC errors on each connection between an interconnect 331 * and a CHIP. Each interconnect is connected to each CHIP, so we need 16 332 * SERD engines (4 interconnects, and 4 CHIPs). 333 * 334 * The topology does not include interconnect/chip, so we cannot do this 335 * automatically. Instead, we explicitly declare 4 sets of serd engine 336 * propogations, one for each CHIP, and let eversholt expand to all available 337 * interconnects. 338 */ 339 event ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip0@interconnect; 340 event ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip1@interconnect; 341 event ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip2@interconnect; 342 event ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip3@interconnect; 343 344 prop error.asic.ultraSPARC-T2plus.interconnect.lfu-c@interconnect -> 345 ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip0@interconnect, 346 ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip1@interconnect, 347 ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip2@interconnect, 348 ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip3@interconnect; 349 350 /* 351 * CHIP0 SERD rules 352 * 353 * These rules create a SERD engine for the connection between each 354 * interconnect and CHIP 0. 355 */ 356 engine serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip0@interconnect, 357 N=LFU_CRC_SERD_N, T=LFU_CRC_SERD_T, method=persistent, 358 trip=ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip0@interconnect; 359 360 event upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip0@interconnect, 361 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip0@interconnect; 362 363 event upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip0@interconnect, 364 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip0@interconnect; 365 366 prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip0@interconnect -> 367 ereport.asic.zambezi.lfu.crc-error@interconnect 368 {MATCH_CPUID(0)}; 369 370 prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip0@interconnect -> 371 ereport.asic.zambezi.lfu.link-down-second-replay@interconnect 372 {MATCH_CPUID(0)}; 373 374 375 /* 376 * CHIP1 SERD rules 377 * 378 * These rules create a SERD engine for the connection between each 379 * interconnect and CHIP 1. 380 */ 381 engine serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip1@interconnect, 382 N=LFU_CRC_SERD_N, T=LFU_CRC_SERD_T, method=persistent, 383 trip=ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip1@interconnect; 384 385 event upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip1@interconnect, 386 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip1@interconnect; 387 388 event upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip1@interconnect, 389 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip1@interconnect; 390 391 prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip1@interconnect -> 392 ereport.asic.zambezi.lfu.crc-error@interconnect 393 {MATCH_CPUID(1)}; 394 395 prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip1@interconnect -> 396 ereport.asic.zambezi.lfu.link-down-second-replay@interconnect 397 {MATCH_CPUID(1)}; 398 399 400 /* 401 * CHIP2 SERD rules 402 * 403 * These rules create a SERD engine for the connection between each 404 * interconnect and CHIP 2. 405 */ 406 engine serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip2@interconnect, 407 N=LFU_CRC_SERD_N, T=LFU_CRC_SERD_T, method=persistent, 408 trip=ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip2@interconnect; 409 410 event upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip2@interconnect, 411 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip2@interconnect; 412 413 event upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip2@interconnect, 414 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip2@interconnect; 415 416 prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip2@interconnect -> 417 ereport.asic.zambezi.lfu.crc-error@interconnect 418 {MATCH_CPUID(2)}; 419 420 prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip2@interconnect -> 421 ereport.asic.zambezi.lfu.link-down-second-replay@interconnect 422 {MATCH_CPUID(2)}; 423 424 425 /* 426 * CHIP3 SERD rules 427 * 428 * These rules create a SERD engine for the connection between each 429 * interconnect and CHIP 3. 430 */ 431 engine serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip3@interconnect, 432 N=LFU_CRC_SERD_N, T=LFU_CRC_SERD_T, method=persistent, 433 trip=ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip3@interconnect; 434 435 event upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip3@interconnect, 436 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip3@interconnect; 437 438 event upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip3@interconnect, 439 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip3@interconnect; 440 441 prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip3@interconnect -> 442 ereport.asic.zambezi.lfu.crc-error@interconnect 443 {MATCH_CPUID(3)}; 444 445 prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip3@interconnect -> 446 ereport.asic.zambezi.lfu.link-down-second-replay@interconnect 447 {MATCH_CPUID(3)}; 448 449 450 /* 451 * LFU propogations that generate 452 * error.asic.ultraSPARC-T2plus.interconnect.lfu-f@interconnect 453 */ 454 prop error.asic.ultraSPARC-T2plus.interconnect.lfu-f@interconnect -> 455 ereport.asic.zambezi.lfu.lane-failure-slf@interconnect; 456 457 458 /* 459 * LFU propogations that generate 460 * error.cpu.ultraSPARC-T2plus.lfu-f.chip@chip 461 */ 462 prop error.cpu.ultraSPARC-T2plus.lfu-f.chip@chip[chip_num] (0) -> 463 ereport.asic.zambezi.lfu.lane-failure-slf@interconnect 464 {MATCH_CPUID(chip_num)}; 465 466 467 /* 468 * LFU propogations that generate 469 * error.cpu.ultrSPARC-T2plus.lfu-u.chip 470 */ 471 prop error.cpu.ultraSPARC-T2plus.lfu-u.chip@chip[chip_num] (0) -> 472 ereport.asic.zambezi.lfu.lane-failure-mlf@interconnect 473 {MATCH_CPUID(chip_num)}, 474 ereport.asic.zambezi.lfu.link-training-state@interconnect 475 {MATCH_CPUID(chip_num)}, 476 ereport.asic.zambezi.lfu.link-training-testing@interconnect 477 {MATCH_CPUID(chip_num)}, 478 ereport.asic.zambezi.lfu.link-training-config@interconnect 479 {MATCH_CPUID(chip_num)}, 480 ereport.asic.zambezi.lfu.link-training-l05@interconnect 481 {MATCH_CPUID(chip_num)}, 482 ereport.asic.zambezi.lfu.link-down-retrain-failed@interconnect 483 {MATCH_CPUID(chip_num)}, 484 ereport.asic.zambezi.lfu.retrain-failed-second-crc@interconnect 485 {MATCH_CPUID(chip_num)}, 486 ereport.asic.zambezi.lfu.retrain-failed-resume-timeout@interconnect 487 {MATCH_CPUID(chip_num)}, 488 ereport.asic.zambezi.lfu.retrain-failed-disabled@interconnect 489 {MATCH_CPUID(chip_num)}; 490 491 /* 492 * LFU propogations that generate 493 * error.asic.ultraSPARC-T2plus.interconnect.lfu-u@interconnect 494 */ 495 prop error.asic.ultraSPARC-T2plus.interconnect.lfu-u@interconnect -> 496 ereport.asic.zambezi.lfu.lane-failure-mlf@interconnect, 497 ereport.asic.zambezi.lfu.link-training-state@interconnect, 498 ereport.asic.zambezi.lfu.link-training-testing@interconnect, 499 ereport.asic.zambezi.lfu.link-training-config@interconnect, 500 ereport.asic.zambezi.lfu.link-training-l05@interconnect, 501 ereport.asic.zambezi.lfu.link-down-retrain-failed@interconnect, 502 ereport.asic.zambezi.lfu.retrain-failed-second-crc@interconnect, 503 ereport.asic.zambezi.lfu.retrain-failed-resume-timeout@interconnect, 504 ereport.asic.zambezi.lfu.retrain-failed-disabled@interconnect, 505 ereport.asic.zambezi.lfu.replay-parity@interconnect, 506 ereport.asic.zambezi.lfu.irq-parity@interconnect, 507 ereport.asic.zambezi.lfu.irq-underflow@interconnect; 508 509 /* 510 * LFU propogations that generate 511 * error.asic.ultraSPARC-T2plus.interconnect.lfu.ignore@interconnect 512 */ 513 prop error.asic.ultraSPARC-T2plus.interconnect.lfu.ignore@interconnect -> 514 ereport.asic.zambezi.lfu.link-down-retrain@interconnect, 515 ereport.asic.zambezi.lfu.electric-idle@interconnect, 516 ereport.asic.zambezi.lfu.retrain-error-resume-timeout@interconnect, 517 ereport.asic.zambezi.lfu.retrain-error-second-crc@interconnect, 518 ereport.asic.zambezi.lfu.retrain-error-disabled@interconnect, 519 ereport.asic.zambezi.lfu.replay-lcf-rcvd-error@interconnect, 520 ereport.asic.zambezi.lfu.replay-lcf-sent-error@interconnect; 521 522 523 /* 524 * LFU propogations that generate 525 * error.cpu.ultraSPARC-T2plus.lfu-c.chip@chip 526 */ 527 prop error.cpu.ultraSPARC-T2plus.lfu-c.chip@chip[chip_num] (0) -> 528 ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip0@interconnect 529 {chip_num == 0}, 530 ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip1@interconnect 531 {chip_num == 1}, 532 ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip2@interconnect 533 {chip_num == 2}, 534 ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip3@interconnect 535 {chip_num == 3}, 536 ereport.asic.zambezi.lfu.data-invalid-or-unmapped@interconnect 537 {MATCH_CPUID(chip_num)}, 538 ereport.asic.zambezi.lfu.reply-invalid-or-unmapped@interconnect 539 {MATCH_CPUID(chip_num)}, 540 ereport.asic.zambezi.lfu.reply-tid-release-set@interconnect 541 {MATCH_CPUID(chip_num)}, 542 ereport.asic.zambezi.lfu.irq-overflow@interconnect 543 {MATCH_CPUID(chip_num)}; 544 545 546 /* 547 * GPD Subsystem 548 */ 549 event ereport.asic.zambezi.gpd.jtag-access-violation@interconnect 550 {within(IMMEDIATE_DELAY)}; 551 event ereport.asic.zambezi.gpd.jtag-mapped-timeout@interconnect 552 {within(IMMEDIATE_DELAY)}; 553 event ereport.asic.zambezi.gpd.link-access-violation@interconnect 554 {within(IMMEDIATE_DELAY)}; 555 event ereport.asic.zambezi.gpd.link-invalid-read-request@interconnect 556 {within(IMMEDIATE_DELAY)}; 557 event ereport.asic.zambezi.gpd.link-invalid-write-request@interconnect 558 {within(IMMEDIATE_DELAY)}; 559 event ereport.asic.zambezi.gpd.link-mapped-timeout@interconnect 560 {within(IMMEDIATE_DELAY)}; 561 event ereport.asic.zambezi.gpd.link-unexpected-data-rcvd@interconnect 562 {within(IMMEDIATE_DELAY)}; 563 event ereport.asic.zambezi.gpd.link-unexpected-request-rcvd@interconnect 564 {within(IMMEDIATE_DELAY)}; 565 event ereport.asic.zambezi.gpd.link-write-data-bytemask-error@interconnect 566 {within(IMMEDIATE_DELAY)}; 567 event ereport.asic.zambezi.gpd.link-write-data-c2c-set@interconnect 568 {within(IMMEDIATE_DELAY)}; 569 event ereport.asic.zambezi.gpd.link-write-data-chunk-error@interconnect 570 {within(IMMEDIATE_DELAY)}; 571 event ereport.asic.zambezi.gpd.link-write-data-error-bit-set@interconnect 572 {within(IMMEDIATE_DELAY)}; 573 event ereport.asic.zambezi.gpd.link-write-data-timeout@interconnect 574 {within(IMMEDIATE_DELAY)}; 575 event ereport.asic.zambezi.gpd.link-write-request-tid-invalid@interconnect 576 {within(IMMEDIATE_DELAY)}; 577 event ereport.asic.zambezi.gpd.link-write-request-timeout@interconnect 578 {within(IMMEDIATE_DELAY)}; 579 event ereport.asic.zambezi.gpd.link-write-tid-invalid@interconnect 580 {within(IMMEDIATE_DELAY)}; 581 event ereport.asic.zambezi.gpd.lpc-access-violation@interconnect 582 {within(IMMEDIATE_DELAY)}; 583 event ereport.asic.zambezi.gpd.lpc-invalid-abort@interconnect 584 {within(IMMEDIATE_DELAY)}; 585 event ereport.asic.zambezi.gpd.lpc-invalid-cycle-type@interconnect 586 {within(IMMEDIATE_DELAY)}; 587 event ereport.asic.zambezi.gpd.lpc-invalid-start@interconnect 588 {within(IMMEDIATE_DELAY)}; 589 event ereport.asic.zambezi.gpd.lpc-mapped-timeout@interconnect 590 {within(IMMEDIATE_DELAY)}; 591 event ereport.asic.zambezi.gpd.lpc-rw-interleave-error@interconnect 592 {within(IMMEDIATE_DELAY)}; 593 594 /* 595 * Declare the intermediate errors that will be generated by the ereports 596 * in this subsystem. These errors will, in turn, propogate to the 597 * appropriate fault. 598 */ 599 event error.asic.fpga@motherboard; 600 event error.asic.ultraSPARC-T2plus.interconnect.gpd@interconnect; 601 event error.asic.ultraSPARC-T2plus.interconnect.gpd.ignore@interconnect; 602 event error.asic.ultraSPARC-T2plus.interconnect.gpd-c@interconnect; 603 event error.asic.ultraSPARC-T2plus.interconnect.gpd-u@interconnect; 604 605 606 /* 607 * Declare the upsets that may be diagnosed for this subsystem 608 */ 609 event upset.asic.ultraSPARC-T2plus.interconnect.gpd.ignore@interconnect; 610 611 612 /* 613 * Declare the faults that may be generated for this subsystem. 614 */ 615 event fault.asic.fpga@motherboard 616 FITrate=FPGA_FIT, ASRU=motherboard, FRU=motherboard; 617 618 event fault.asic.ultraSPARC-T2plus.interconnect.gpd-c@interconnect 619 FITrate=INTERCONNECT_GPD_FIT, ASRU=interconnect, FRU=motherboard; 620 621 event fault.asic.ultraSPARC-T2plus.interconnect.gpd-u@interconnect 622 FITrate=INTERCONNECT_GPD_FIT, ASRU=interconnect, FRU=motherboard; 623 624 625 /* 626 * Define how the intermediate errors propogate to faults for this subsystem. 627 */ 628 prop fault.asic.fpga@motherboard -> 629 error.asic.fpga@motherboard; 630 631 prop upset.asic.ultraSPARC-T2plus.interconnect.gpd.ignore@interconnect -> 632 error.asic.ultraSPARC-T2plus.interconnect.gpd.ignore@interconnect; 633 634 prop fault.asic.ultraSPARC-T2plus.interconnect.gpd-u@interconnect -> 635 error.asic.ultraSPARC-T2plus.interconnect.gpd-u@interconnect; 636 637 prop fault.asic.ultraSPARC-T2plus.interconnect.gpd-c@interconnect -> 638 error.asic.ultraSPARC-T2plus.interconnect.gpd@interconnect, 639 error.asic.ultraSPARC-T2plus.interconnect.gpd-c@interconnect; 640 641 /* 642 * GPD suspect list 643 * fault.asic.ultraSPARC-T2plus.interconnect.gpd-u 644 * fault.cpu.ultraSPARC-T2plus.chip 645 * 646 * Events in this list are diagnosed only if they are primary errors. 647 * The necessary information is unavailable for secondary errors, so 648 * they are logged but not diagnosed. 649 */ 650 prop error.cpu.ultraSPARC-T2plus.gpd-u.chip@chip[chip_num] (0) -> 651 ereport.asic.zambezi.gpd.link-write-request-timeout@interconnect 652 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 653 ereport.asic.zambezi.gpd.link-write-data-timeout@interconnect 654 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 655 ereport.asic.zambezi.gpd.link-write-request-tid-invalid@interconnect 656 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 657 ereport.asic.zambezi.gpd.link-unexpected-data-rcvd@interconnect 658 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 659 ereport.asic.zambezi.gpd.link-unexpected-request-rcvd@interconnect 660 {IS_PRIMARY && MATCH_CPUID(chip_num)}; 661 662 prop error.cpu.ultraSPARC-T2plus.gpd-c.chip@chip[chip_num] (0) -> 663 ereport.asic.zambezi.gpd.link-write-tid-invalid@interconnect 664 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 665 ereport.asic.zambezi.gpd.link-write-data-chunk-error@interconnect 666 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 667 ereport.asic.zambezi.gpd.link-write-data-c2c-set@interconnect 668 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 669 ereport.asic.zambezi.gpd.link-write-data-error-bit-set@interconnect 670 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 671 ereport.asic.zambezi.gpd.link-invalid-write-request@interconnect 672 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 673 ereport.asic.zambezi.gpd.link-write-data-bytemask-error@interconnect 674 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 675 ereport.asic.zambezi.gpd.link-mapped-timeout@interconnect 676 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 677 ereport.asic.zambezi.gpd.link-access-violation@interconnect 678 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 679 ereport.asic.zambezi.gpd.link-invalid-read-request@interconnect 680 {IS_PRIMARY && MATCH_CPUID(chip_num)}; 681 682 prop error.asic.ultraSPARC-T2plus.interconnect.gpd-u@interconnect -> 683 ereport.asic.zambezi.gpd.link-write-request-timeout@interconnect 684 {IS_PRIMARY}, 685 ereport.asic.zambezi.gpd.link-write-data-timeout@interconnect 686 {IS_PRIMARY}, 687 ereport.asic.zambezi.gpd.link-write-request-tid-invalid@interconnect 688 {IS_PRIMARY}, 689 ereport.asic.zambezi.gpd.link-unexpected-data-rcvd@interconnect 690 {IS_PRIMARY}, 691 ereport.asic.zambezi.gpd.link-unexpected-request-rcvd@interconnect 692 {IS_PRIMARY}; 693 694 prop error.asic.ultraSPARC-T2plus.interconnect.gpd.ignore@interconnect -> 695 ereport.asic.zambezi.gpd.link-write-request-timeout@interconnect 696 {IS_SECONDARY}, 697 ereport.asic.zambezi.gpd.link-write-data-timeout@interconnect 698 {IS_SECONDARY}, 699 ereport.asic.zambezi.gpd.link-write-request-tid-invalid@interconnect 700 {IS_SECONDARY}, 701 ereport.asic.zambezi.gpd.link-unexpected-data-rcvd@interconnect 702 {IS_SECONDARY}, 703 ereport.asic.zambezi.gpd.link-unexpected-request-rcvd@interconnect 704 {IS_SECONDARY}, 705 ereport.asic.zambezi.gpd.link-write-tid-invalid@interconnect 706 {IS_SECONDARY}, 707 ereport.asic.zambezi.gpd.link-write-data-chunk-error@interconnect 708 {IS_SECONDARY}, 709 ereport.asic.zambezi.gpd.link-write-data-c2c-set@interconnect 710 {IS_SECONDARY}, 711 ereport.asic.zambezi.gpd.link-write-data-error-bit-set@interconnect 712 {IS_SECONDARY}, 713 ereport.asic.zambezi.gpd.link-invalid-write-request@interconnect 714 {IS_SECONDARY}, 715 ereport.asic.zambezi.gpd.link-write-data-bytemask-error@interconnect 716 {IS_SECONDARY}, 717 ereport.asic.zambezi.gpd.link-mapped-timeout@interconnect 718 {IS_SECONDARY}, 719 ereport.asic.zambezi.gpd.link-access-violation@interconnect 720 {IS_SECONDARY}, 721 ereport.asic.zambezi.gpd.link-invalid-read-request@interconnect 722 {IS_SECONDARY}; 723 724 prop error.asic.ultraSPARC-T2plus.interconnect.gpd-c@interconnect -> 725 ereport.asic.zambezi.gpd.link-write-tid-invalid@interconnect 726 {IS_PRIMARY}, 727 ereport.asic.zambezi.gpd.link-write-data-chunk-error@interconnect 728 {IS_PRIMARY}, 729 ereport.asic.zambezi.gpd.link-write-data-c2c-set@interconnect 730 {IS_PRIMARY}, 731 ereport.asic.zambezi.gpd.link-write-data-error-bit-set@interconnect 732 {IS_PRIMARY}, 733 ereport.asic.zambezi.gpd.link-invalid-write-request@interconnect 734 {IS_PRIMARY}, 735 ereport.asic.zambezi.gpd.link-write-data-bytemask-error@interconnect 736 {IS_PRIMARY}, 737 ereport.asic.zambezi.gpd.link-mapped-timeout@interconnect 738 {IS_PRIMARY}, 739 ereport.asic.zambezi.gpd.link-access-violation@interconnect 740 {IS_PRIMARY}, 741 ereport.asic.zambezi.gpd.link-invalid-read-request@interconnect 742 {IS_PRIMARY}; 743 744 prop error.asic.ultraSPARC-T2plus.interconnect.gpd@interconnect -> 745 ereport.asic.zambezi.gpd.jtag-access-violation@interconnect, 746 ereport.asic.zambezi.gpd.jtag-mapped-timeout@interconnect, 747 ereport.asic.zambezi.gpd.lpc-mapped-timeout@interconnect, 748 ereport.asic.zambezi.gpd.lpc-access-violation@interconnect, 749 ereport.asic.zambezi.gpd.lpc-rw-interleave-error@interconnect, 750 ereport.asic.zambezi.gpd.lpc-invalid-abort@interconnect, 751 ereport.asic.zambezi.gpd.lpc-invalid-start@interconnect, 752 ereport.asic.zambezi.gpd.lpc-invalid-cycle-type@interconnect; 753 754 prop error.asic.fpga@motherboard (0) -> 755 ereport.asic.zambezi.gpd.lpc-invalid-abort@interconnect, 756 ereport.asic.zambezi.gpd.lpc-invalid-start@interconnect, 757 ereport.asic.zambezi.gpd.lpc-invalid-cycle-type@interconnect; 758 759 760 /* 761 * ASU Subsystem 762 */ 763 event ereport.asic.zambezi.asu.cam-parity-error@interconnect 764 {within(IMMEDIATE_DELAY)}; 765 event ereport.asic.zambezi.asu.invalid-nc-destid@interconnect 766 {within(IMMEDIATE_DELAY)}; 767 event ereport.asic.zambezi.asu.invalid-tid-cacheable@interconnect 768 {within(IMMEDIATE_DELAY)}; 769 event ereport.asic.zambezi.asu.invalid-tid-non-cacheable@interconnect 770 {within(IMMEDIATE_DELAY)}; 771 event ereport.asic.zambezi.asu.invalid-wb-destid@interconnect 772 {within(IMMEDIATE_DELAY)}; 773 event ereport.asic.zambezi.asu.malformed-wb@interconnect 774 {within(IMMEDIATE_DELAY)}; 775 event ereport.asic.zambezi.asu.pending-ram-parity-error@interconnect 776 {within(IMMEDIATE_DELAY)}; 777 event ereport.asic.zambezi.asu.pending-tid-ram-parity-error@interconnect 778 {within(IMMEDIATE_DELAY)}; 779 780 /* 781 * Declare the intermediate errors that will be generated by the ereports 782 * in this subsystem. These errors will, in turn, propogate to the 783 * appropriate fault. 784 */ 785 event error.asic.ultraSPARC-T2plus.interconnect.asu.ignore@interconnect; 786 event error.asic.ultraSPARC-T2plus.interconnect.asu@interconnect; 787 788 789 /* 790 * Declare the upsets that may be diagnosed for this subsystem 791 */ 792 event upset.asic.ultraSPARC-T2plus.interconnect.asu.ignore@interconnect; 793 794 795 /* 796 * Declare the faults that may be generated for this subsystem. 797 */ 798 event fault.asic.ultraSPARC-T2plus.interconnect.asu@interconnect 799 FITrate=INTERCONNECT_ASU_FIT, ASRU=interconnect, FRU=motherboard; 800 801 802 /* 803 * Define how the intermediate errors propogate to faults for this subsystem. 804 */ 805 prop upset.asic.ultraSPARC-T2plus.interconnect.asu.ignore@interconnect -> 806 error.asic.ultraSPARC-T2plus.interconnect.asu.ignore@interconnect; 807 808 prop fault.asic.ultraSPARC-T2plus.interconnect.asu@interconnect -> 809 error.asic.ultraSPARC-T2plus.interconnect.asu@interconnect; 810 811 812 prop error.cpu.ultraSPARC-T2plus.asu.protocol@chip[chip_num] (0) -> 813 ereport.asic.zambezi.asu.invalid-nc-destid@interconnect 814 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 815 ereport.asic.zambezi.asu.invalid-tid-non-cacheable@interconnect 816 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 817 ereport.asic.zambezi.asu.invalid-wb-destid@interconnect 818 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 819 ereport.asic.zambezi.asu.malformed-wb@interconnect 820 {IS_PRIMARY && MATCH_CPUID(chip_num)}, 821 ereport.asic.zambezi.asu.invalid-tid-cacheable@interconnect 822 {IS_PRIMARY && MATCH_CPUID(chip_num)}; 823 824 prop error.asic.ultraSPARC-T2plus.interconnect.asu.ignore@interconnect -> 825 ereport.asic.zambezi.asu.invalid-nc-destid@interconnect 826 {IS_SECONDARY}, 827 ereport.asic.zambezi.asu.invalid-tid-non-cacheable@interconnect 828 {IS_SECONDARY}, 829 ereport.asic.zambezi.asu.invalid-wb-destid@interconnect 830 {IS_SECONDARY}, 831 ereport.asic.zambezi.asu.malformed-wb@interconnect 832 {IS_SECONDARY}, 833 ereport.asic.zambezi.asu.invalid-tid-cacheable@interconnect 834 {IS_SECONDARY}; 835 836 prop error.asic.ultraSPARC-T2plus.interconnect.asu@interconnect -> 837 ereport.asic.zambezi.asu.pending-ram-parity-error@interconnect, 838 ereport.asic.zambezi.asu.pending-tid-ram-parity-error@interconnect, 839 ereport.asic.zambezi.asu.cam-parity-error@interconnect; 840
Indexes created Wed Feb 10 02:29:26 UTC 2010
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