1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma dictionary "INTEL" 28 29 /* 30 * Eversholt rules for the intel CPU/Memory 31 */ 32 33 /* 34 * Ereports for Simple error codes. 35 */ 36 37 #define SMPL_EVENT(leafclass, t) \ 38 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) } 39 40 SMPL_EVENT(unknown, 1s); 41 SMPL_EVENT(unclassified, 1s); 42 SMPL_EVENT(microcode_rom_parity, 1s); 43 SMPL_EVENT(external, 1s); 44 SMPL_EVENT(frc, 1s); 45 SMPL_EVENT(internal_timer, 1s); 46 SMPL_EVENT(internal_parity, 1s); 47 SMPL_EVENT(internal_unclassified, 1s); 48 49 /* 50 * Propogations for all but "external" and "unknown" simple errors. 51 * If the error is uncorrected we produce a fault immediately, otherwise 52 * we diagnose it to an upset and decalre a fault when the SERD engine 53 * trips. prop statement for ereport.cpu.intel.internal_unclassified is 54 * moved to the Nehalem EX section to deal with poison case. 55 */ 56 57 engine serd.cpu.intel.simple@chip/core/strand, N=3, T=72h; 58 event fault.cpu.intel.internal@chip/core/strand, 59 engine=serd.cpu.intel.simple@chip/core/strand; 60 61 prop fault.cpu.intel.internal@chip/core/strand 62 { payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1} (0)-> 63 ereport.cpu.intel.microcode_rom_parity@chip/core/strand, 64 ereport.cpu.intel.internal_timer@chip/core/strand, 65 ereport.cpu.intel.internal_parity@chip/core/strand, 66 ereport.cpu.intel.unclassified@chip/core/strand, 67 ereport.cpu.intel.frc@chip/core/strand; 68 69 /* 70 * Ereports for Compound error codes. These are in pairs "foo" and "foo_uc" 71 * for the corrected and uncorrected version of each error type. All are 72 * detected at chip/core/strand. 73 */ 74 75 #define CMPND_EVENT(leafclass, t) \ 76 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) }; \ 77 event ereport.cpu.intel.leafclass/**/_uc@chip/core/strand { within(t) } 78 79 /* 80 * Ereports for Compound error codes - intel errors 81 */ 82 CMPND_EVENT(l0cache, 1s); 83 CMPND_EVENT(l1cache, 1s); 84 CMPND_EVENT(l2cache, 1s); 85 CMPND_EVENT(cache, 1s); 86 87 /* 88 * Ereports for Compound error codes - TLB errors 89 */ 90 CMPND_EVENT(l0dtlb, 1s); 91 CMPND_EVENT(l1dtlb, 1s); 92 CMPND_EVENT(l2dtlb, 1s); 93 CMPND_EVENT(dtlb, 1s); 94 95 CMPND_EVENT(l0itlb, 1s); 96 CMPND_EVENT(l1itlb, 1s); 97 CMPND_EVENT(l2itlb, 1s); 98 CMPND_EVENT(itlb, 1s); 99 100 CMPND_EVENT(l0tlb, 1s); 101 CMPND_EVENT(l1tlb, 1s); 102 CMPND_EVENT(l2tlb, 1s); 103 CMPND_EVENT(tlb, 1s); 104 105 /* 106 * Ereports for Compound error codes - memory hierarchy errors 107 */ 108 CMPND_EVENT(l0dcache, 1s); 109 CMPND_EVENT(l1dcache, 1s); 110 CMPND_EVENT(l2dcache, 1s); 111 CMPND_EVENT(dcache, 1s); 112 113 CMPND_EVENT(l0icache, 1s); 114 CMPND_EVENT(l1icache, 1s); 115 CMPND_EVENT(l2icache, 1s); 116 CMPND_EVENT(icache, 1s); 117 118 /* 119 * Ereports for Compound error codes - bus and interconnect errors 120 */ 121 CMPND_EVENT(bus_interconnect, 1s); 122 CMPND_EVENT(bus_interconnect_memory, 1s); 123 CMPND_EVENT(bus_interconnect_io, 1s); 124 125 /* 126 * Compound error propogations. 127 * 128 * We resist the temptation propogate, for example, a single dcache fault 129 * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache). 130 * Instead we will diagnose a distinct fault for each possible cache level, 131 * whether or not current chips have dcaches at all levels. 132 * 133 * Corrected errors are SERDed and produce a fault when the engine fires; 134 * the same fault is diagnosed immediately for a corresponding uncorrected 135 * error. 136 */ 137 138 #define CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t) \ 139 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 140 event fault.cpu.intel.fltleaf@chip/core/strand, \ 141 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 142 \ 143 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 144 ereport.cpu.intel.erptleaf@chip/core/strand; \ 145 \ 146 prop fault.cpu.intel.fltleaf@chip/core/strand \ 147 { setserdincrement(n + 1) } (0)-> \ 148 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 149 150 #define CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t) \ 151 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 152 event fault.cpu.intel.fltleaf@chip/core/strand, retire=0, response=0,\ 153 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 154 \ 155 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 156 ereport.cpu.intel.erptleaf@chip/core/strand; \ 157 \ 158 prop fault.cpu.intel.fltleaf@chip/core/strand \ 159 { setserdincrement(n + 1) } (0)-> \ 160 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 161 162 CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h); 163 CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h); 164 CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h); 165 CMPND_FLT_PROP_1(cache, cache, 12, 72h); 166 167 CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h); 168 CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h); 169 CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h); 170 CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h); 171 172 CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h); 173 CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h); 174 CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h); 175 CMPND_FLT_PROP_1(itlb, itlb, 12, 72h); 176 177 CMPND_FLT_PROP_1(l0tlb, l0tlb, 3, 72h); 178 CMPND_FLT_PROP_1(l1tlb, l1tlb, 3, 72h); 179 CMPND_FLT_PROP_1(l2tlb, l2tlb, 3, 72h); 180 CMPND_FLT_PROP_1(tlb, tlb, 12, 72h); 181 182 CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h); 183 CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h); 184 CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h); 185 CMPND_FLT_PROP_1(dcache, dcache, 12, 72h); 186 187 CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h); 188 CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h); 189 CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h); 190 CMPND_FLT_PROP_1(icache, icache, 12, 72h); 191 192 CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h); 193 CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h); 194 CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h); 195 196 event upset.discard@chip/core/strand; 197 198 prop upset.discard@chip/core/strand (0)-> 199 ereport.cpu.intel.external@chip/core/strand, 200 ereport.cpu.intel.unknown@chip/core/strand; 201 202 /* errors detected in northbridge */ 203 204 205 /* 206 * SET_ADDR and SET_OFFSET are used to set a payload value in the fault that 207 * we diagnose for page faults, to record the physical address of the faulting 208 * page. 209 */ 210 #define SET_ADDR (!payloadprop_defined("physaddr") || \ 211 setpayloadprop("asru-physaddr", payloadprop("physaddr"))) 212 213 #define SET_OFFSET (!payloadprop_defined("offset") || \ 214 setpayloadprop("asru-offset", payloadprop("offset"))) 215 216 #define EREPORT_BUS_ERROR \ 217 ereport.cpu.intel.bus_interconnect_memory_uc@chip/core/strand, \ 218 ereport.cpu.intel.bus_interconnect_uc@chip/core/strand, \ 219 ereport.cpu.intel.bus_interconnect_memory@chip/core/strand, \ 220 ereport.cpu.intel.bus_interconnect@chip/core/strand, \ 221 ereport.cpu.intel.external@chip/core/strand 222 223 engine stat.ce_pgflt@memory-controller/dram-channel/dimm; 224 225 event ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller{within(12s)}; 226 event ereport.cpu.intel.nb.ddr2_mem_ue@ 227 motherboard/memory-controller{within(12s)}; 228 event ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller{within(12s)}; 229 event fault.memory.intel.page_ue@ 230 motherboard/memory-controller/dram-channel/dimm/rank, 231 message=0, response=0; 232 event fault.memory.intel.dimm_ue@ 233 motherboard/memory-controller/dram-channel/dimm/rank; 234 235 prop fault.memory.intel.page_ue@ 236 motherboard/memory-controller/dram-channel/dimm/rank[rank_num] 237 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 238 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 239 SET_ADDR && SET_OFFSET } (1)-> 240 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 241 ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller, 242 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 243 244 prop fault.memory.intel.dimm_ue@ 245 motherboard/memory-controller/dram-channel/dimm/rank[rank_num] 246 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 247 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 248 ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller, 249 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 250 251 event upset.memory.intel.discard@motherboard/memory-controller{within(1s)}; 252 253 prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 254 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 255 ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller, 256 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 257 258 prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 259 EREPORT_BUS_ERROR; 260 261 #define PAGE_CE_COUNT 2 262 #define PAGE_CE_TIME 72h 263 #define DIMM_CE_COUNT 10 264 #define DIMM_CE_TIME 1week 265 266 #define MBDIMM motherboard/memory-controller/dram-channel/dimm 267 event ereport.cpu.intel.nb.mem_ce@MBDIMM/rank{within(12s)}; 268 event ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank{within(12s)}; 269 event ereport.cpu.intel.nb.ddr2_mem_ce@ 270 motherboard/memory-controller{within(12s)}; 271 272 engine serd.memory.intel.page_ce@MBDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 273 event fault.memory.intel.page_ce@MBDIMM/rank, message=0, response=0, 274 count=stat.ce_pgflt@MBDIMM, engine=serd.memory.intel.page_ce@MBDIMM/rank; 275 prop fault.memory.intel.page_ce@MBDIMM/rank 276 { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 277 SET_ADDR && SET_OFFSET } (0)-> 278 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, 279 ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank; 280 281 engine serd.memory.intel.dimm_ce@MBDIMM/rank, N=DIMM_CE_COUNT, T=DIMM_CE_TIME; 282 event fault.memory.intel.dimm_ce@MBDIMM/rank, 283 engine=serd.memory.intel.dimm_ce@MBDIMM/rank; 284 prop fault.memory.intel.dimm_ce@MBDIMM/rank 285 { !confprop_defined(MBDIMM, "dimm-size") && 286 count(stat.ce_pgflt@MBDIMM) > 512 } (1)-> 287 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, 288 ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank; 289 #define DIMM_CE(dimm_size, n, t, fault_rate) \ 290 prop fault.memory.intel.dimm_ce@MBDIMM/rank { \ 291 confprop(MBDIMM, "dimm-size") == dimm_size && \ 292 count(stat.ce_pgflt@MBDIMM) > fault_rate && \ 293 setserdn(n) & setserdt(t) } (1)-> \ 294 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, \ 295 ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank; 296 297 DIMM_CE("8G", 8, 1week, 2000) 298 DIMM_CE("4G", 4, 1week, 1500) 299 DIMM_CE("2G", 4, 2week, 1000) 300 DIMM_CE("1G", 4, 4week, 500) 301 DIMM_CE("512M", 4, 8week, 250) 302 DIMM_CE("256M", 4, 16week, 125) 303 304 prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 305 ereport.cpu.intel.nb.ddr2_mem_ce@motherboard/memory-controller; 306 307 event ereport.cpu.intel.nb.fbd.alert@rank{within(12s)}; 308 event fault.memory.intel.fbd.alert@rank, retire=0; 309 310 prop fault.memory.intel.fbd.alert@rank (1)-> 311 ereport.cpu.intel.nb.fbd.alert@rank; 312 313 prop fault.memory.intel.fbd.alert@rank (0)-> 314 EREPORT_BUS_ERROR; 315 316 event ereport.cpu.intel.nb.fbd.crc@rank{within(12s)}; 317 event fault.memory.intel.fbd.crc@rank, retire=0; 318 319 prop fault.memory.intel.fbd.crc@rank (1)-> 320 ereport.cpu.intel.nb.fbd.crc@rank; 321 322 prop fault.memory.intel.fbd.crc@rank (0)-> EREPORT_BUS_ERROR; 323 324 event ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller {within(12s)}; 325 event fault.memory.intel.fbd.reset_timeout@memory-controller, retire=0; 326 327 prop fault.memory.intel.fbd.reset_timeout@memory-controller (1)-> 328 ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller; 329 330 prop fault.memory.intel.fbd.reset_timeout@memory-controller (0)-> 331 EREPORT_BUS_ERROR; 332 333 event ereport.cpu.intel.nb.fbd.ch@dram-channel {within(12s)}; 334 engine serd.cpu.intel.nb.fbd.ch@dram-channel, N=2, T=1month; 335 event fault.memory.intel.fbd.ch@dram-channel, retire=0, 336 engine=serd.cpu.intel.nb.fbd.ch@dram-channel; 337 338 prop fault.memory.intel.fbd.ch@dram-channel (1)-> 339 ereport.cpu.intel.nb.fbd.ch@dram-channel; 340 341 prop fault.memory.intel.fbd.ch@dram-channel (0)-> 342 EREPORT_BUS_ERROR; 343 344 event ereport.cpu.intel.nb.fbd.otf@dram-channel {within(12s)}; 345 engine serd.cpu.intel.nb.fbd_otf@dram-channel, N=2, T=1week; 346 event fault.memory.intel.fbd.otf@dram-channel, retire=0, response=0, 347 engine=serd.cpu.intel.nb.fbd_otf@dram-channel; 348 349 prop fault.memory.intel.fbd.otf@dram-channel (1)-> 350 ereport.cpu.intel.nb.fbd.otf@dram-channel; 351 352 event ereport.cpu.intel.nb.otf@motherboard {within(12s)}; 353 event fault.cpu.intel.nb.otf@motherboard, retire=0, response=0; 354 355 prop fault.cpu.intel.nb.otf@motherboard (1)-> 356 ereport.cpu.intel.nb.otf@motherboard; 357 358 event ereport.cpu.intel.nb.unknown@motherboard {within(12s)}; 359 event ereport.cpu.intel.nb.unknown@memory-controller {within(12s)}; 360 event ereport.cpu.intel.nb.unknown@memory-controller/dram-channel {within(12s)}; 361 event ereport.cpu.intel.nb.spd@memory-controller/dram-channel {within(12s)}; 362 event ereport.cpu.intel.nb.ddr2_spd@ 363 memory-controller/dram-channel {within(12s)}; 364 event upset.discard@memory-controller; 365 366 prop upset.discard@memory-controller (0)-> 367 ereport.cpu.intel.nb.unknown@motherboard, 368 ereport.cpu.intel.nb.unknown@memory-controller, 369 ereport.cpu.intel.nb.unknown@memory-controller/dram-channel, 370 ereport.cpu.intel.nb.spd@memory-controller/dram-channel, 371 ereport.cpu.intel.nb.ddr2_spd@memory-controller/dram-channel; 372 373 event ereport.cpu.intel.nb.mem_ds@memory-controller{within(30s)}; 374 event ereport.cpu.intel.nb.ddr2_mem_ds@memory-controller{within(30s)}; 375 event fault.memory.intel.fbd.mem_ds@memory-controller/dram-channel/dimm/rank, 376 retire=0; 377 378 prop fault.memory.intel.fbd.mem_ds@ 379 memory-controller/dram-channel/dimm/rank[rank_num] 380 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 381 ereport.cpu.intel.nb.mem_ds@memory-controller, 382 ereport.cpu.intel.nb.ddr2_mem_ds@memory-controller; 383 384 event ereport.cpu.intel.nb.fsb@chip{within(12s)}; 385 event fault.cpu.intel.nb.fsb@chip, retire=0; 386 387 prop fault.cpu.intel.nb.fsb@chip (1)-> 388 ereport.cpu.intel.nb.fsb@chip; 389 390 prop fault.cpu.intel.nb.fsb@chip (0)-> EREPORT_BUS_ERROR; 391 392 event ereport.cpu.intel.nb.ie@motherboard{within(12s)}; 393 event fault.cpu.intel.nb.ie@motherboard, retire=0; 394 event upset.cpu.intel.nb.ie_ce@motherboard{within(12s)}; 395 396 prop upset.cpu.intel.nb.ie_ce@motherboard 397 { payloadprop("intel-error-list") == "B6" } (0)-> 398 ereport.cpu.intel.nb.ie@motherboard; 399 400 prop fault.cpu.intel.nb.ie@motherboard 401 { payloadprop("intel-error-list") != "B6" } (1)-> 402 ereport.cpu.intel.nb.ie@motherboard; 403 404 prop fault.cpu.intel.nb.ie@motherboard (0)-> EREPORT_BUS_ERROR; 405 406 event ereport.cpu.intel.nb.dma@motherboard{within(12s)}; 407 event fault.cpu.intel.nb.dma@motherboard, retire=0, response=0; 408 409 prop fault.cpu.intel.nb.dma@motherboard (1)-> 410 ereport.cpu.intel.nb.dma@motherboard; 411 412 prop fault.cpu.intel.nb.dma@motherboard (0)-> EREPORT_BUS_ERROR; 413 414 event ereport.cpu.intel.nb.esi@motherboard{within(12s)}; 415 event ereport.cpu.intel.nb.pex@hostbridge{within(12s)}; 416 event upset.cpu.intel.nb.pex@hostbridge; 417 418 prop upset.cpu.intel.nb.pex@hostbridge (1)-> 419 ereport.cpu.intel.nb.esi@motherboard, 420 ereport.cpu.intel.nb.pex@hostbridge; 421 422 prop upset.cpu.intel.nb.pex@hostbridge (0)-> EREPORT_BUS_ERROR; 423 424 event ereport.cpu.intel.nb.unknown@rank{within(12s)}; 425 event upset.discard@rank; 426 427 prop upset.discard@rank (1)-> 428 ereport.cpu.intel.nb.unknown@rank; 429 430 prop upset.discard@rank (0)-> EREPORT_BUS_ERROR; 431 432 /* 433 * CPU integrated memory controller 434 */ 435 436 #define CONTAINS_RANK (payloadprop_contains("resource", \ 437 asru(chip/memory-controller/dram-channel/dimm/rank)) || \ 438 payloadprop_contains("resource", \ 439 asru(chip/memory-controller/dram-channel/dimm))) 440 441 #define STAT_CPU_MEM_CE_PGFLTS \ 442 stat.ce_pgflt@chip/memory-controller/dram-channel/dimm 443 444 #define SET_RES_OFFSET \ 445 (!payloadprop_defined("resource[0].hc-specific.offset") || \ 446 setpayloadprop("asru-offset", \ 447 payloadprop("resource[0].hc-specific.offset"))) 448 449 engine STAT_CPU_MEM_CE_PGFLTS; 450 451 event ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller 452 {within(12s)}; 453 454 event fault.memory.intel.page_ue@ 455 chip/memory-controller/dram-channel/dimm/rank, 456 message=0, response=0; /* do not message individual pageflts */ 457 458 prop fault.memory.intel.page_ue@ 459 chip/memory-controller/dram-channel/dimm/rank 460 { CONTAINS_RANK && (payloadprop_defined("physaddr") || 461 payloadprop_defined("resource[0].hc-specific.offset")) && 462 SET_ADDR && SET_RES_OFFSET } (0)-> 463 ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller; 464 465 #define CHIPDIMM chip/memory-controller/dram-channel/dimm 466 467 event fault.memory.intel.dimm_ue@CHIPDIMM/rank; 468 469 event error.memory.intel.dimm_ue_ep@CHIPDIMM/rank; 470 event error.memory.intel.dimm_ue_ex@CHIPDIMM/rank; 471 472 prop fault.memory.intel.dimm_ue@CHIPDIMM/rank (1)-> 473 error.memory.intel.dimm_ue_ep@CHIPDIMM/rank, 474 error.memory.intel.dimm_ue_ex@CHIPDIMM/rank; 475 476 prop error.memory.intel.dimm_ue_ep@CHIPDIMM/rank 477 { CONTAINS_RANK } (1)-> 478 ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller; 479 480 prop fault.memory.intel.dimm_ue@CHIPDIMM/rank (0)-> EREPORT_BUS_ERROR; 481 482 event ereport.cpu.intel.quickpath.mem_ce@ 483 chip/memory-controller{within(12s)}; 484 485 engine serd.memory.intel.page_ce@CHIPDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 486 event fault.memory.intel.page_ce@CHIPDIMM/rank, message=0, response=0, 487 count=STAT_CPU_MEM_CE_PGFLTS, 488 engine=serd.memory.intel.page_ce@CHIPDIMM/rank; 489 prop fault.memory.intel.page_ce@CHIPDIMM/rank 490 { CONTAINS_RANK && (payloadprop_defined("physaddr") || 491 payloadprop_defined("resource[0].hc-specific.offset")) && 492 SET_ADDR && SET_RES_OFFSET } (0)-> 493 ereport.cpu.intel.quickpath.mem_ce@chip/memory-controller; 494 495 engine serd.memory.intel.dimm_ce@CHIPDIMM, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 496 event fault.memory.intel.dimm_ce@CHIPDIMM, 497 engine=serd.memory.intel.dimm_ce@CHIPDIMM; 498 prop fault.memory.intel.dimm_ce@CHIPDIMM 499 { !confprop_defined(CHIPDIMM, "dimm-size") && 500 count(STAT_CPU_MEM_CE_PGFLTS) > 512 } (0)-> 501 ereport.cpu.intel.quickpath.mem_ce@chip/memory-controller; 502 503 #define CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \ 504 prop fault.memory.intel.dimm_ce@CHIPDIMM { \ 505 confprop(CHIPDIMM, "dimm-size") == dimm_size && \ 506 count(STAT_CPU_MEM_CE_PGFLTS) > fault_rate && \ 507 setserdn(n) & setserdt(t) } (0)-> \ 508 ereport.cpu.intel.quickpath.mem_ce@ \ 509 chip/memory-controller; 510 511 CPU_MEM_DIMM_CE("16G", 16, 1week, 2000) 512 CPU_MEM_DIMM_CE("8G", 8, 1week, 2000) 513 CPU_MEM_DIMM_CE("4G", 4, 1week, 1500) 514 CPU_MEM_DIMM_CE("2G", 4, 2week, 1000) 515 CPU_MEM_DIMM_CE("1G", 4, 4week, 500) 516 CPU_MEM_DIMM_CE("512M", 4, 8week, 250) 517 518 event ereport.cpu.intel.quickpath.mem_unknown@chip/memory-controller {within(12s)}; 519 event ereport.cpu.intel.quickpath.mem_unknown@chip/memory-controller/dram-channel 520 {within(12s)}; 521 event ereport.cpu.intel.quickpath.mem_unknown@ 522 chip/memory-controller/dram-channel/dimm/rank{within(12s)}; 523 event upset.discard@chip/memory-controller; 524 event upset.discard@chip/memory-controller/dram-channel/dimm/rank; 525 526 prop upset.discard@chip/memory-controller (0)-> 527 ereport.cpu.intel.quickpath.mem_unknown@chip/memory-controller, 528 ereport.cpu.intel.quickpath.mem_unknown@ 529 chip/memory-controller/dram-channel; 530 531 prop upset.discard@ 532 chip/memory-controller/dram-channel/dimm/rank (1)-> 533 ereport.cpu.intel.quickpath.mem_unknown@ 534 chip/memory-controller/dram-channel/dimm/rank; 535 536 event ereport.cpu.intel.quickpath.mem_parity@chip/memory-controller {within(1s)}; 537 event fault.cpu.intel.quickpath.mem_parity@chip/memory-controller; 538 539 prop fault.cpu.intel.quickpath.mem_parity@chip/memory-controller (1)-> 540 ereport.cpu.intel.quickpath.mem_parity@chip/memory-controller; 541 542 event ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller {within(1s)}; 543 event fault.cpu.intel.quickpath.mem_addr_parity@ 544 chip/memory-controller; 545 event fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM; 546 event fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM/rank; 547 548 prop fault.cpu.intel.quickpath.mem_addr_parity@ 549 chip/memory-controller (1)-> 550 ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller; 551 552 prop fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM 553 { payloadprop_contains("resource", asru(CHIPDIMM)) } (1)-> 554 ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller; 555 556 prop fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM/rank 557 { payloadprop_contains("resource", asru(CHIPDIMM/rank)) } (1)-> 558 ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller; 559 560 event ereport.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller {within(1s)}; 561 event fault.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller; 562 563 prop fault.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller (1)-> 564 ereport.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller; 565 566 event ereport.cpu.intel.quickpath.mem_spare@chip/memory-controller {within(1s)}; 567 event fault.cpu.intel.quickpath.mem_spare@ 568 chip/memory-controller/dram-channel/dimm; 569 570 prop fault.cpu.intel.quickpath.mem_spare@ 571 chip/memory-controller/dram-channel/dimm (1)-> 572 ereport.cpu.intel.quickpath.mem_spare@chip/memory-controller; 573 574 event ereport.cpu.intel.quickpath.mem_bad_id@chip/memory-controller {within(1s)}; 575 event fault.cpu.intel.quickpath.mem_bad_id@chip/memory-controller; 576 577 prop fault.cpu.intel.quickpath.mem_bad_id@chip/memory-controller (1)-> 578 ereport.cpu.intel.quickpath.mem_bad_id@chip/memory-controller; 579 580 event ereport.cpu.intel.quickpath.mem_redundant@chip/memory-controller {within(1s)}; 581 engine serd.cpu.intel.quickpath.mem_redundant@CHIPDIMM, N=2, T=72h; 582 event fault.cpu.intel.quickpath.mem_redundant@CHIPDIMM, 583 engine=serd.cpu.intel.quickpath.mem_redundant@CHIPDIMM; 584 585 event error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank; 586 587 prop fault.cpu.intel.quickpath.mem_redundant@CHIPDIMM (1)-> 588 error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank<>; 589 prop error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank 590 { CONTAINS_RANK } (1)-> 591 ereport.cpu.intel.quickpath.mem_redundant@ 592 chip/memory-controller; 593 594 #define STATUS_UC (payloadprop("error_uncorrected") == 1) 595 event ereport.cpu.intel.quickpath.interconnect@chip 596 {within(1s)}; 597 event upset.cpu.intel.quickpath.interconnect@chip; 598 /* Diagnose corrected events to upsets */ 599 prop upset.cpu.intel.quickpath.interconnect@chip 600 { !STATUS_UC } (1)-> 601 ereport.cpu.intel.quickpath.interconnect@chip; 602 603 engine serd.cpu.intel.quickpath.interconnect@chip, 604 N=3, T=72h; 605 event fault.cpu.intel.quickpath.interconnect@chip, 606 engine=serd.cpu.intel.quickpath.interconnect@chip; 607 608 /* Diagnose uncorrected events to faults */ 609 prop fault.cpu.intel.quickpath.interconnect@chip 610 { STATUS_UC } (0)-> 611 ereport.cpu.intel.quickpath.interconnect@chip; 612 613 614 /* 615 * Nehalem EX specific rules 616 */ 617 /* MBox errors */ 618 #define EX_MEM_EVENT(leafclass, t) \ 619 event ereport.cpu.intel.quickpath.leafclass@ \ 620 chip/memory-controller { within(t) } 621 622 EX_MEM_EVENT(mem_lnktrns, 1s); 623 EX_MEM_EVENT(mem_lnkpers, 1s); 624 EX_MEM_EVENT(mem_sbfbdlinkerr, 1s); 625 EX_MEM_EVENT(mem_nbfbdlnkerr, 1s); 626 EX_MEM_EVENT(mem_lnkcrcvld, 1s); 627 628 engine serd.cpu.intel.quickpath.mem_link_ce@chip/memory-controller, 629 N=500, T=1week; 630 event fault.cpu.intel.quickpath.mem_link_ce@chip/memory-controller, 631 engine=serd.cpu.intel.quickpath.mem_link_ce@chip/memory-controller, 632 retire=0, response=0; 633 634 prop fault.cpu.intel.quickpath.mem_link_ce@chip/memory-controller -> 635 ereport.cpu.intel.quickpath.mem_lnktrns@chip/memory-controller, 636 ereport.cpu.intel.quickpath.mem_lnkpers@chip/memory-controller, 637 ereport.cpu.intel.quickpath.mem_sbfbdlinkerr@chip/memory-controller, 638 ereport.cpu.intel.quickpath.mem_nbfbdlnkerr@chip/memory-controller, 639 ereport.cpu.intel.quickpath.mem_lnkcrcvld@chip/memory-controller; 640 641 EX_MEM_EVENT(mem_lnkuncorr_uc, 1s); 642 EX_MEM_EVENT(mem_lnkpers_uc, 1s); 643 EX_MEM_EVENT(mem_sbfbdlinkerr_uc, 1s); 644 EX_MEM_EVENT(mem_nbfbdlnkerr_uc, 1s); 645 EX_MEM_EVENT(mem_lnkcrcvld_uc, 1s); 646 647 event fault.cpu.intel.quickpath.mem_link_ue@chip/memory-controller, 648 retire=0; 649 650 prop fault.cpu.intel.quickpath.mem_link_ue@chip/memory-controller -> 651 ereport.cpu.intel.quickpath.mem_lnkuncorr_uc@chip/memory-controller, 652 ereport.cpu.intel.quickpath.mem_lnkpers_uc@chip/memory-controller, 653 ereport.cpu.intel.quickpath.mem_sbfbdlinkerr_uc@chip/memory-controller, 654 ereport.cpu.intel.quickpath.mem_nbfbdlnkerr_uc@chip/memory-controller, 655 ereport.cpu.intel.quickpath.mem_lnkcrcvld_uc@chip/memory-controller; 656 657 EX_MEM_EVENT(mem_ptrl_fsm_err, 1s); 658 EX_MEM_EVENT(mem_errflw_fsm_fail, 1s); 659 EX_MEM_EVENT(mem_vberr, 1s); 660 661 engine serd.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller, 662 N=500, T=1week; 663 event fault.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller, 664 engine=serd.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller, 665 retire=0, response=0; 666 667 prop fault.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller -> 668 ereport.cpu.intel.quickpath.mem_ptrl_fsm_err@chip/memory-controller, 669 ereport.cpu.intel.quickpath.mem_errflw_fsm_fail@chip/memory-controller, 670 ereport.cpu.intel.quickpath.mem_vberr@chip/memory-controller; 671 672 EX_MEM_EVENT(mem_ptrl_fsm_err_uc, 1s); 673 EX_MEM_EVENT(mem_errflw_fsm_fail_uc, 1s); 674 EX_MEM_EVENT(mem_mcpar_fsmerr_uc, 1s); 675 EX_MEM_EVENT(mem_vberr_uc, 1s); 676 EX_MEM_EVENT(mem_fberr_uc, 1s); 677 678 event fault.cpu.intel.quickpath.mem_controller_ue@chip/memory-controller, 679 retire=0; 680 681 prop fault.cpu.intel.quickpath.mem_controller_ue@chip/memory-controller -> 682 ereport.cpu.intel.quickpath.mem_ptrl_fsm_err_uc@chip/memory-controller, 683 ereport.cpu.intel.quickpath.mem_errflw_fsm_fail_uc@chip/memory-controller, 684 ereport.cpu.intel.quickpath.mem_mcpar_fsmerr_uc@chip/memory-controller, 685 ereport.cpu.intel.quickpath.mem_vberr_uc@chip/memory-controller, 686 ereport.cpu.intel.quickpath.mem_fberr_uc@chip/memory-controller; 687 688 EX_MEM_EVENT(mem_scrubbing_uc, 1s); 689 event fault.cpu.intel.quickpath.mem_scrubbing@ 690 chip/memory-controller/dram-channel/dimm/rank, 691 response=0; 692 693 prop fault.cpu.intel.quickpath.mem_scrubbing@ 694 chip/memory-controller/dram-channel/dimm/rank[rank_num] 695 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 696 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 697 SET_ADDR && SET_OFFSET } (1)-> 698 ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip/memory-controller; 699 700 EX_MEM_EVENT(mem_ecc_uc, 12s); 701 EX_MEM_EVENT(mem_even_parity_uc, 1s); 702 703 EX_MEM_EVENT(mem_ecc, 12s); 704 EX_MEM_EVENT(mem_even_parity, 1s); 705 706 event error.memory.intel.ex_dimm_ce@ 707 chip/memory-controller/dram-channel/dimm/rank; 708 709 prop fault.memory.intel.page_ue@ 710 chip/memory-controller/dram-channel/dimm/rank[rank_num] 711 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 712 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 713 SET_ADDR && SET_OFFSET } (0)-> 714 ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller, 715 ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller; 716 717 prop fault.memory.intel.page_ce@ 718 chip/memory-controller/dram-channel/dimm/rank[rank_num] 719 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 720 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 721 SET_ADDR && SET_OFFSET } (0)-> 722 ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, 723 ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller; 724 725 prop error.memory.intel.dimm_ue_ex@ 726 chip/memory-controller/dram-channel/dimm/rank[rank_num] 727 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 728 ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller, 729 ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller; 730 731 prop fault.memory.intel.dimm_ce@ 732 chip/memory-controller/dram-channel/dimm 733 { !confprop_defined(chip/memory-controller/dram-channel/dimm, 734 "dimm-size") && setserdn(10) & setserdt(1week) } (0)-> 735 error.memory.intel.ex_dimm_ce@ 736 chip/memory-controller/dram-channel/dimm/rank; 737 prop error.memory.intel.ex_dimm_ce@ 738 chip/memory-controller/dram-channel/dimm/rank[rank_num] 739 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 740 !confprop_defined(chip/memory-controller/dram-channel/dimm, 741 "dimm-size") && 742 count(STAT_CPU_MEM_CE_PGFLTS) > 512 } (1)-> 743 ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, 744 ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller; 745 746 #define EX_CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \ 747 prop fault.memory.intel.dimm_ce@ \ 748 chip/memory-controller/dram-channel/dimm { \ 749 confprop(chip/memory-controller/dram-channel/dimm, \ 750 "dimm-size") == dimm_size && \ 751 setserdn(n) & setserdt(t) } (0)-> \ 752 error.memory.intel.ex_dimm_ce@ \ 753 chip/memory-controller/dram-channel/dimm/rank; \ 754 prop error.memory.intel.ex_dimm_ce@ \ 755 chip/memory-controller/dram-channel/dimm/rank[rank_num] { \ 756 payloadprop_defined("rank") && rank_num == payloadprop("rank") && \ 757 confprop(chip/memory-controller/dram-channel/dimm, \ 758 "dimm-size") == dimm_size && \ 759 count(STAT_CPU_MEM_CE_PGFLTS) > fault_rate } (1)-> \ 760 ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, \ 761 ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller; 762 763 EX_CPU_MEM_DIMM_CE("16G", 16, 1week, 2000) 764 EX_CPU_MEM_DIMM_CE("8G", 8, 1week, 2000) 765 EX_CPU_MEM_DIMM_CE("4G", 4, 1week, 1500) 766 EX_CPU_MEM_DIMM_CE("2G", 4, 2week, 1000) 767 EX_CPU_MEM_DIMM_CE("1G", 4, 4week, 500) 768 769 event upset.memory.intel.discard@chip/memory-controller{within(1s)}; 770 771 prop upset.memory.intel.discard@chip/memory-controller (0)-> 772 ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip/memory-controller, 773 ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller, 774 ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller, 775 ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, 776 ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller; 777 778 EX_MEM_EVENT(mem_failover_mir, 1s); 779 event fault.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller, 780 retire=0; 781 782 prop fault.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller -> 783 ereport.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller; 784 785 /* 786 * RBox errors 787 */ 788 #define EX_EVENT(leafclass, t) \ 789 event ereport.cpu.intel.quickpath.leafclass@chip { within(t) } 790 791 engine serd.cpu.intel.quickpath.bus_interconnect@chip, 792 N=3, T=72h; 793 event fault.cpu.intel.quickpath.bus_interconnect@chip, 794 engine=serd.cpu.intel.quickpath.bus_interconnect@chip, 795 retire=0; 796 797 EX_EVENT(bus_retry_abort, 1s); 798 EX_EVENT(bus_link_init_ce, 1s); 799 event upset.cpu.intel.quickpath.discard@chip; 800 801 prop upset.cpu.intel.quickpath.discard@chip (0)-> 802 ereport.cpu.intel.quickpath.bus_retry_abort@chip, 803 ereport.cpu.intel.quickpath.bus_link_init_ce@chip; 804 805 EX_EVENT(bus_unknown, 1s); 806 EX_EVENT(bus_single_ecc, 1s); 807 EX_EVENT(bus_crc_flit, 1s); 808 809 prop fault.cpu.intel.quickpath.bus_interconnect@chip (0)-> 810 ereport.cpu.intel.quickpath.bus_unknown@chip, 811 ereport.cpu.intel.quickpath.bus_single_ecc@chip, 812 ereport.cpu.intel.quickpath.bus_crc_flit@chip; 813 814 EX_EVENT(bus_unknown_external, 1s); 815 EX_EVENT(bus_crc_flit_external, 1s); 816 prop upset.cpu.intel.quickpath.discard@chip (0)-> 817 ereport.cpu.intel.quickpath.bus_unknown_external@chip, 818 ereport.cpu.intel.quickpath.bus_crc_flit_external@chip; 819 820 EX_EVENT(bus_unknown_uc, 1s); 821 EX_EVENT(bus_opr_poison_err, 1s); 822 EX_EVENT(bus_eot_parity, 1s); 823 EX_EVENT(bus_rta_parity, 1s); 824 EX_EVENT(bus_bad_sbu_route, 1s); 825 EX_EVENT(bus_bad_msg, 1s); 826 EX_EVENT(bus_bad_vn_credit, 1s); 827 EX_EVENT(bus_hdr_double_ecc, 1s); 828 EX_EVENT(bus_link_retry_err, 1s); 829 830 prop fault.cpu.intel.quickpath.bus_interconnect@chip 831 { setserdincrement(4) } (0)-> 832 ereport.cpu.intel.quickpath.bus_unknown_uc@chip, 833 ereport.cpu.intel.quickpath.bus_opr_poison_err@chip, 834 ereport.cpu.intel.quickpath.bus_eot_parity@chip, 835 ereport.cpu.intel.quickpath.bus_rta_parity@chip, 836 ereport.cpu.intel.quickpath.bus_bad_sbu_route@chip, 837 ereport.cpu.intel.quickpath.bus_bad_msg@chip, 838 ereport.cpu.intel.quickpath.bus_bad_vn_credit@chip, 839 ereport.cpu.intel.quickpath.bus_hdr_double_ecc@chip, 840 ereport.cpu.intel.quickpath.bus_link_retry_err@chip; 841 842 EX_EVENT(bus_unknown_uc_external, 1s); 843 EX_EVENT(bus_opr_poison_err_external, 1s); 844 EX_EVENT(bus_eot_parity_external, 1s); 845 EX_EVENT(bus_rta_parity_external, 1s); 846 EX_EVENT(bus_bad_sbu_route_external, 1s); 847 EX_EVENT(bus_bad_msg_external, 1s); 848 EX_EVENT(bus_bad_vn_credit_external, 1s); 849 EX_EVENT(bus_hdr_double_ecc_external, 1s); 850 EX_EVENT(bus_link_retry_err_external, 1s); 851 852 prop upset.cpu.intel.quickpath.discard@chip (0)-> 853 ereport.cpu.intel.quickpath.bus_unknown_uc_external@chip, 854 ereport.cpu.intel.quickpath.bus_opr_poison_err_external@chip, 855 ereport.cpu.intel.quickpath.bus_eot_parity_external@chip, 856 ereport.cpu.intel.quickpath.bus_rta_parity_external@chip, 857 ereport.cpu.intel.quickpath.bus_bad_sbu_route_external@chip, 858 ereport.cpu.intel.quickpath.bus_bad_msg_external@chip, 859 ereport.cpu.intel.quickpath.bus_bad_vn_credit_external@chip, 860 ereport.cpu.intel.quickpath.bus_hdr_double_ecc_external@chip, 861 ereport.cpu.intel.quickpath.bus_link_retry_err_external@chip; 862 863 /* 864 * CBox errors 865 */ 866 EX_EVENT(llc_ewb_uc, 1s); 867 event fault.cpu.intel.quickpath.llc_ewb@chip, 868 retire=0, response=0; 869 870 prop fault.cpu.intel.quickpath.llc_ewb@chip 871 { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 872 SET_ADDR && SET_OFFSET } (1)-> 873 ereport.cpu.intel.quickpath.llc_ewb_uc@chip; 874 875 prop upset.cpu.intel.quickpath.discard@chip (0)-> 876 ereport.cpu.intel.quickpath.llc_ewb_uc@chip; 877 878 /* 879 * SBox errors 880 */ 881 EX_EVENT(system_cache_uc, 1s); 882 event fault.cpu.intel.quickpath.system_cache@chip, 883 retire=0, response=0; 884 prop fault.cpu.intel.quickpath.system_cache@chip -> 885 ereport.cpu.intel.quickpath.system_cache_uc@chip; 886 887 /* 888 * BBox errors 889 */ 890 EX_EVENT(home_agent_uc, 1s); 891 event fault.cpu.intel.quickpath.home_agent@chip, 892 retire=0, response=0; 893 prop fault.cpu.intel.quickpath.home_agent@chip -> 894 ereport.cpu.intel.quickpath.home_agent_uc@chip; 895 896 /* 897 * UBox errors 898 */ 899 EX_EVENT(sys_cfg_cfa_ecc, 1s); 900 EX_EVENT(sys_cfg_uc, 1s); 901 902 engine serd.cpu.intel.quickpath.sys_cfg@chip, 903 N=2, T=72h; 904 event fault.cpu.intel.quickpath.sys_cfg@chip, 905 engine=serd.cpu.intel.quickpath.sys_cfg@chip, 906 retire=0, response=0; 907 908 prop fault.cpu.intel.quickpath.sys_cfg@chip (0)-> 909 ereport.cpu.intel.quickpath.sys_cfg_cfa_ecc@chip; 910 911 prop fault.cpu.intel.quickpath.sys_cfg@chip 912 { setserdincrement(3) } (0)-> 913 ereport.cpu.intel.quickpath.sys_cfg_uc@chip; 914 915 /* 916 * Handling poison errors 917 */ 918 engine stat.has_poison@motherboard; 919 event fault.cpu.intel.has_poison@motherboard, 920 count=stat.has_poison@motherboard[0], 921 message=0, retire=0, response=0; 922 engine stat.discard_fatal@motherboard; 923 event fault.cpu.intel.discard_fatal@motherboard, 924 count=stat.discard_fatal@motherboard[0], 925 message=0, retire=0, response=0; 926 927 prop fault.cpu.intel.has_poison@motherboard 928 { payloadprop_defined("poison") && 1 == payloadprop("poison") } (1)-> 929 ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip<>/memory-controller<>, 930 ereport.cpu.intel.quickpath.llc_ewb_uc@chip<>, 931 ereport.cpu.intel.quickpath.system_cache_uc@chip<>, 932 ereport.cpu.intel.quickpath.bus_opr_poison_err@chip<>, 933 ereport.cpu.intel.quickpath.bus_opr_poison_err_external@chip<>; 934 935 prop fault.cpu.intel.discard_fatal@motherboard 936 { count(stat.has_poison@motherboard[0]) > count(stat.discard_fatal@motherboard[0]) && 937 payloadprop_defined("bank_number") && 5 == payloadprop("bank_number") && 938 payloadprop_defined("processor_context_corrupt") && 939 1 == payloadprop("processor_context_corrupt") } (0)-> 940 ereport.cpu.intel.internal_unclassified@chip<>/core<>/strand<> {within(10s)}; 941 942 prop fault.cpu.intel.internal@chip/core/strand 943 { (count(stat.has_poison@motherboard[0]) <= count(stat.discard_fatal@motherboard[0]) || 944 !payloadprop_defined("bank_number") || 5 != payloadprop("bank_number") || 945 !payloadprop_defined("processor_context_corrupt") || 946 0 == payloadprop("processor_context_corrupt")) && 947 (payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1) } (0)-> 948 ereport.cpu.intel.internal_unclassified@chip/core/strand; 949
Indexes created Wed Feb 10 04:24:43 UTC 2010
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