| /onnv/onnv-gate/usr/src/lib/fm/topo/modules/sun4u/chip/ |
| Makefile | 31 include ../../sun4/chip/Makefile.chip
|
| chip_sun4u.c | 49 * system. For each chip found, the necessary nodes (one or more cores, and
59 #define CHIP_NODE_NAME "chip"
61 typedef struct chip { struct
73 { "chip", FM_FMRI_SCHEME_HC, CHIP_VERSION, &chip_ops };
78 chip_t *chip; local
82 topo_mod_dprintf(mod, "initializing chip enumerator\n");
84 if ((chip = topo_mod_zalloc(mod, sizeof (chip_t))) == NULL)
87 if ((chip->chip_kc = kstat_open()) == NULL) {
90 topo_mod_free(mod, chip, sizeof (chip_t));
94 chip->chip_ncpustats = sysconf(_SC_CPUID_MAX)
119 chip_t *chip; local
271 chip_t *chip = (chip_t *)arg; local
[all...] |
| /onnv/onnv-gate/usr/src/lib/fm/topo/modules/sun4u/ |
| Makefile | 28 SUBDIRS = chip hostbridge pcibus
|
| /onnv/onnv-gate/usr/src/lib/fm/topo/modules/i86pc/ |
| Makefile | 27 SUBDIRS = chip hostbridge pcibus x86pi
|
| /onnv/onnv-gate/usr/src/cmd/fm/eversholt/files/sparc/sun4v/ |
| gcpu.esc | 53 * some set of @chip, @core, and @strand resources since this is
56 * cache per chip, another may have an L2 per core.
87 ERPT_EVENT(chip, itlb-uc);
90 ERPT_EVENT(chip, dtlb-uc);
93 ERPT_EVENT(chip, icache-uc);
95 ERPT_EVENT(chip, dcache-uc);
97 ERPT_EVENT(chip, ireg-uc);
100 ERPT_EVENT(chip, freg-uc);
103 ERPT_EVENT(chip, mreg-uc);
106 ERPT_EVENT(chip, l2data-uc)
[all...] |
| /onnv/onnv-gate/usr/src/cmd/fm/eversholt/files/i386/i86pc/ |
| amd64.esc | 57 * "prop foo@chip/memory-controller/dimm/rank -> blah@chip/core/strand"
61 * all dimms, ranks and cpus on the same chip (since chip appears in the
66 asru(chip/memory-controller/dimm/rank)) \
68 asru(chip/memory-controller/dimm)))
122 event ereport.cpu.amd.ic.inf_sys_ecc1@chip/core/strand{within(5s)};
123 event ereport.cpu.amd.dc.inf_sys_ecc1@chip/core/strand{within(5s)};
124 event ereport.cpu.amd.bu.s_ecc1@chip/core/strand{within(5s)};
125 event ereport.cpu.amd.nb.mem_ce@chip/core/strand{within(5s)}
[all...] |
| intel.esc | 38 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) }
57 engine serd.cpu.intel.simple@chip/core/strand, N=3, T=72h;
58 event fault.cpu.intel.internal@chip/core/strand,
59 engine=serd.cpu.intel.simple@chip/core/strand;
61 prop fault.cpu.intel.internal@chip/core/strand
63 ereport.cpu.intel.microcode_rom_parity@chip/core/strand,
64 ereport.cpu.intel.internal_timer@chip/core/strand,
65 ereport.cpu.intel.internal_parity@chip/core/strand,
66 ereport.cpu.intel.unclassified@chip/core/strand,
67 ereport.cpu.intel.frc@chip/core/strand
[all...] |
| gcpu_amd.esc | 28 * Eversholt rules for generic AMD with on-chip memory-controller(s), as seen
32 * are observed via MCA (typically through an on-chip memory-controller)
44 * those chip versions that include an Online Spare Control register; this
45 * register provides counts of ECC errors seen per channel and chip-select
47 * hc:///motherboard/chip/memory-controller/dram-channel/chip-select
54 * The number of pages that must be faulted on a chip-select for repeated
62 * chip-select (must be at least CS_PAGEFLT_THRESH). If a chip-select
70 * correctable ereports are experienced on a single chip-select withi
[all...] |
| gcpu.esc | 44 event ereport.cpu.generic-x86.leafclass@chip/core/strand { within(1s) }
63 engine serd.cpu.generic-x86.simple@chip/core/strand, N=SMPL_N, T=72h;
64 event fault.cpu.generic-x86.internal@chip/core/strand,
65 engine=serd.cpu.generic-x86.simple@chip/core/strand;
67 prop fault.cpu.generic-x86.internal@chip/core/strand
70 ereport.cpu.generic-x86.microcode_rom_parity@chip/core/strand,
71 ereport.cpu.generic-x86.internal_timer@chip/core/strand,
72 ereport.cpu.generic-x86.internal_parity@chip/core/strand,
73 ereport.cpu.generic-x86.unclassified@chip/core/strand,
74 ereport.cpu.generic-x86.internal_unclassified@chip/core/strand
[all...] |
| /onnv/onnv-gate/usr/src/lib/fm/topo/modules/i86pc/chip/ |
| Makefile | 26 MODULE = chip
29 MODULESRCS = chip.c chip_label.c chip_subr.c chip_amd.c chip_intel.c\
|
| chip.c | 52 #include "chip.h"
59 * system. For each chip found, the necessary nodes (one or more cores, and
72 { PGNAME(CHIP), TOPO_STABILITY_PRIVATE, TOPO_STABILITY_PRIVATE, 1 };
113 topo_mod_dprintf(mod, "initializing chip enumerator\n");
346 * Inherit FRU from the chip node, for native, we use hc
459 tnode_t *chip; local
495 ": enumerating x86pi & chip topology, but"
496 " no Chip properties from SMBIOS"
509 if ((chip = topo_node_lookup(pnode, CHIP_NODE_NAME, chipid)) == NULL) {
510 if ((chip = create_node(mod, pnode, auth, CHIP_NODE_NAME
[all...] |
| chip_label.c | 169 * dimms_per_chip: the number of DIMM slots per chip
177 tnode_t *chip; local
212 chip = topo_node_parent(topo_node_parent(node));
216 (void) snprintf(buf, BUFSZ, fmtstr, topo_node_instance(chip),
220 (void) snprintf(buf, BUFSZ, fmtstr, topo_node_instance(chip),
221 (((topo_node_instance(chip) + 1) * dimms_per_chip)
243 * are 4 DIMM slots per chip. It takes the following two arguments:
266 tnode_t *chip; local
292 chip = topo_node_parent(topo_node_parent(node));
297 + (topo_node_instance(chip) * 4) + offset))
671 tnode_t *chip, *chan; local
718 tnode_t *chip; local
792 tnode_t *chip; local
[all...] |
| /onnv/onnv-gate/usr/src/lib/fm/topo/modules/sun4v/platform-cpu/ |
| cpu_mdesc.c | 47 cpu_find_proc(md_info_t *chip, uint32_t procid) {
52 for (i = 0, procp = chip->procs; i < chip->nprocs; i++, procp++) {
62 cpu_find_cpumap(md_info_t *chip, uint32_t cpuid) {
66 for (i = 0, mcmp = chip->cpus; i < chip->ncpus; i++, mcmp++) {
75 cpu_get_serialid_mdesc(md_info_t *chip, uint32_t cpuid, uint64_t *serialidp)
78 if ((mcmp = cpu_find_cpumap(chip, cpuid)) != NULL) {
86 cpu_n1_mdesc_init(topo_mod_t *mod, md_t *mdp, md_info_t *chip)
96 chip->ncpus = md_scan_dag(mdp
[all...] |
| cpu_mdesc.h | 62 int cpumap_chipidx; /* chip idx */
86 extern int cpu_mdesc_init(topo_mod_t *mod, md_info_t *chip);
87 extern void cpu_mdesc_fini(topo_mod_t *mod, md_info_t *chip);
89 extern int cpu_get_serialid_mdesc(md_info_t *chip, uint32_t cpuid,
91 extern md_cpumap_t *cpu_find_cpumap(md_info_t *chip, uint32_t cpuid);
92 extern md_proc_t *cpu_find_proc(md_info_t *chip, uint32_t procid);
|
| cpu.c | 94 md_info_t *chip; local
101 if ((chip = topo_mod_zalloc(mod, sizeof (md_info_t))) == NULL)
104 if (cpu_mdesc_init(mod, chip) != 0) {
106 topo_mod_free(mod, chip, sizeof (md_info_t));
110 topo_mod_setspecific(mod, (void *)chip);
115 cpu_mdesc_fini(mod, chip);
116 topo_mod_free(mod, chip, sizeof (md_info_t));
128 md_info_t *chip; local
130 chip = (md_info_t *)topo_mod_getspecific(mod);
132 cpu_mdesc_fini(mod, chip);
150 md_info_t *chip = (md_info_t *)topo_mod_getspecific(mod); local
196 md_info_t *chip = (md_info_t *)topo_mod_getspecific(mod); local
244 md_info_t *chip = (md_info_t *)topo_mod_getspecific(mod); local
316 md_info_t *chip = (md_info_t *)topo_mod_getspecific(mod); local
[all...] |
| /onnv/onnv-gate/usr/src/lib/fm/topo/modules/sun4v/ |
| Makefile | 28 SUBDIRS = chip \
|
| /onnv/onnv-gate/usr/src/lib/fm/topo/modules/sun4v/chip/ |
| Makefile | 35 include ../../sun4/chip/Makefile.chip
|
| chip_sun4v.c | 46 * system. For each chip found, the necessary nodes (one or more cores, and
52 #define CHIP_NODE_NAME "chip"
64 { "chip", FM_FMRI_SCHEME_HC, CHIP_VERSION, &chip_ops };
77 md_info_t *chip; local
81 topo_mod_dprintf(mod, "initializing chip enumerator\n");
83 if ((chip = topo_mod_zalloc(mod, sizeof (md_info_t))) == NULL)
86 if (cpu_mdesc_init(mod, chip) != 0) {
88 topo_mod_free(mod, chip, sizeof (md_info_t));
92 topo_mod_setspecific(mod, (void *)chip);
97 cpu_mdesc_fini(mod, chip);
110 md_info_t *chip; local
416 md_info_t *chip = (md_info_t *)arg; local
[all...] |
| /onnv/onnv-gate/usr/src/uts/common/io/vr/ |
| vr.c | 420 if (vrp->chip.state == CHIPSTATE_RUNNING)
530 if (vrp->chip.state == CHIPSTATE_SUSPENDED_RUNNING)
546 if (vrp->chip.state == CHIPSTATE_RUNNING) {
548 vrp->chip.state = CHIPSTATE_SUSPENDED_RUNNING;
628 vrp->chip.vendor = VR_GET16(vrp->acc_cfg, PCI_CONF_VENID);
629 vrp->chip.device = VR_GET16(vrp->acc_cfg, PCI_CONF_DEVID);
630 vrp->chip.revision = VR_GET16(vrp->acc_cfg, PCI_CONF_REVID);
637 if (vrp->chip.revision >= vr_chip_info[n].revmin &&
638 vrp->chip.revision <= vr_chip_info[n].revmax) {
640 (void*)&vrp->chip.info
[all...] |
| /onnv/onnv-gate/usr/src/lib/fm/topo/modules/sun4/chip/ |
| Makefile.chip | 27 MODULE = chip
|
| /onnv/onnv-gate/usr/src/lib/fm/topo/maps/i86pc/ |
| Makefile | 29 TOPOFILE = i86pc-hc-topology.xml chip-hc-topology.xml psu-hc-topology.xml \
|
| /onnv/onnv-gate/usr/src/uts/intel/io/intel_nhm/ |
| intel_nhmdrv.c | 117 int chip; local
124 chip = getminor(dev) % MAX_CPU_NODES;
125 if (inhm_mc_nvl[chip] == NULL ||
131 if (inhm_mc_nvl[chip])
133 inhm_create_nvl(chip);
139 mcs.mcs_size = (uint32_t)inhm_mc_snapshotsz[chip];
147 if (ddi_copyout(inhm_mc_snapshot[chip], (void *)arg,
148 inhm_mc_snapshotsz[chip], mode) < 0)
|
| /onnv/onnv-gate/usr/src/cmd/fm/dicts/ |
| SUN4V.dict | 85 fault.cpu.ultraSPARC-T2plus.chip=57
86 fault.asic.ultraSPARC-T2plus.interconnect.lfu-c fault.cpu.ultraSPARC-T2plus.chip=58
87 fault.asic.ultraSPARC-T2plus.interconnect.lfu-f fault.cpu.ultraSPARC-T2plus.chip=59
88 fault.asic.ultraSPARC-T2plus.interconnect.lfu-u fault.cpu.ultraSPARC-T2plus.chip=60
90 fault.asic.ultraSPARC-T2plus.interconnect.gpd-u fault.cpu.ultraSPARC-T2plus.chip=62
91 fault.asic.ultraSPARC-T2plus.interconnect.gpd-c fault.cpu.ultraSPARC-T2plus.chip=63
106 fault.cpu.generic-sparc.chip=78
107 fault.cpu.generic-sparc.chip-nr=79
108 fault.cpu.generic-sparc.chip-uc=80
109 fault.cpu.generic-sparc.chip-uc-nr=8
[all...] |
| /onnv/onnv-gate/usr/src/lib/libdtrace/common/ |
| sched.d | 34 chipid_t cpu_chip; /* chip identifier */
75 inline chipid_t chip = curcpu->cpu_chip;
76 #pragma D attributes Stable/Stable/Common chip
77 #pragma D binding "1.0" chip
|
| /onnv/onnv-gate/usr/src/uts/sun4u/sys/ |
| opl_cfg.h | 52 * | 1 | LSB ID | CHIP | CORE | CPU |
60 #define OPL_PORTID(board, chip) ((1 << 10) | (board << 5) | (chip << 3))
62 #define OPL_CPUID(board, chip, core, cpu) \
64 ((board << 5) | (chip << 3) | (core << 1) | (cpu))
67 * Dummy address space for a chip.
69 #define OPL_PROC_AS(board, chip) \
72 (1ULL << 33) | ((uint64_t)chip << 4))
|
