| /onnv/onnv-gate/usr/src/uts/i86pc/boot/ |
| boot_serial.h | 38 #define ISR 2 /* ... intr status reg */
45 #define FIFOR ISR /* ... fifo write reg */
|
| boot_console.c | 152 outb(port + ISR, 0x20);
153 if (inb(port + ISR) & 0x20) {
158 outb(port + ISR, 0x40); /* set to bank 2 */
161 outb(port + ISR, 0x00); /* set to bank 0 */
174 if ((inb(port + ISR) & 0xc0) != 0xc0) {
|
| /onnv/onnv-gate/usr/src/uts/common/sys/ |
| asy.h | 64 #define ISR 2 /* interrupt status register */
72 #define FIFOR ISR /* FIFO register for 16550 */
73 #define EFR ISR /* Enhanced feature register for 16650 */
|
| /onnv/onnv-gate/usr/src/uts/sun4/sys/ |
| sudev.h | 52 #define ISR 2 /* interrupt status register */
60 #define FIFOR ISR /* FIFO register for 16550 */
|
| /onnv/onnv-gate/usr/src/uts/common/io/sfe/ |
| sfereg.h | 125 #define ISR 0x10 /* Interrupt status register */
|
| sfe.c | 538 lp->isr_pended |= INL(dp, ISR) & lp->our_intr_bits;
551 done |= INL(dp, ISR) & (ISR_TXRCMP | ISR_RXRCMP);
592 lp->isr_pended |= INL(dp, ISR) & lp->our_intr_bits;
946 val = INL(dp, ISR);
986 val = INL(dp, ISR);
1546 uint32_t isr; local
[all...] |
| /onnv/onnv-gate/usr/src/uts/sun4/io/ |
| su_driver.c | 365 * If bit 4 or 5 appears on inb() ISR, board is not there.
367 if (ddi_get8(handle, addr+ISR) & 0x30) {
577 OUTB(ISR, 0x20);
578 if (INB(ISR) & 0x20) { /* 82510 chip is present */
586 OUTB(ISR, 0x40); /* set to bank 2 */
589 OUTB(ISR, 0x00); /* set to bank 0 */
600 if ((INB(ISR) & 0xc0) == 0xc0)
[all...] |
| /onnv/onnv-gate/usr/src/grub/grub-0.97/netboot/ |
| ns83820.c | 272 #define ISR 0x10
658 u32 isr = readl(ns->base + ISR); local
659 if(ISR_PHY & isr)
661 if(( ISR_RXIDLE | ISR_RXDESC | ISR_RXERR) & isr)
727 u32 isr = readl(ns->base + ISR); local
728 if (ISR_TXIDLE & isr)
|
| /onnv/onnv-gate/usr/src/uts/common/io/ |
| asy.c | [all...] |
