| /onnv/onnv-gate/usr/src/cmd/mdb/sparc/mdb/ |
| kvm_v9dep.c | 250 uint32_t pil; local
360 * which on sparcv9 is the %pil register's value.
362 if (mdb_tgt_readsym(t, MDB_TGT_AS_VIRT, &pil, sizeof (pil),
363 MDB_TGT_OBJ_EXEC, "panic_ipl") == sizeof (pil))
364 kregs[KREG_PIL] = pil;
|
| /onnv/onnv-gate/usr/src/uts/sun4v/sys/ |
| cnex.h | 49 uint32_t pil; /* PIL for device class */ member in struct:cnex_intr_map
|
| /onnv/onnv-gate/usr/src/uts/sun4u/io/pci/ |
| pci_ib.c | 539 ib_new_ino_pil(ib_t *ib_p, ib_ino_t ino_num, uint_t pil, ih_t *ih_p)
556 ino_p->ino_lopil = pil;
560 ipil_p->ipil_pil = pil;
571 if (ino_p->ino_lopil > pil)
572 ino_p->ino_lopil = pil;
582 ushort_t pil = ipil_p->ipil_pil; local
599 if ((--ino_p->ino_ipil_size) && (ino_p->ino_lopil == pil)) {
600 for (next = ino_p->ino_ipil_p, pil = next->ipil_pil;
603 if (pil > next->ipil_pil)
604 pil = next->ipil_pil
[all...] |
| /onnv/onnv-gate/usr/src/cmd/mdb/sparc/modules/intr/ |
| intr.c | 44 uint32_t pil; member in struct:intr_info
245 info.pil = ipil.ipil_pil;
347 info.pil = ipil.ipil_pil;
392 " Pil\t"
415 mdb_printf(" %4d\t", info.pil);
439 mdb_printf("Pil:\t\t%d\n", info.pil);
|
| /onnv/onnv-gate/usr/src/uts/sun4/io/ |
| ebus.c | 743 uint32_t pil; member in struct:ebus_string_to_pil
797 * This is a hack to set the PIL for the devices under ebus.
800 * Lastly we default a PIL level of 1.
808 DBG2(D_INTR, ebus_p, "child name %s; match PIL %d\n",
810 ebus_name_to_pil[i].pil);
812 hdlp->ih_pri = ebus_name_to_pil[i].pil;
827 "PIL %d\n", ebus_device_type_to_pil[i].
828 string, ebus_device_type_to_pil[i].pil);
830 hdlp->ih_pri = ebus_device_type_to_pil[i].pil;
840 * for the PIL
[all...] |
| /onnv/onnv-gate/usr/src/uts/sun4u/montecarlo/io/ |
| acebus.c | 659 uint32_t pil; member in struct:ebus_string_to_pil
707 * This is a hack to set the PIL for the devices under ebus.
710 * Lastly we default a PIL level of 1.
720 DBG2(D_INTR, ebus_p, "child name %s; match PIL %d\n",
722 acebus_name_to_pil[i].pil);
724 hdlp->ih_pri = acebus_name_to_pil[i].pil;
739 "Device type %s; match PIL %d\n",
741 acebus_device_type_to_pil[i].pil);
743 hdlp->ih_pri = acebus_device_type_to_pil[i].pil;
753 * for the PIL
[all...] |
| /onnv/onnv-gate/usr/src/uts/sun4v/io/ |
| cnex.c | 611 int rv, idx, pil; local
683 /* Pick a PIL on the basis of the channel's devclass */
684 for (idx = 0, pil = PIL_3; idx < CNEX_MAX_DEVS; idx++) {
686 pil = cnex_class_to_intr[idx].pil;
692 if (add_ivintr(iinfo->icookie, pil, (intrfunc)cnex_intr_wrapper,
734 (void) rem_ivintr(iinfo->icookie, pil);
800 int rv, idx, pil; local
877 /* Pick a PIL on the basis of the channel's devclass */
878 for (idx = 0, pil = PIL_3; idx < CNEX_MAX_DEVS; idx++)
[all...] |
| vnex.c | 48 * Vnex name to pil map
57 uint32_t pil; member in struct:vnex_pil_map
394 return (vnex_name_to_pil[i].pil);
398 * if not found pil is 0
|
| /onnv/onnv-gate/usr/src/uts/common/io/ |
| pci_intr_lib.c | 46 /* default class to pil value mapping */
1253 uint32_t pil; local
[all...] |
| /onnv/onnv-gate/usr/src/uts/i86pc/os/ |
| intr.c | 106 * The 'pil' is already set to the appropriate level for rp->r_trapno.
109 hilevel_intr_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, struct regs *rp)
116 ASSERT(pil > LOCK_LEVEL);
118 if (pil == CBE_HIGH_PIL) {
143 ASSERT(nestpil < pil);
171 * Store starting timestamp in CPU structure for this PIL.
173 mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] = now;
175 ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
177 if (pil == 15) {
181 * when this count hits zero do we clear the PIL 15 bit fro
357 uint_t pil, basespl; local
493 uint_t pil; local
528 uint_t pil; local
635 uint_t pil, basespl; local
[all...] |
| /onnv/onnv-gate/usr/src/uts/sun4/io/px/ |
| px_ib.c | 482 px_ib_new_ino_pil(px_ib_t *ib_p, devino_t ino_num, uint_t pil, px_ih_t *ih_p)
493 ipil_p->ipil_pil = pil;
504 if ((ino_p->ino_lopil == 0) || (ino_p->ino_lopil > pil))
505 ino_p->ino_lopil = pil;
514 ushort_t pil = ipil_p->ipil_pil; local
532 if ((--ino_p->ino_ipil_size) && (ino_p->ino_lopil == pil)) {
533 for (next = ino_p->ino_ipil_p, pil = next->ipil_pil;
536 if (pil > next->ipil_pil)
537 pil = next->ipil_pil;
541 * Value stored in pil should be the lowest pil
[all...] |
| px_intr.c | 29 * PIL lookup routine
151 ushort_t pil = ipil_p->ipil_pil; local
156 "ino=%x sysino=%llx pil=%x ih_size=%x ih_lst=%x\n",
190 if (pil <= LOCK_LEVEL)
205 ino_p->ino_claimed |= (1 << pil);
207 /* Interrupt can only be cleared after all pil levels are handled */
208 if (pil != ino_p->ino_lopil)
255 ushort_t pil = ipil_p->ipil_pil; local
264 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: msiq_id =%x ino=%x pil=%x "
398 if (pil <= LOCK_LEVEL
[all...] |
| /onnv/onnv-gate/usr/src/uts/common/io/cardbus/ |
| cardbus_cfg.c | 113 int pil; member in struct:cardbus_name_entry
[all...] |
| /onnv/onnv-gate/usr/src/uts/sun4u/sys/ |
| sysiosbus.h | 362 uint32_t pil; member in struct:sbus_wrapper_arg
|
| /onnv/onnv-gate/usr/src/uts/sun4u/os/ |
| cpr_impl.c | 473 uint_t pil, reset_pil; local
475 pil = getpil();
476 if (pil < XCALL_PIL)
484 setpil(pil);
[all...] |
| /onnv/onnv-gate/usr/src/uts/sun4u/sunfire/sys/ |
| fhc.h | 958 uint_t pil; member in struct:fhcintrspec
|
| /onnv/onnv-gate/usr/src/cmd/mdb/common/modules/genunix/ |
| genunix.c | 3107 uint8_t pil; local
[all...] |
